Neuromorphic architectures: challenges and opportunites in the years to come
|
|
- Shanon Webster
- 6 years ago
- Views:
Transcription
1 Neuromorphic architectures: challenges and opportunites in the years to come Andreas G. Andreou Electrical and Computer Engineering Center for Language and Speech Processing Johns Hopkins University NRI Workshop /18/2009 1
2 Part I: Neuromorphic architectures What did we learn the last 25 years? NRI Workshop /18/2009 2
3 1986: Let the physics do the work! max x ci a+ c i= 1, N i System / Architecture Circuits Devices / Technology i i i i = 0 = 0 1 V () t = I() t dt C i Q I V i = 0 t I D SI n0 exp κ V n GS October 1986 (1st Draft) V t NRI Workshop /18/2009 3
4 circuits: analog, digital and beyond CVDT Continuous-Value Discrete-Time Continuous-Value Continuous-Time CVCT CCD Switched Capacitor Binary digital Multivalue digital Linear and non-linear analog Asynchronous digital Neuron spikes EPSP Anisochronous Pulse Time Modulation DVDT Discrete-Value Discrete-Time Discrete-Value Continuous-Time DVCT P.M. Furth and A.G. Andreou, Comparing the bit-energy of continuous and discrete signal representations, Proceedings of the Fourth Workshop on Physics and Computation (PhysComp96), T.Toffoli, M. Biafore and J. Leao eds., New England Complex Systems Institute, pp , Boston, MA, November NRI Workshop /18/2009 4
5 the energy costs of computing bits DVDT practical limit at 10nm CMOS C = fbw log2 1+ S N CVCT DVDT Landauer (theoretical limit) Power [ J ] BitEnergy Capacity [ bit] NRI Workshop /18/2009 5
6 silicon retina NIPS 91 Chemical synapses Electrical synapses NRI Workshop /18/2009 6
7 the mathematical abstraction of biology 1. Photons to electrons: transduction and amplification I ( x, y ) = β I ( x, y ) Φ( x, y ) in m n ph m n m n 2. Local gain control: source coding I ( x, y ) = I out m n u Iin( xm, yn) I ( x, y ) + ψ I ( x, y ) in m n M, N in i j 3. Spatial filtering: optimal smoothing i x y i x y i x y 2 2 h( m, n) + λ h( m, n) = in( m, n) = 2 out m n h m n i ( x, y ) i ( x, y ) Andreas NRI Workshop G. Andreou 2009 DARPA Monterey Workshop 8/18/2009 Tuesday, August 18,
8 the statistics of natural scenes pdf (log( I)) W. Richards, Lightness scale from image intensity distributions, Applied Optics, vol. 21, no. 14, , PO ( ) N 0.2 O m Rfl*SrfOr*Txtr Image Intensity I = (log( I)) n (log( I )) + n c n m = 12.5 n = 1 I = 3 S NRI Workshop /18/ log( I) P(log( I)) d( I ) = P( O) d( O) 1 PO ( ) N log( I) O = G(log( I )) = N P( x) d( x) 1 Naka-Rushton Equation
9 matching signals to circuits! challenge: matching the wide dynamic range of signals to limited dynamic range of analog computing hardware circuit design problem I I I I I I I p out C = = p p U U + H I = 0.6 na,1.8na U p = 1.2 I = 1.5 na, 3nA H non-linear analog processing to do source coding NRI Workshop /18/2009 9
10 dealing with the dynamic range problem Silicon Retina CCD Camera (210 x 230 pixels) X (6 OPS per pixel for second order smoothing) X (6 OPS per pixel for Laplacian) X (6 OPS per pixel for gain control) X (10 5 OPS per second khz temporal response--) = 5 X 10 4 X 2 x 10 2 X OPS with 50mW total power dissipation at 5 Volts power supply Subthreshold CMOS 560,000 transistors, era 1995 NRI Workshop /18/
11 embedded analog computing in digital memories exploiting problem statistics! minimal complexity CMOS circuits Andreas NRI Workshop G. Andreou 2009 DARPA Monterey Workshop Tuesday, 8/18/2009August 18,
12 precision on demand architecture Andreas NRI Workshop G. Andreou 2009 DARPA Monterey Workshop Tuesday, 8/18/2009August 18,
13 dealing with device mismatch again ISCAS 94 Floating Gate Adaptation Andreas NRI Workshop G. Andreou 2009 DARPA Monterey Workshop Tuesday, 8/18/2009August 18,
14 Part II: What is the real problem? Physical world 3 dimensional world s problems N dimensional NRI Workshop /18/
15 natural and synthetic computing structures The Brain IBM Blue Gene/L exist in three dimensional physical space but can deal with problems in hyper dimensional spaces NRI Workshop /18/
16 visual representation of the world through cortical maps Multiple stimulus modalities such as orientation, spatial frequency, ocular dominance are mapped into 2D+δ patches on the surface of the cortex (V1) Conflicting constraints Maximize coverage every location in the physical space is mapped to all possible combinations of stimulus modalities- Minimize wiring length and metabolic costs neurons with similar stimulus response should exist in closed proximity on the cortical surface (smoothness of mapping). The ice-cube model for stimulus representation in V1 (Hubel and Wiesel 1977) suggests stimulus modalities in orthogonal dimensions orientation ocular dominance NRI Workshop /18/
17 natural and synthetic computing structures: another view The Brain IBM Blue Gene/L 15W 125 KW 5 racks NRI Workshop /18/
18 the energy costs of communication 3D CMOS a. 10nm CMOS inverter b. 100nm CMOS inverter c. Intra die 1cm metal line d. Electrical chip to chip link e. Optical chip to chip link f. FireWire link g. Wireless chip to chip link h. Ultra Wide Band radio M.A Marwick and A.G. Andreou, Retinomorphic system design in three dimensional SOI-CMOS, Proceedings of the 2006 IEEE International Symposium on Circuits and Systems. NRI Workshop /18/
19 3D silicon cortex (a dynamical system approach) Supply Voltage 1.5V Technology MITLL 0.18μm 3DL1 Array size Spatial Processing 8 orient Filter time 3-4ns External Communications ADER protocol (2 phase async.) Internal Communications 4 phase asynchronous Dynamic Range 6 bit Minimum Frame Rate 300Hz Maximum Frame Rate 20kHz Andreas NRI Workshop G. Andreou 2009 DARPA Monterey Workshop Tuesday, 8/18/2009August 18,
20 Towards Field Programmable Spiking Array in 3D CMOS Results gold din green din ack red dout purple dout ack Block Diagram 5 asynchronous handshake buffers in each path (4 deep FIFO + 1 MUX) Utilizes all three tiers Handshake between tiers data_i ctrl_i d_b_o d_a_o Tier C Tier B Tier A Andreas NRI Workshop G. Andreou 2009 DARPA Monterey Workshop Tuesday, 8/18/2009August 18,
21 Part III: Final remarks Group B: Andreou, Dally, Roukes, Cornwell, Nair, Simon NRI Workshop /18/
22 Commodity The Tyrannies Compatibility NRI Workshop /18/
23 Nano to the rescue Improving memory density Makes higher Bytes per FLOP economically feasible Improves the capacity at each level NRI Workshop /18/
24 On hardware, algorithms and architectures Computational and energy efficiency can only be achieved through co-development of algorithms to application specific, reconfigurable architectures. NRI Workshop /18/
25 summary Early 80s: Carver Mead s neuromorphic manifesto towards new ways of computing inspired by biology device physics based approach exploit statistics of the problem parallel distributed processing processors in memory adaptation learning analog circuits Late 90s: Some neuromorphic apostles took the wrong turn and got lost on the way. Today: Good news! The problems of the world have not yet been solved, and the apostles are 15 years older and hopefully wiser! NRI Workshop /18/
Neuromorphic computing with Memristive devices. NCM group
Neuromorphic computing with Memristive devices NCM group Why neuromorphic? New needs for computing Recognition, Mining, Synthesis (Intel) Increase of Fault (nanoscale engineering) SEMICONDUCTOR TECHNOLOGY
More information3/10/2013. Lecture #1. How small is Nano? (A movie) What is Nanotechnology? What is Nanoelectronics? What are Emerging Devices?
EECS 498/598: Nanocircuits and Nanoarchitectures Lecture 1: Introduction to Nanotelectronic Devices (Sept. 5) Lectures 2: ITRS Nanoelectronics Road Map (Sept 7) Lecture 3: Nanodevices; Guest Lecture by
More informationTowards Eyes for Sensor Network Systems
Towards Eyes for Sensor Network Systems Andreas G. Andreou Electrical and Computer Engineering and Whitaker Biomedical Engineering Institute Johns Hopkins University http://www.ece.jhu.edu/faculty/andreou/aga/index.htm
More informationPost Von Neumann Computing
Post Von Neumann Computing Matthias Kaiserswerth Hasler Stiftung (formerly IBM Research) 1 2014 IBM Corporation Foundation Purpose Support information and communication technologies (ICT) to advance Switzerland
More informationNovel VLSI Implementation for Triplet-based Spike-Timing Dependent Plasticity
Novel LSI Implementation for Triplet-based Spike-Timing Dependent Plasticity Mostafa Rahimi Azghadi, Omid Kavehei, Said Al-Sarawi, Nicolangelo Iannella, and Derek Abbott Centre for Biomedical Engineering,
More informationAddressing Challenges in Neuromorphic Computing with Memristive Synapses
Addressing Challenges in Neuromorphic Computing with Memristive Synapses Vishal Saxena 1, Xinyu Wu 1 and Maria Mitkova 2 1 Analog Mixed-Signal and Photonic IC (AMPIC) Lab 2 Nanoionic Materials and Devices
More informationA Gray Code Based Time-to-Digital Converter Architecture and its FPGA Implementation
A Gray Code Based Time-to-Digital Converter Architecture and its FPGA Implementation Congbing Li Haruo Kobayashi Gunma University Gunma University Kobayashi Lab Outline Research Objective & Background
More informationNEUROMORPHIC COMPUTING WITH MAGNETO-METALLIC NEURONS & SYNAPSES: PROSPECTS AND PERSPECTIVES
NEUROMORPHIC COMPUTING WITH MAGNETO-METALLIC NEURONS & SYNAPSES: PROSPECTS AND PERSPECTIVES KAUSHIK ROY ABHRONIL SENGUPTA, KARTHIK YOGENDRA, DELIANG FAN, SYED SARWAR, PRIYA PANDA, GOPAL SRINIVASAN, JASON
More informationFloating Point Representation and Digital Logic. Lecture 11 CS301
Floating Point Representation and Digital Logic Lecture 11 CS301 Administrative Daily Review of today s lecture w Due tomorrow (10/4) at 8am Lab #3 due Friday (9/7) 1:29pm HW #5 assigned w Due Monday 10/8
More informationControl gates as building blocks for reversible computers
Control gates as building blocks for reversible computers A. De Vos 1, B. Desoete 2, F. Janiak 3, and A. Nogawski 3 1 Universiteit Gent and Imec v.z.w., B-9000 Gent, Belgium 2 Universiteit Gent, B-9000
More informationMark Redekopp, All rights reserved. Lecture 1 Slides. Intro Number Systems Logic Functions
Lecture Slides Intro Number Systems Logic Functions EE 0 in Context EE 0 EE 20L Logic Design Fundamentals Logic Design, CAD Tools, Lab tools, Project EE 357 EE 457 Computer Architecture Using the logic
More informationSynaptic Devices and Neuron Circuits for Neuron-Inspired NanoElectronics
Synaptic Devices and Neuron Circuits for Neuron-Inspired NanoElectronics Byung-Gook Park Inter-university Semiconductor Research Center & Department of Electrical and Computer Engineering Seoul National
More informationWHY BIOLOGY CAN AND SILICON... CAN T
AND THE COMPUTER WHY BIOLOGY CAN AND SILICON... CAN T Valeriu Beiu 1 Structure Motivation 101... on Brain s single ion transistors et al. Power device(s) wire(s) system Reliability device(s) wire(s) system
More informationOutline. Neural dynamics with log-domain integrator circuits. Where it began Biophysics of membrane channels
Outline Neural dynamics with log-domain integrator circuits Giacomo Indiveri Neuromorphic Cognitive Systems group Institute of Neuroinformatics niversity of Zurich and ETH Zurich Dynamics of Multi-function
More informationPerformance Enhancement of Reversible Binary to Gray Code Converter Circuit using Feynman gate
Performance Enhancement of Reversible Binary to Gray Code Converter Circuit using Feynman gate Kamal Prakash Pandey 1, Pradumn Kumar 2, Rakesh Kumar Singh 3 1, 2, 3 Department of Electronics and Communication
More informationKINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK
KINGS COLLEGE OF ENGINEERING DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING QUESTION BANK SUBJECT CODE: EC 1354 SUB.NAME : VLSI DESIGN YEAR / SEMESTER: III / VI UNIT I MOS TRANSISTOR THEORY AND
More informationIntroduction. Previous work has shown that AER can also be used to construct largescale networks with arbitrary, configurable synaptic connectivity.
Introduction The goal of neuromorphic engineering is to design and implement microelectronic systems that emulate the structure and function of the brain. Address-event representation (AER) is a communication
More informationCenter for Spintronic Materials, Interfaces, and Novel Architectures. Spintronics Enabled Efficient Neuromorphic Computing: Prospects and Perspectives
Center for Spintronic Materials, Interfaces, and Novel Architectures Spintronics Enabled Efficient Neuromorphic Computing: Prospects and Perspectives KAUSHIK ROY ABHRONIL SENGUPTA, KARTHIK YOGENDRA, DELIANG
More informationE40M Review - Part 1
E40M Review Part 1 Topics in Part 1 (Today): KCL, KVL, Power Devices: V and I sources, R Nodal Analysis. Superposition Devices: Diodes, C, L Time Domain Diode, C, L Circuits Topics in Part 2 (Wed): MOSFETs,
More informationTransistor Implementation of Reversible Comparator Circuit Using Low Power Technique
Transistor Implementation of Reversible Comparator Circuit Using Low Power Technique Madhina Basha, V.N.Lakshmana Kumar Department of ECE, MVGR COLLEGE OF ENGINEERING Visakhapatnam, A.P, INDIA Abstract:
More informationMagnetic tunnel junction beyond memory from logic to neuromorphic computing WANJUN PARK DEPT. OF ELECTRONIC ENGINEERING, HANYANG UNIVERSITY
Magnetic tunnel junction beyond memory from logic to neuromorphic computing WANJUN PARK DEPT. OF ELECTRONIC ENGINEERING, HANYANG UNIVERSITY Magnetic Tunnel Junctions (MTJs) Structure High density memory
More informationLast Lecture. Power Dissipation CMOS Scaling. EECS 141 S02 Lecture 8
EECS 141 S02 Lecture 8 Power Dissipation CMOS Scaling Last Lecture CMOS Inverter loading Switching Performance Evaluation Design optimization Inverter Sizing 1 Today CMOS Inverter power dissipation» Dynamic»
More informationA 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic- Compatible Embedded Flash Memory Technology
A 68 Parallel Row Access Neuromorphic Core with 22K Multi-Level Synapses Based on Logic- Compatible Embedded Flash Memory Technology M. Kim 1, J. Kim 1, G. Park 1, L. Everson 1, H. Kim 1, S. Song 1,2,
More informationEE115C Winter 2017 Digital Electronic Circuits. Lecture 6: Power Consumption
EE115C Winter 2017 Digital Electronic Circuits Lecture 6: Power Consumption Four Key Design Metrics for Digital ICs Cost of ICs Reliability Speed Power EE115C Winter 2017 2 Power and Energy Challenges
More informationPower Dissipation. Where Does Power Go in CMOS?
Power Dissipation [Adapted from Chapter 5 of Digital Integrated Circuits, 2003, J. Rabaey et al.] Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit
More informationDesign Considerations for Integrated Semiconductor Control Electronics for a Large-scale Solid State Quantum Processor
Design Considerations for Integrated Semiconductor Control Electronics for a Large-scale Solid State Quantum Processor Hendrik Bluhm Andre Kruth Lotte Geck Carsten Degenhardt 1 0 Ψ 1 Quantum Computing
More informationJ. Lazzaro, S. Ryckebusch, M.A. Mahowald, and C. A. Mead California Institute of Technology Pasadena, CA 91125
WINNER-TAKE-ALL NETWORKS OF O(N) COMPLEXITY J. Lazzaro, S. Ryckebusch, M.A. Mahowald, and C. A. Mead California Institute of Technology Pasadena, CA 91125 ABSTRACT We have designed, fabricated, and tested
More information1 Introduction The Separation of Independent Sources (SIS) assumes that some unknown but independent temporal signals propagate through a mixing and/o
Appeared in IEEE Trans. on Circuits and Systems, vol. 42, no. 11, pp. 748-751, November 95 c Implementation and Test Results of a Chip for The Separation of Mixed Signals Ammar B. A. Gharbi and Fathi M.
More informationMicroelectronics Part 1: Main CMOS circuits design rules
GBM8320 Dispositifs Médicaux telligents Microelectronics Part 1: Main CMOS circuits design rules Mohamad Sawan et al. Laboratoire de neurotechnologies Polystim! http://www.cours.polymtl.ca/gbm8320/! med-amine.miled@polymtl.ca!
More informationISSN (PRINT): , (ONLINE): , VOLUME-4, ISSUE-10,
A NOVEL DOMINO LOGIC DESIGN FOR EMBEDDED APPLICATION Dr.K.Sujatha Associate Professor, Department of Computer science and Engineering, Sri Krishna College of Engineering and Technology, Coimbatore, Tamilnadu,
More informationChapter 1 :: From Zero to One
Chapter 1 :: From Zero to One Digital Design and Computer Architecture David Money Harris and Sarah L. Harris Copyright 2007 Elsevier 1- Chapter 1 :: Topics Background The Game Plan The Art of Managing
More informationVidyalankar S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution
. (a) (i) ( B C 5) H (A 2 B D) H S.E. Sem. III [CMPN] Digital Logic Design and Analysis Prelim Question Paper Solution ( B C 5) H (A 2 B D) H = (FFFF 698) H (ii) (2.3) 4 + (22.3) 4 2 2. 3 2. 3 2 3. 2 (2.3)
More informationE40M Capacitors. M. Horowitz, J. Plummer, R. Howe
E40M Capacitors 1 Reading Reader: Chapter 6 Capacitance A & L: 9.1.1, 9.2.1 2 Why Are Capacitors Useful/Important? How do we design circuits that respond to certain frequencies? What determines how fast
More informationESE570 Spring University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals
University of Pennsylvania Department of Electrical and System Engineering Digital Integrated Cicruits AND VLSI Fundamentals ESE570, Spring 2018 Final Monday, Apr 0 5 Problems with point weightings shown.
More informationConstruction of a reconfigurable dynamic logic cell
PRAMANA c Indian Academy of Sciences Vol. 64, No. 3 journal of March 2005 physics pp. 433 441 Construction of a reconfigurable dynamic logic cell K MURALI 1, SUDESHNA SINHA 2 and WILLIAM L DITTO 3 1 Department
More informationIntegrated Circuit Implementation of a Compact Discrete-Time Chaos Generator
Analog Integrated Circuits and Signal Processing, 46, 275 280, 2006 c 2006 Springer Science + Business Media, Inc. Manufactured in The Netherlands. Integrated Circuit Implementation of a Compact Discrete-Time
More informationSemiconductor memories
Semiconductor memories Semiconductor Memories Data in Write Memory cell Read Data out Some design issues : How many cells? Function? Power consuption? Access type? How fast are read/write operations? Semiconductor
More informationEfficient electron transport on helium with silicon integrated circuits
Efficient electron transport on helium with silicon integrated circuits - - + - - Forrest Bradbury 1 and Maika Takita 1, Kevin Eng 2, Tom M Gurrieri 2, Kathy J Wilkel 2, Stephen A Lyon 1 1 Princeton University
More informationThe N3XT Technology for. Brain-Inspired Computing
The N3XT Technology for Brain-Inspired Computing SystemX Alliance 27..8 Department of Electrical Engineering 25.4.5 2 25.4.5 Source: Google 3 25.4.5 Source: vrworld.com 4 25.4.5 Source: BDC Stanford Magazine
More informationChapter 7. Sequential Circuits Registers, Counters, RAM
Chapter 7. Sequential Circuits Registers, Counters, RAM Register - a group of binary storage elements suitable for holding binary info A group of FFs constitutes a register Commonly used as temporary storage
More informationDesign and Implementation of Carry Adders Using Adiabatic and Reversible Logic Gates
Design and Implementation of Carry Adders Using Adiabatic and Reversible Logic Gates B.BharathKumar 1, ShaikAsra Tabassum 2 1 Research Scholar, Dept of ECE, Lords Institute of Engineering & Technology,
More informationMemory and computing beyond CMOS
Memory and computing beyond CMOS Dipartimento di Elettronica, Informazione e Bioingegneria Politecnico di Milano daniele.ielmini@polimi.it Outline 2 Introduction What is CMOS? What comes after CMOS? Example:
More informationEE241 - Spring 2003 Advanced Digital Integrated Circuits
EE241 - Spring 2003 Advanced Digital Integrated Circuits Lecture 16 Energy-Recovery Circuits SOI Technology and Circuits Optimal EDP Contours 1 Leakage and Switching ELk 2 = ESw Opt L ln d K tech α avg
More informationA brain-inspired neuromorphic architecture for robust neural computation
A brain-inspired neuromorphic architecture for robust neural computation Fabio Stefanini and Giacomo Indiveri Institute of Neuroinformatics University of Zurich and ETH Zurich BIC Workshop @ ISCA40 June
More informationVectorized 128-bit Input FP16/FP32/ FP64 Floating-Point Multiplier
Vectorized 128-bit Input FP16/FP32/ FP64 Floating-Point Multiplier Espen Stenersen Master of Science in Electronics Submission date: June 2008 Supervisor: Per Gunnar Kjeldsberg, IET Co-supervisor: Torstein
More informationWhere Does Power Go in CMOS?
Power Dissipation Where Does Power Go in CMOS? Dynamic Power Consumption Charging and Discharging Capacitors Short Circuit Currents Short Circuit Path between Supply Rails during Switching Leakage Leaking
More informationFrom Physics to Logic
From Physics to Logic This course aims to introduce you to the layers of abstraction of modern computer systems. We won t spend much time below the level of bits, bytes, words, and functional units, but
More informationLecture Notes 2 Charge-Coupled Devices (CCDs) Part I. Basic CCD Operation CCD Image Sensor Architectures Static and Dynamic Analysis
Lecture Notes 2 Charge-Coupled Devices (CCDs) Part I Basic CCD Operation CCD Image Sensor Architectures Static and Dynamic Analysis Charge Well Capacity Buried channel CCD Transfer Efficiency Readout Speed
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 19: March 29, 2018 Memory Overview, Memory Core Cells Today! Charge Leakage/Charge Sharing " Domino Logic Design Considerations! Logic Comparisons!
More informationEECS150 - Digital Design Lecture 15 SIFT2 + FSM. Recap and Outline
EECS150 - Digital Design Lecture 15 SIFT2 + FSM Oct. 15, 2013 Prof. Ronald Fearing Electrical Engineering and Computer Sciences University of California, Berkeley (slides courtesy of Prof. John Wawrzynek)
More informationUniversity of Toronto Faculty of Applied Science and Engineering Final Examination
University of Toronto Faculty of Applied Science and Engineering Final Examination ECE 24S - Digital Systems Examiner: Belinda Wang, Jianwen Zhu 2: - 4:3pm, April 26th, 24 Duration: 5 minutes (2.5 hours)
More informationLEADING THE EVOLUTION OF COMPUTE MARK KACHMAREK HPC STRATEGIC PLANNING MANAGER APRIL 17, 2018
LEADING THE EVOLUTION OF COMPUTE MARK KACHMAREK HPC STRATEGIC PLANNING MANAGER APRIL 17, 2018 INTEL S RESEARCH EFFORTS COMPONENTS RESEARCH INTEL LABS ENABLING MOORE S LAW DEVELOPING NOVEL INTEGRATION ENABLING
More informationSingle Electron Devices and Circuits
Single Electron Devices and Circuits M. F. Gonzalez-Zalba 1, S. Kaxiras 2, R.D. Levine 3, F. Remacle 4, S. Rogge 5, M. Sanquer 6 1 Hitachi Cambridge Laboratory, Cambridge, UK 2 Division of Computer Systems,
More informationChapter 8. Low-Power VLSI Design Methodology
VLSI Design hapter 8 Low-Power VLSI Design Methodology Jin-Fu Li hapter 8 Low-Power VLSI Design Methodology Introduction Low-Power Gate-Level Design Low-Power Architecture-Level Design Algorithmic-Level
More informationLecture 6 Power Zhuo Feng. Z. Feng MTU EE4800 CMOS Digital IC Design & Analysis 2010
EE4800 CMOS Digital IC Design & Analysis Lecture 6 Power Zhuo Feng 6.1 Outline Power and Energy Dynamic Power Static Power 6.2 Power and Energy Power is drawn from a voltage source attached to the V DD
More informationESE 570: Digital Integrated Circuits and VLSI Fundamentals
ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 21: April 4, 2017 Memory Overview, Memory Core Cells Penn ESE 570 Spring 2017 Khanna Today! Memory " Classification " ROM Memories " RAM Memory
More informationLecture 7: Logic design. Combinational logic circuits
/24/28 Lecture 7: Logic design Binary digital circuits: Two voltage levels: and (ground and supply voltage) Built from transistors used as on/off switches Analog circuits not very suitable for generic
More informationHow to outperform a supercomputer with neuromorphic chips
How to outperform a supercomputer with neuromorphic chips Kwabena Boahen Stanford Bioengineering boahen@stanford.edu Telluride Acknowledgements Paul Merolla John Arthur Joseph Kai Lin Hynna BrainsInSilicon.stanford.edu
More informationAn Optical Parallel Adder Towards Light Speed Data Processing
An Optical Parallel Adder Towards Light Speed Data Processing Tohru ISHIHARA, Akihiko SHINYA, Koji INOUE, Kengo NOZAKI and Masaya NOTOMI Kyoto University NTT Nanophotonics Center / NTT Basic Research Laboratories
More informationνmos Enhanced Differential Current-Switch Threshold Logic Gates
νmos Enhanced Differential Current-Switch hreshold Logic Gates K.C. Li ( ), M. Padure ( ), S.D. Cotofana ( ) ( ) Delft University of echnology, he Netherlands Mekelweg 4, 2628 CD, Delft, he Netherlands
More informationAn Analog-digital CMOS circuit for motion detection based on direction-selective neural networks
An Analog-digital CMOS circuit for motion detection based on direction-selective neural networks Masato Koutani, Tetsuya Asai, and Yoshihito Amemiya Department of Electrical Engineering, Hokkaido University
More informationEE 466/586 VLSI Design. Partha Pande School of EECS Washington State University
EE 466/586 VLSI Design Partha Pande School of EECS Washington State University pande@eecs.wsu.edu Lecture 8 Power Dissipation in CMOS Gates Power in CMOS gates Dynamic Power Capacitance switching Crowbar
More informationMixed Analog-Digital VLSI Circuits & Systems Laboratory
CORNELL U N I V E R S I T Y School of Electrical and Computer Engineering Mixed Analog-Digital VLSI Circuits & Systems Laboratory Our research presently revolves around two major themes: Devising new circuit
More information2.1. Unit 2. Digital Circuits (Logic)
2.1 Unit 2 Digital Circuits (Logic) 2.2 Moving from voltages to 1's and 0's ANALOG VS. DIGITAL volts volts 2.3 Analog signal Signal Types Continuous time signal where each voltage level has a unique meaning
More information! Charge Leakage/Charge Sharing. " Domino Logic Design Considerations. ! Logic Comparisons. ! Memory. " Classification. " ROM Memories.
ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 9: March 9, 8 Memory Overview, Memory Core Cells Today! Charge Leakage/ " Domino Logic Design Considerations! Logic Comparisons! Memory " Classification
More informationCSE370: Introduction to Digital Design
CSE370: Introduction to Digital Design Course staff Gaetano Borriello, Brian DeRenzi, Firat Kiyak Course web www.cs.washington.edu/370/ Make sure to subscribe to class mailing list (cse370@cs) Course text
More informationTiming Issues. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić. January 2003
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolić Timing Issues January 2003 1 Synchronous Timing CLK In R Combinational 1 R Logic 2 C in C out Out 2
More informationAdministrative Stuff
EE141- Spring 2004 Digital Integrated Circuits Lecture 30 PERSPECTIVES 1 Administrative Stuff Homework 10 posted just for practice. No need to turn in (hw 9 due today). Normal office hours next week. HKN
More informationPower Minimization of Full Adder Using Reversible Logic
I J C T A, 9(4), 2016, pp. 13-18 International Science Press Power Minimization of Full Adder Using Reversible Logic S. Anandhi 1, M. Janaki Rani 2, K. Manivannan 3 ABSTRACT Adders are normally used for
More informationGMU, ECE 680 Physical VLSI Design 1
ECE680: Physical VLSI Design Chapter VII Timing Issues in Digital Circuits (chapter 10 in textbook) GMU, ECE 680 Physical VLSI Design 1 Synchronous Timing (Fig. 10 1) CLK In R Combinational 1 R Logic 2
More informationDesign and Synthesis of Sequential Circuit Using Reversible Logic
ISSN: 2278 0211 (Online) Design and Synthesis of Sequential Circuit Using Reversible Logic Mr. Sandesh.N.G PG Student, VLSI Design and Embedded System, B.G.S. Institute of Technology, B.G.Nagar, Karnataka,
More informationDigital Logic. CS211 Computer Architecture. l Topics. l Transistors (Design & Types) l Logic Gates. l Combinational Circuits.
CS211 Computer Architecture Digital Logic l Topics l Transistors (Design & Types) l Logic Gates l Combinational Circuits l K-Maps Figures & Tables borrowed from:! http://www.allaboutcircuits.com/vol_4/index.html!
More informationCS/COE0447: Computer Organization
Logic design? CS/COE0447: Computer Organization and Assembly Language Logic Design Review Digital hardware is implemented by way of logic design Digital circuits process and produce two discrete values:
More informationMemory, Latches, & Registers
Memory, Latches, & Registers 1) Structured Logic Arrays 2) Memory Arrays 3) Transparent Latches 4) How to save a few bucks at toll booths 5) Edge-triggered Registers L13 Memory 1 General Table Lookup Synthesis
More informationOver Current Protection Circuits Voltage controlled DC-AC Inverters Maximum operating temperature of 175 C
Description xj SiC Series 8mW - 12V SiC Normally-On JFET UJN128Z Die Form United Silicon Carbide, Inc offers the xj series of high-performance SiC normally-on JFET transistors. This series exhibits ultra-low
More informationDesign for Manufacturability and Power Estimation. Physical issues verification (DSM)
Design for Manufacturability and Power Estimation Lecture 25 Alessandra Nardi Thanks to Prof. Jan Rabaey and Prof. K. Keutzer Physical issues verification (DSM) Interconnects Signal Integrity P/G integrity
More informationA Novel LUT Using Quaternary Logic
A Novel LUT Using Quaternary Logic 1*GEETHA N S 2SATHYAVATHI, N S 1Department of ECE, Applied Electronics, Sri Balaji Chockalingam Engineering College, Arani,TN, India. 2Assistant Professor, Department
More informationCS/COE0447: Computer Organization
CS/COE0447: Computer Organization and Assembly Language Logic Design Review Sangyeun Cho Dept. of Computer Science Logic design? Digital hardware is implemented by way of logic design Digital circuits
More informationMagnetic core memory (1951) cm 2 ( bit)
Magnetic core memory (1951) 16 16 cm 2 (128 128 bit) Semiconductor Memory Classification Read-Write Memory Non-Volatile Read-Write Memory Read-Only Memory Random Access Non-Random Access EPROM E 2 PROM
More informationIntroduction to Computer Engineering. CS/ECE 252, Spring 2017 Rahul Nayar Computer Sciences Department University of Wisconsin Madison
Introduction to Computer Engineering CS/ECE 252, Spring 2017 Rahul Nayar Computer Sciences Department University of Wisconsin Madison Chapter 3 Digital Logic Structures Slides based on set prepared by
More informationCMPE12 - Notes chapter 1. Digital Logic. (Textbook Chapter 3)
CMPE12 - Notes chapter 1 Digital Logic (Textbook Chapter 3) Transistor: Building Block of Computers Microprocessors contain TONS of transistors Intel Montecito (2005): 1.72 billion Intel Pentium 4 (2000):
More informationDelay and Energy Consumption Analysis of Conventional SRAM
World Academy of Science, Engineering and Technology 13 8 Delay and Energy Consumption Analysis of Conventional SAM Arash Azizi-Mazreah, Mohammad T. Manzuri Shalmani, Hamid Barati, and Ali Barati Abstract
More informationPARALLEL DIGITAL-ANALOG CONVERTERS
CMOS Analog IC Design Page 10.2-1 10.2 - PARALLEL DIGITAL-ANALOG CONVERTERS CLASSIFICATION OF DIGITAL-ANALOG CONVERTERS CMOS Analog IC Design Page 10.2-2 CURRENT SCALING DIGITAL-ANALOG CONVERTERS GENERAL
More informationDigital Circuits. 1. Inputs & Outputs are quantized at two levels. 2. Binary arithmetic, only digits are 0 & 1. Position indicates power of 2.
Digital Circuits 1. Inputs & Outputs are quantized at two levels. 2. inary arithmetic, only digits are 0 & 1. Position indicates power of 2. 11001 = 2 4 + 2 3 + 0 + 0 +2 0 16 + 8 + 0 + 0 + 1 = 25 Digital
More informationTilt-aftereffect and adaptation of V1 neurons
Tilt-aftereffect and adaptation of V1 neurons Dezhe Jin Department of Physics The Pennsylvania State University Outline The tilt aftereffect (TAE) Classical model of neural basis of TAE Neural data on
More informationCSE140L: Components and Design Techniques for Digital Systems Lab. FSMs. Instructor: Mohsen Imani. Slides from Tajana Simunic Rosing
CSE140L: Components and Design Techniques for Digital Systems Lab FSMs Instructor: Mohsen Imani Slides from Tajana Simunic Rosing Source: Vahid, Katz 1 FSM design example Moore vs. Mealy Remove one 1 from
More informationNPSAT1 Solar Cell Measurement System
NPSAT1 Solar Cell Measurement System Presented by Captain John Salmon, USMC Space Systems Academic Group 777 Dyer Rd., Bldg. 233 Code (SP/Sd), Rm. 125 Monterey, CA 93943 (831) 656-7521 Topics NPSAT1 Overview
More informationVHDL DESIGN AND IMPLEMENTATION OF C.P.U BY REVERSIBLE LOGIC GATES
VHDL DESIGN AND IMPLEMENTATION OF C.P.U BY REVERSIBLE LOGIC GATES 1.Devarasetty Vinod Kumar/ M.tech,2. Dr. Tata Jagannadha Swamy/Professor, Dept of Electronics and Commn. Engineering, Gokaraju Rangaraju
More informationDEPFET sensors development for the Pixel Detector of BELLE II
DEPFET sensors development for the Pixel Detector of BELLE II 13 th Topical Seminar on Innovative Particle and Radiation Detectors (IPRD13) 7 10 October 2013, Siena, Italy Paola Avella for the DEPFET collaboration
More informationLearning on Silicon: Overview
Learning on Silicon: Overview Gert Cauwenberghs Johns Hopkins University gert@jhu.edu 520.776 Learning on Silicon http://bach.ece.jhu.edu/gert/courses/776 Learning on Silicon: Overview Adaptive Microsystems
More informationECE321 Electronics I
ECE321 Electronics I Lecture 1: Introduction to Digital Electronics Payman Zarkesh-Ha Office: ECE Bldg. 230B Office hours: Tuesday 2:00-3:00PM or by appointment E-mail: payman@ece.unm.edu Slide: 1 Textbook
More informationToday. ESE532: System-on-a-Chip Architecture. Energy. Message. Preclass Challenge: Power. Energy Today s bottleneck What drives Efficiency of
ESE532: System-on-a-Chip Architecture Day 22: April 10, 2017 Today Today s bottleneck What drives Efficiency of Processors, FPGAs, accelerators 1 2 Message dominates Including limiting performance Make
More informationLogic. Intro to Neuroscence: Neuromorphic Engineering 12/9/2013. (c) S. Liu and T. Delbruck, Inst. of Neuroinformatics, UZH-ETH Zurich 1
Introductory Course in Neuroscience Neuromorphic Shih-Chii Liu Inst. of Neuroinformatics http://www.ini.uzh.ch/~shih/wiki/doku.php?id=introneuro What is neuromorphic engineering? It consists of embodying
More informationClock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements.
1 2 Introduction Clock signal in digital circuit is responsible for synchronizing the transfer to the data between processing elements. Defines the precise instants when the circuit is allowed to change
More informationMachine Learning. Neural Networks. (slides from Domingos, Pardo, others)
Machine Learning Neural Networks (slides from Domingos, Pardo, others) Human Brain Neurons Input-Output Transformation Input Spikes Output Spike Spike (= a brief pulse) (Excitatory Post-Synaptic Potential)
More informationA High-Yield Area-Power Efficient DWT Hardware for Implantable Neural Interface Applications
Neural Engineering 27 A High-Yield Area-Power Efficient DWT Hardware for Implantable Neural Interface Applications Awais M. Kamboh, Andrew Mason, Karim Oweiss {Kambohaw, Mason, Koweiss} @msu.edu Department
More informationMOS Transistors Models
MOS Transistors Models Andreas G. Andreou Pedro Julian Electrical and Computer Engineering Johns Hopkins University http://andreoulab.net The MOS transistor Levels of Abstraction- Model Equations If V
More informationEE241 - Spring 2001 Advanced Digital Integrated Circuits
EE241 - Spring 21 Advanced Digital Integrated Circuits Lecture 12 Low Power Design Self-Resetting Logic Signals are pulses, not levels 1 Self-Resetting Logic Sense-Amplifying Logic Matsui, JSSC 12/94 2
More informationCMOS Inverter. Performance Scaling
Announcements Exam #2 regrade requests due today. Homework #8 due today. Final Exam: Th June 12, 8:30 10:20am, CMU 120 (extension to 11:20am requested). Grades available for viewing via Catalyst. CMOS
More informationEE241 - Spring 2006 Advanced Digital Integrated Circuits
EE241 - Spring 2006 Advanced Digital Integrated Circuits Lecture 20: Asynchronous & Synchronization Self-timed and Asynchronous Design Functions of clock in synchronous design 1) Acts as completion signal
More information