2.1. Unit 2. Digital Circuits (Logic)

Transcription

1 2.1 Unit 2 Digital Circuits (Logic)

2 2.2 Moving from voltages to 1's and 0's ANALOG VS. DIGITAL

3 volts volts 2.3 Analog signal Signal Types Continuous time signal where each voltage level has a unique meaning Most information types are inherently analog Digital signal Continuous signal where voltage levels are mapped into 2 ranges meaning 0 or 1 Possible to convert a single analog signal to a set of digital signals Threshold Analog time Digital time

4 Logic 0 Illegal Logic Signals and Meaning Analog Digital 5.0 V 5.0 V 2.0 V Threshold Range 0.8 V 0.0 V Each voltage value has unique meaning 0.0 V Each voltage maps to '0' or '1' (There is a small illegal range where meaning is undefined since threshold can vary based on temperature, small variations in manufacturing, etc.)

5 2.5 Analog vs. Digital USC students used to program analog computers!

6 2.6 A Brief History COMPUTERS AND SWITCHING TECHNOLOGY

7 2.7 Electronic Computers Replaced mechanical computation engines Electronic computers require some kind of "switching" technology Initially that was the vacuum tube 1945 ENIAC was one of the first, fully electronic computers Used thousands of vacuum tubes as fundamental switching (on/off) technology Weighed 30 tons, required 15,000 square feet, and maximum size number was 10 decimal digits (i.e. ±9,999,999,999) Still required some patch panels (wire plugs) to configure it

8 2.8 Vacuum Tube Technology Digital, electronic computers use some sort of voltage controlled switch (on/off) Looks like a light bulb Usually 3 nodes 1 node serves as the switch value allowing current to flow between the other 2 nodes (on) or preventing current flow between the other 2 nodes (off) Example: if the switch input voltage is 5V, then current is allowed to flow between the other nodes A Switch Input (Hi or Lo Voltage) Current can flow based on voltage of input switch B Vacuum Tube

9 2.9 Vacuum Tube Disadvantages Relatively large Especially when you need 19,000 to make 1 computer Unreliable Can burn out just like a light bulb Dissipate a lot of heat (power)

10 Voltage at the gate controls the operation of the transistor 2.10 Transistor Another switching device Invented by Bell Labs in 1948 Uses semiconductor materials (silicon) Much smaller, faster, more reliable (doesn't burn out), and dissipated less power Individual Transistors (About the size of your fingertip) Source Gate +5V Drain High voltage at gate allows current to flow from source to drain Source Gate 0V Silicon Drain Silicon Low voltage at gate prevents current from flowing from source to drain Transistor is 'on' Transistor is 'off'

11 2.11 Moore's Law & Transistors Moore's Law = Number of transistors able to be fabricated on a chip will double every years (i.e. exponential growth) Achieved by shrinking the transistor structure However, we are approaching the physical limitations of this shrinking 53% compound annual growth rate over 50 years No other technology has grown so fast so long Transistors are the fundamental building block of computer HW Switching devices: Can conduct [on = 1] or notconduct [off = 0] based on an input voltage

12 2.12 How Does a Transistor Work Transistor inner workings

13 2.13 NMOS Transistor Physics Let's review what we saw in the video Transistor is started by implanting two ntype silicon areas, separated by ptype ntype silicon (extra negative charges) Source Input Drain Input ptype silicon ("extra" positive charges)

14 2.14 NMOS Transistor Physics A thin, insulator layer (silicon dioxide or just "oxide") is placed over the silicon between source and drain Source Input Drain Output Insulator Layer (oxide) ntype silicon (extra negative charges) ptype silicon ("extra" positive charges)

15 2.15 NMOS Transistor Physics A thin, insulator layer (silicon dioxide or just "oxide") is placed over the silicon between source and drain Conductive polysilicon material is layered over the oxide to form the gate input Source Input Gate Input Drain Output conductive polysilicon Insulator Layer (oxide) ntype silicon (extra negative charges) ptype silicon ("extra" positive charges)

16 2.16 NMOS Transistor Physics Positive voltage (charge) at the gate input repels the extra positive charges in the p type silicon Result is a negativecharge channel between the source input and drain Source Input negativelycharge channel Gate Input positive charge "repelled" ptype Drain Output ntype

17 2.17 NMOS Transistor Physics Electrons can flow through the negative channel from the source input to the drain output The transistor is "on" Gate Input Source Input + + Drain Output + ntype ptype Negative channel between source and drain = Current flow

18 2.18 NMOS Transistor Physics If a low voltage (negative charge) is placed on the gate, no channel will develop and no current will flow The transistor is "off" Gate Input Source Input Drain Output ntype ptype No negative channel between source and drain = No current flow

19 2.19 View of a Transistor Crosssection of transistors on an IC Moore's Law is founded on our ability to keep shrinking transistor sizes Gate/channel width shrinks Gate oxide shrinks Transistor feature size is referred to as the implementation "technology node" Electron Microscope View of Transistor CrossSection

20 Minimum Feature Size 2.20

21 2.21 Intel Processor Trends 1971 Intel transistors Max 4Kbits addressable memory 1 MHz operation 2 nd Gen. Intel Core i7 Extreme Processor for desktops launched in Q4 of 2012 #cores/#threads: 6/12 Technology node: 32nm Clock speed: 3.5 GHz Transistor count: Over one billion Cache: 15MB Addressable memory: 64GB Size: 52.5mm by 45.0mm mm 2

22 ARM Cortex A15 ARM Cortex A15 in 2011 to cores per cluster, two clusters per chip Technology node: 22nm Clock speed: 2.5 GHz Transistor count: Over one billion Cache: Up to 4MB per cluster Addressable memory: up to 1TB Size: 52.5mm by 45.0mm

23 DIGITAL LOGIC GATES 2.23

24 2.24 Transistors and Logic Transistors act as switches (on or off) A S1 S2 B Logic operations (AND / OR) formed by connecting them in specific patterns Series Connection Parallel Connection A Series Connection S1 AND S2 must be on for A to be connected to B S1 S2 Parallel Connection S1 OR S2 must be on for A to be connected to B B

25 2.25 Gates Each logical operation (AND, OR, NOT) can be implemented as an digital device called a "gate" The schematic symbols below are used to represent each logic gate Each logic gate can be built by connecting transistors in various configurations AND Gate OR Gate NOT Gate

26 2.26 AND Gates An AND gate outputs a '1' (true) if ALL inputs are '1' (true) Gates can have several inputs Behavior can be shown in a truth table (listing all possible input combinations and the corresponding output) X Y Z F X Y F X Y F=X Y F X Y Z F=X Y Z F input AND 3input AND

27 2.27 OR Gates An OR gate outputs a '1' (true) if ANY input is '1' (true) Gates can also have several inputs X Y Z F X Y F=X+Y F X Y F X Y Z F=X+Y+Z F input OR 3input OR

28 2.28 Buffer & NOT (Inverter) Gate A Buffer simply passes a digital value But strengthens it electrically (e.g. boosts 3.7V closer to 5V) A NOT (aka "inverter") gate inverts a digital signal to its opposite value (i.e. flips a bit) the "bubble" (logically performs the inversion) X F X F X F X F F = X F = X

29 2.29 Aside: How Do You Build an Inverter (1)? A simple (though maybe not ideal) method to build an inverter is to place a transistor in series with a resistor Input to inverter is input to transistor Output of inverter is node between resistor and transistor We can model the transistor as a resistor Develop an equation for Vout Vdd Vin Vout Vdd R pullup R pullup R trans Vout = Vdd R trans + R pullup Vout Vout Vin Vin R Trans GND GND

30 2.30 Aside: How Do You Build an Inverter (2)? First, estimate the resistance of R trans if Vin is 0 (low) then again if Vin is 1 (highvoltage) Use that estimate in your equation for Vout to determine the output voltage Vdd Vdd R pullup R pullup Vout = Vout = 0 R trans = 1 (Vdd) R trans = GND GND

31 2.31 NAND and NOR Gates Inverted versions of the AND and OR gate X Y Z X Y Z NAND NOR Z X Y Z X Y X Y Z X Y Z X Y Z X Y Z AND NAND OR NOR True if NOT ALL inputs are true True if NOT ANY input is true

32 2.32 XOR and XNOR Gates Exclusive OR gate. Outputs a '1' if either input is a '1', but not both. X Y F X Y Z F X Y F X Y Z F XOR XNOR F X Y X Y F X Y Z F F X Y X Y F X Y Z F True if an odd # of inputs are true = True if inputs are different True if an even # of inputs are true = True if inputs are same

33 2.33 Logic Example A B C 0 D F 1

34 2.34 Logic Example A B C 0 D F 0

35 2.35 Practice: Waveform Diagrams Waveform diagrams show digital circuit operation over time Vertical axis: Each signal can be HIGH (1) or LOW (0) Horizontal axis: time Complete the waveform for the given circuit A B C w NOT of B x A and w y B or C F x xor y A B C w x y F

36 BOOLEAN ALGEBRA INTRO 2.36

37 2.37 Boolean Algebra Intro Larger logic circuits are too complex to analyze with truth tables or schematics Instead, use mathematical notation (equations) and develop axioms and theorems to help us manipulate logical expressions/equations Axioms = Basis / assumptions used Theorems = manipulations that we can use

38 2.38 Axioms Axioms are the basis for Boolean Algebra Notice that these axioms are simply restating our definition of digital/binary logic A1/A1 = Binary variables (only 2 values possible) A2/A2 = NOT operation A3,A4,A5 = AND operation A3,A4,A5 = OR operation (A1) X = 0 if X 1 (A1 ) X = 1 if X 0 (A2) If X = 0, then X = 1 (A2 ) If X = 1, then X = 0 (A3) 0 0 = 0 (A3 ) = 1 (A4) 1 1 = 1 (A4 ) = 0 (A5) 1 0 = 0 1 = 0 (A5 ) = = 1

39 2.39 Duality Every truth statement can yields another truth statement I exercise if I have time and energy (original statement) I don t exercise if I don t have time or don t have energy (dual statement) To express the dual, swap 1 s 0 s +

40 2.40 Duality The dual of an expression is not equal to the original Original expression Taking the dual of both sides of an equation yields a new equation Dual X + 1 = 1 Original equation X 0 = 0 Dual

41 2.41 Single Variable Theorems Provide some simplifications for expressions containing: a single variable a single variable and a constant bit Each theorem has a dual (another true statement) Each theorem can be proved by writing a truth table for both sides (i.e. proving the theorem holds for all possible values of X) T1 X + 0 = X T1' X 1 = X T2 X + 1 = 1 T2' X 0 = 0 T3 X + X = X T3' X X = X T4 (X')' = X T5 X + X' = 1 T5' X X' = 0

42 2.42 Single Variable Theorem (T1) X+0 = X (T1) X 1 = X (T1 ) X Y Z OR Hold Y constant X Y Z AND Whenever a variable is OR ed with 0, the output will be the same as the variable 0 OR Anything equals that anything Whenever a variable is AND ed with 1, the output will be the same as the variable 1 AND Anything equals that anything

43 2.43 Single Variable Theorem (T2) X+1 = 1 (T2) X 0 = 0 (T2 ) X Y Z OR Hold Y constant X Y Z AND Whenever a variable is OR ed with 1, the output will be 1 1 OR anything equals 1 Whenever a variable is AND ed with 0, the output will be 0 0 AND anything equals 0

44 2.44 Single Variable Theorem (T3) X+X = X (T3) X X = X (T3 ) X Y Z OR Whenever a variable is OR ed with itself, the result is just the value of the variable X Y Z AND Whenever a variable is AND ed with itself, the result is just the value of the variable This theorem can be used to reduce two identical terms into one OR to replicate one term into two.

45 2.45 Single Variable Theorem (T4) (X ) = X (T4) (X) = X (T4) Anything inverted twice yields its original value

46 2.46 Single Variable Theorem (T5) X+X = 1 (T5) X X = 0 (T5 ) X Y Z OR Whenever a variable is OR ed with its complement, one value has to be 1 and thus the result is 1 X Y Z AND Whenever a variable is AND ed with its complement, one value has to be 0 and thus the result is 0 This theorem can be used to simplify variables into a constant or to expand a constant into a variable.

47 2.47 Practice Exercise 1: Given the circuit below, write the corresponding logic equation for Y Exercise 2: Suppose we learn S=0, simply the equation for Y using T1T5 Exercise 3: Suppose we learn S=1, simply the equation for Y using T1T5 IN0 S Y IN1

48 ISEL0 ISEL1 ISEL2 ISEL3 OSEL0 OSEL1 OSEL2 OSEL Application: Channel Selector Given 4 input, digital music/sound channels and 4 output channels Given individual select inputs that select 1 input channel to be routed to 1 output channel Input channels ICH0 OCH ICH1 ICH2 Channel Selector OCH1 OCH2 4 Output channels ICH3 OCH3 Input Channel Select Output Channel Select

49 2.49 Application: Steering Logic 4input music channels (ICHx) Select one input channel (use ISELx inputs) Route to one output channel (use OSELx inputs) ICH ICH ICH ICH 3 ISEL0 ISEL1 ISEL2 ISEL3 OSEL0 OSEL1 OSEL2 OSEL3 OCH 0 OCH 1 OCH 2 OCH 3

50 OSEL0 OSEL1 OSEL2 OSEL Application: Steering Logic 1 st Level of AND gates act as barriers only passing 1 channel OR gates combines 3 streams of 0 s with the 1 channel that got passed (i.e. ICH1) 2 nd Level of AND gates passes the channel to only the selected output ICH 0 0 Connection Point ICH1 0 OCH 0 ICH ICH1 ICH1 0 ICH1 0 0 OCH 1 ICH ICH1 0 0 OCH 2 ICH ICH1 1 ICH1 OCH 3 AND: 1 AND ICHx = ICHx 0 AND ICHx = ISEL0 ISEL1 ISEL2 ISEL3 OR: 0 + ICH = ICH AND: 1 AND ICH1 = ICH1 0 AND ICH1 = 0

51 2.51 Speed, area, and power DIGITAL DESIGN GOALS

52 2.52 Digital Design Goals When designing a circuit, we want to optimize for the following three things: Area or Circuit Size (minimize) Speed (maximize) or Delay (minimize) Power (minimize) Can usually only optimize one or two of the 3 There is a huge trade space! This is what engineering is all about!

53 2.53 Minimizing Circuit Area Approaches: Reduce the number of gates used to implement a circuit Reduce the number of inputs to each gate In general a gate with n inputs requires 2*n transistors to implement Simplify logic expressions (usually by factoring and then canceling terms) to reduce the number of gates We'll learn more about this soon

54 2.54 Maximizing Speed Speed is affected by: Levels of logic (path length) Gate type Number of inputs (fanin) to the gate Number of outputs a gate connects to (fanout) Feature size and implementation technology

55 2.55 Delay Example Levels of Logic = Max. # of gates on any path from input to output A B C 0 D Levels of Logic F 1 0 Change in D, C, or A must propagate through 4 levels of gates

56 2.56 Gate Delays Order the gate types in terms of fastest to slowest? 1 X Z Typical gate delay for a 2input NAND or NOR is under a 100 ps. 2 3 X Y X Y Z Z X Y X Y Z Z 4 X Y Z X Y Z

57 2.57 Logical Operations Summary All digital circuits can be described using AND, OR, and NOT Note: You'll learn in future courses that digital circuits can be described with any of the following sets: {AND, NOT}, {OR, NOT}, {NAND only}, or {NOR only} Normal convention: 1 = true / 0 = false A logic circuit takes some digital inputs and transforms each possible input combination to a desired output values Triviaoftheday: The Apollo Guidance Computer that controlled the lunar spacecraft in 1969 was built out of 8,400 3input NOR gates. Inputs I 0 I 1 I 2 Logic Circuit O 0 O 1 Outputs

58 2.58 Storing bits SEQUENTIAL LOGIC

59 2.59 Combinational vs. Sequential Logic All logic is categorized into 2 groups Combinational logic: Outputs = f(current inputs) Sequential Logic Outputs = f(current + past inputs) Sequential logic has the notion of memory (remembering inputs or events that happened in the past)

60 2.60 Combinational vs. Sequential Current inputs Combinational Logic Outputs Current inputs Combinational Logic Outputs Sequential Outputs (State) feedback as inputs Sequential Logic Sequential Inputs (Next State) Outputs depend only on current outputs Outputs depend on current inputs and previous inputs (previous inputs summarized via state)

61 2.61 Combinational Example: Staircase Light Switch Whether or not the light is on is only dependent on the current position of the switches Light S2 S1 S1 S2 Light S1 S2 Logic Circuit Light

62 2.62 Water Tank Problem Build a control system for a pump to keep the tank from going empty Pump Pump Sensor High Sensor Low Sensor

63 2.63 Sequential Devices (Registers) AND, OR, NOT, NAND, and other gates are known as combinational logic Outputs only depend on what the inputs are right now, not one second ago This implies they have no "memory" (can't remember a value) Sequential logic devices provide the ability to retain or "remember" a value by itself (even after the input is changed or removed) Outputs can depend on the current inputs, and previous states of the circuit (stored values.) Usually have a controlling signal that indicates when the device should update the value it is remembering vs. when it should simply remember that value This controlling signal is usually the "clock" signal

64 2.64 Registers Registers are the most common sequential device Registers sample the data input (D) on the edge of a clock pulse (CP) and stores that value at the output (Q) Analogy: Taking a picture with your phone when you press a button (clock pulse) the camera samples the scene (input) and remembers/saves it as a snapshot (output). A register can only save 1 value (i.e. the last picture taken) Data Input (could be many bits) Clock pulse t = 0 ns t = 1 ns t = 5 ns t = 7 ns t = 10 ns D CP Q Block Diagram of a Register Data Output (could be many bits) The clock pulse (positive edge) here Clock pulse d(t) Some input value changing over time d(1) d(2) d(3) d(4) d(5) d(6) d(7) d(8) d(9) d(10) d(11) d(12) q(t) unk d(1) d(5) d(7) d(10) causes q(t) to sample and hold the current d(t) value

65 2.65 FlipFlops Flipflops are the building blocks of registers 1 Flipflop PER bit of input/output There are many kinds of flipflops but the most common is the D (Data) Flipflop (a.k.a. DFF) D Flipflop triggers on the clock edge and captures the Dvalue at that instant and causes Q to remember it until the next edge Positive Edge: instant the clock transition from low to high (0 to 1) PositiveEdge Triggered DFF Clock pulse d(t) Clock Signal D DFF CLK Q q(t) d(t) q(t)

66 2.66 Registers and Flipflops A register is simply a group of D flipflops that all trigger on a single clock pulse D0 D1 4bit Register D Q DFF D Q Q0 Q1 DFF CLK Q t+1 D2 D Q Q2 Steady level of 0 or 1 0 Q t 1 Q t DFF Positive Edge D t D3 D Q Q3 CP DFF

67 2.67 Pulses and Clocks Registers need an edge to trigger We can generate pulses at specific times (creating an irregular pattern) when we know the data we want has arrived Other registers in our hardware should trigger at a regular interval For that we use a clock signal Alternating high/low voltage pulse train Controls the ordering and timing of operations performed in the processor 1 cycle is usually measured from rising/positive edge to rising/positive edge Clock frequency (F) = # of cycles per second Clock Period (T) = 1 / Freq. 1 (5V) 0 (0V) Clock Pulses Clock Signal 1 cycle Op. 1 Op. 2 Op GHz = 2.8*10 9 cycles per second = ns/cycle Processor

68 2.68 Combinational vs. Sequential Sequential logic (i.e. registers) is used to store values Each register is analogous to a variable in your software program (a variable stores a number until you need it) Combinational logic is used to process bits (i.e. perform operations on values Analogous to operators (+,,*) in your software program