Mixed Analog-Digital VLSI Circuits & Systems Laboratory
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1 CORNELL U N I V E R S I T Y School of Electrical and Computer Engineering Mixed Analog-Digital VLSI Circuits & Systems Laboratory Our research presently revolves around two major themes: Devising new circuit techniques to facilitate the development of low-power/low-voltage analog and mixed-signal systems. Developing structured synthesis methodologies that will shorten the design time for complex analog and mixed-signal systems.
2 Low-Voltage Topologies for Analog and Mixed-Signal Circuits in Nanoscale CMOS Bradley A. Minch Mixed Analog-Digital VLSI Circuits and Systems Laboratory School of Electrical and Computer Engineering Cornell University Ithaca, NY
3 The Double-Gate MOS Transistor V F V S V D V D I V F V B V S V B The double-gate MOS transistor is perhaps the most promising device structure for scaling L down to 20 nm. Similar to fully-depleted SOI structure, but back gate provides better control over the potential in the silicon body, reducing short-channel effects. In principle, we can use V F and V B independently for signal or biasing inputs fi new topologies possible!
4 Conventional MOS Differential Pairs V 1 M 1 M 2 V 2 V V b M b V b M b V V 1 M 1 M 2 V 2 The differential pair is widely used as an input stage for operational amplifiers, comparators, mixers, and many other circuits. This circuit does not function well with a low powersupply voltage, because transistor M b shuts off if V 1 and V 2 get too close to the appropriate rail.
5 Conventional MOS Differential Pairs V 1 M 1 M 2 V 2 V V b M b V b M b V V 1 M 1 M 2 V 2 Differential-pair intuition: = (g(v 1, -V)) and = (g(v 2, -V)), where is expansive and g is quasilinear. V adjusts itself so that + Æ.
6 Capacitive Voltage Dividers V 2 C 2 C 1 Q V fi -C 1 ( V 1 - V)-C 2 ( V 2 -V)=Q fi( C 1 +C 2 )V =C 1 V 1 +C 2 V 2 +Q V = C 1 C 1 +C 2 V 1 + C 2 C 1 +C 2 V 2 + Q C 1 +C 2 V 1 The voltage on the middle node is a weighted sum of the two input voltages. If node V is really floating, then the inputs couple into the floating node all the way down to DC! The charge Q linearly offsets the V. The charge can be adjusted either optically or electronically.
7 Floating-Gate MOS Transitors V 2 C 2 Q V I C 1 V 1 The capacitors C 1 and C 2 are called control gates. If floating-gate voltage, V, is a weighted sum of the control-gate voltages. The floating-gate charge, Q, can be thought of as giving us a programmable threshold voltage.
8 An Inverted Floating-Gate Differential Pair V b M b V C 2 C 2 M 1a M 2a C 1 C 1 V 1 V 2 Differential-pair intuition: = (g(v 1, V)) and = (g(v 2, V)), where is expansive and g is quasilinear. V adjusts itself so that + Æ.
9 An Inverted Floating-Gate Differential Pair V b M b V C 2 C 2 M 1a M 2a C 1 C 1 V 1 V 2 Differential-pair intuition: = (g(v 1, V)) and = (g(v 2, V)), where is expansive and g is quasilinear. V adjusts itself so that + Æ. Sign reversal permits us to invert V w.r.t. the normal diffpair.
10 An Inverted Floating-Gate Differential Pair V b M b V C 2 C 2 M 1b M 1a M 2a M 2b C 1 C 1 V 1 V 2 Differential-pair intuition: = (g(v 1, V)) and = (g(v 2, V)), where is expansive and g is quasilinear. V adjusts itself so that + Æ. M 1b and M 2b provide mirror copies of and.
11 An Inverted Floating-Gate Differential Pair V b M b V c Vc M 1c M 2c M 1b V C 2 C 2 M 1a M 2a M 2b C 1 C 1 V 1 V 2 Differential-pair intuition: = (g(v 1, V)) and = (g(v 2, V)), where is expansive and g is quasilinear. V adjusts itself so that + Æ. M 1c and M 2c mitigate the C gd s of transistors M 1b and M 2b.
12 An Inverted Floating-Gate Differential Pair V b M b V c Vc M 1c M 2c M 1b V C 2 C 2 M 1a M 2a M 2b C 1 C 1 V 1 V 2 C 1 sets the linear range and transconductance gain. C 2 controls by how much V changes in response to changes in either V cm or. Input and output voltage ranges are from rail-to-rail. Transconductance gain nearly constant with V cm.
13 Output Currents vs. V dm ( = 316 pa) 400,, -, + (pa) V cm = 1.2 V V cm = 0 V V dm (V)
14 Output Currents vs. V dm ( = 31.6 ma) 40,, -, + (ma) V cm = 1.2 V V cm = 0 V V dm (V)
15 g dm (A/V) Transconducance Gain vs. V cm 100 ma 31.6 ma 10.0 ma 3.16 ma 1.00 ma 316 na 100 na 31.6 na 10.0 na 3.16 na 1.00 na 316 pa = 100 pa V cm (V)
16 Common-Mode Output Current vs. V out + (A) ma 31.6 ma 10.0 ma 3.16 ma 1.00 ma 316 na 100 na 31.6 na 10.0 na 3.16 na 1.00 na 316 pa = 100 pa V out (V)
17 A Double-Gate MOS Inverted Differential Pair? V b V? V b V V 1 V 2 V 1 V 2 Requirements for DGMOS version to be feasible: Independent front and back gates V 1 and V affect in a similar manner V 2 and V affect in a similar manner V transconductance larger than V 1 and V 2 V 1, V 2, and V ground
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