Lecture 6 NEW TYPES OF MEMORY

Transcription

1 Lecture 6 NEW TYPES OF MEMORY

2 Memory Logic needs memory to function (efficiently) Current memories Volatile memory SRAM DRAM Non-volatile memory (Flash) Emerging memories Phase-change memory STT-MRAM (Ferroelectric RAM)... Mattias Borg / More than Moore Future of Electronics 1

3 Memory architecture CPU Register (L0) Caches L1, ~10 s kb L2, ~100 s kb L3, ~10 s MB (L4, ~100 s MB edram) Main memory (off-chip) Permanent memory (Hard-drive, flash) Mattias Borg / More than Moore Future of Electronics 2

4 Toshiba, IBM, IEDM 2008 Static Random Access Memory cell SRAM 6 transistor (6T) Two cross coupled inverters Fast but area expensive (120F 2 ) Used for CPU cache rather than main memory (< 10 MB) Inverter 1 Inverter 2 Mattias Borg / Lecture 1 3

5 SRAM write Apply bit to bit line BL: 1 - And opposite to conjugate BL Mattias Borg / More than Moore Future of Electronics 4

6 SRAM write V dd off on 0 = on on off on = Apply bit to bit line BL: 1 2. Turn on M5 and M6 to save bit - M5 saves on right inverter - M6 saves on left inverter - M5/6 are stronger than M1-4 Mattias Borg / More than Moore Future of Electronics 5

7 SRAM read off off 0 = on on off = 1 off V dd /2 V dd /2 1. Precharge bit lines to V dd /2 - Saves time since lines are long Mattias Borg / More than Moore Future of Electronics 6

8 SRAM read on 0 = on = 1 V dd /2+ 0 V dd / Precharge bit lines to V dd /2 2. Turn on M5-6 to take out charge to bit lines 3. Voltage difference between BL and its conjugate is amplified and sensed 0 or 1 - If voltage difference is small enough then the read is non-destructive Mattias Borg / More than Moore Future of Electronics 7

9 Dynamic Random Access Memory DRAM Used for upper level caches and main memory Slower than SRAM, but much compacter (6F 2 ) 1T-1C Arranged in cross-bar grid Vertical trench capacitors to save space Mattias Borg / More than Moore Future of Electronics 8

10 DRAM operation The gate is connected to the word-line Source is connected to bit-line DRAM > 256 kb divided into blocks Limit of speed Capacitor charge needs refreshing (~50 ms) Mattias Borg / More than Moore Future of Electronics 9

11 DRAM write a 1 V row = V dd row line on on No charge Q=low charging Q=low high bit line 1 V bit1 = 0 bit line 2 V bit2 = V dd 1. Drive bit line to V dd 2. Select row 3. Capacitor is charged and the state is saved. Mattias Borg / More than Moore Future of Electronics 10

12 DRAM read a bit - 1 V row = 0 row line off off Q=low Q=high bit line 1 V bit1 = 0 bit line 2 V bit2 = V dd /2 1. Precharge bit line to V dd /2 - Reduces read swing Mattias Borg / More than Moore Future of Electronics 11

13 DRAM read a bit - 2 V row = V dd row line on on decharging Q=low low decharging Q=high low bit line 1 V bit1 = 0 bit line 2 V bit2 = V dd /2 1. Precharge bit line to V dd /2 2. Select the row - Capacitors on whole row decharge 3. Finish by re-writing data on row Mattias Borg / More than Moore Future of Electronics 12

14 DRAM energy cost Write: Dependent on size of capacitor V row = V dd row line Destructive read! Reading a bit destroys the word line, which needs rewriting energy cost Volatile memory: Refreshing capacitor charge regularly (every ~ms) bit line V bit2 = V dd on charging Q=low high Mattias Borg / More than Moore Future of Electronics 13

15 Embedded DRAM SRAM takes up too much space, too energy costly Embedding DRAM with Processor increases band width Intel embeds DRAM in package with Processor IBM directly on processor chip edram does not scale beyond 22 nm node... Capacitor cannot be made much deeper than with aspect ratio of 40 Max(H/W) ~ 40 H W Intel SiP edram Mattias Borg / More than Moore Future of Electronics 14

16 Need for new memory technology To reduce power consumption at given performance Memory uses large fraction of chip power Low Power is vital for edge IoT devices for many architectures, memory power may be a third to a half of the total energy. Drew Sonics. Passive power consumption (leakage, refresh) Read-write energy cost Lower memory cost On-chip memory removes pins and reduces cost However, it needs die area which increases cost Mattias Borg / More than Moore Future of Electronics 15

17 Phase change memory Utilizes large resistivity contrast between crystalline and amorphous phases Switching by crystallizing/amorphidizing material by electrical heating Non-volatile memory GeTe Sb 2 Te 3 alloys crystallize fast Allows for multi-level data saving (>1 bit/device) IBM PCM cell 2015 Wong et al. Proc. IEEE 2010 Mattias Borg / More than Moore Future of Electronics 16

18 PCM operation RESET: Large current pulse melts (amorphidizes) PCM near bottom electrode SET: Medium current pulse writes (crystallizes) the material READ: Low current pulse measures the resistance state Mattias Borg / More than Moore Future of Electronics 17

19 Threshold switching Critical for feasibility In high-r state: Poole-Frenkel transport through traps Very high voltage would be needed to deliver sufficient power to heat above T cryst But: Above V > V t the large electric field dramatically increases conductivity Origin still debated Allows for sufficient crystallization power Mattias Borg / More than Moore Future of Electronics 18

20 PCM instead of DRAM Energy; DRAM needs rewrite after every read + refresh PCM is non-volatile Speed: DRAM: < 10 ns PCM: 10 ns best ( ns most often) Cost/Density: SRAM area: 120F 2 DRAM area: 6F 2 PCM: 5.8F 2 Endurance is Samsung IEDM 06 Mattias Borg / More than Moore Future of Electronics 19

21 PCM device design Crystallization time constant limits speed Cubic/Rock salt structure with small atomic movements Low bond ionicity and hybridization Crystal growth from amorphous-crystalline interface much faster than complete recrystallization To minimize RESET current High thermal resistance in PC material Nanostructuring! High interface resistance can be utilized to localize heat Small interface between heater and PC material At best ~ 100 µa reset current (100 µa x 10 1 V 1 pj/bit Mattias Borg / More than Moore Future of Electronics 20

22 Multilevel PCM By tuning amorphidization level resistance can be tuned in an analogue fashion Allows for multilevel data storage in single device Denser data storage Mattias Borg / More than Moore Future of Electronics 21

23 Remaining issues Endurance (10 9 cycles) Stress-induced void formation (stuck open) Sb segregation (stuch closed) Resistance drift Explanations: Stress release, decrease in defect density, fermi level shift,... Void formation Mattias Borg / More than Moore Future of Electronics 22

24 STT-MRAM Non-volatile memory Electron tunneling through a magnetic tunnel junction 1T-1MTJ Based on 2 recently discovered phenomena: Tunneling magnetoresistance Spin-torque transfer Mattias Borg / More than Moore Future of Electronics 23

25 Promise of STT-MRAM Energy SRAM: 10 s fj/bit DRAM: 1-10 pj/bit STT-MRAM: fj/bit Speed/delay SRAM: 1 ns DRAM: ~10 ns STT-MRAM: < 10 ns Cost/Density SRAM: 120F 2 DRAM: 6F 2 STT-MRAM: 4-6F 2 Volatility SRAM and DRAM: Volatile STT-MRAM: Non-volatile Mattias Borg / More than Moore Future of Electronics 24

26 Tunneling magnetoresistance The resistance of the tunneling junction depends strongly on relative orientation of the magnetic layers Antiparallel spin few empty states high resistance Parallel spin good match of DOS low resistance Reading of spin-state is thus possible Giant TMR through crystalline MgO barriers Fe(001) spd hybridized states (Δ 1 ) are fully polarized Couple to evanescent Δ 1 states in MgO MgO(001) evanescent Δ 1 decay slowest filters out states with low P Makes TMR effect very strong! Mattias Borg / More than Moore Future of Electronics 25

27 Spin-torque transfer Electrons flowing through the tunnel junction can transfer spin angular momentum between RL and FL Resulting torque on magnetization of the FL WRITING of data to FL An electron spin passing through a magnetized layer has its spin direction altered But also the magnetization is affected (torque) Mattias Borg / More than Moore Future of Electronics 26

28 Typical design Utilizes a Magnetic Tunnel Junction (MTJ): Tunneling oxide Epitaxial and crystalline MgO Giant Tunneling Magneto-Resistance effect Lower ferromagnetic electrode (Reference layer) Provides a stable magnetization (hard to change) Upper ferromagnetic electrode (Free layer) Eas(ier) to change magnetization Encodes data Two main designs: Magnetization in-plane (IP) or perpendicular to the plane (PP) Spin current upwards parallel magnetization ( 1 ) Spin current downwards antiparallel magnetization ( 0 ) In-plane Perpendicular (to the) Plane Mattias Borg / More than Moore Future of Electronics 27

29 Reference layer design Two ferromagnetic layers separated closely by non-magnetic layer Dipole interaction strong antiferromagnetic coupling Synthetic Anti-Ferromagnet (SAF) Substantially decreases stray magnetic field lower crosstalk between RL and FL FL MgO RL CuFeB < 1 nm Ruthenium CuFeB Anti-ferromagnet Mattias Borg / More than Moore Future of Electronics 28

30 word line 1 word line 2 LUND UNIVERSITY STT-MRAM Write 0 bit line V= -V dd FL Magnetization is flipped parallel RL off on V= 0 0 is low resistive state (parallel) Word line chooses device Bit line biased negative current upwards parallel spin Mattias Borg / More than Moore Future of Electronics 29

31 word line 1 word line 2 LUND UNIVERSITY STT-MRAM Write 1 bit line V= V dd FL Magnetization is flipped antiparallel RL off on V= 0 0 is low resistive state (parallel) Word line chooses device Bit line biased negative current upwards parallel spin Mattias Borg / More than Moore Future of Electronics 30

32 word line 1 word line 2 LUND UNIVERSITY STT-MRAM Read bit line V << V dd FL Resistance high = 0 Resistance low = 1 RL on on Read current much lower than needed to flip magnetization Parallel / Antiparallel spin in free layer low / high resistance i.e. data read out V= 0 Mattias Borg / More than Moore Future of Electronics 31

33 Energy LUND UNIVERSITY Data retention Free layer needs to retain its magnetization despite disturbance Typical target is 10 years retention 40 kt ~ 1 ev energy barrier for switch Possible disturbance: Thermal fluctuations Read event Typical prob. for unwanted switch ~ This was for long a major road block kt E b Mattias Borg / More than Moore Future of Electronics 32

34 Stability of the Free layer Perpendicular Magnetic Anisotropy (PMA) prevents spontaneous magnetization switching Shape anisotropy High aspect ratio (disc shape) high shape anisotropy Interface PMA Related to change of crystal symmetry at interface MgO/CuFeB interface strong IPMA effect Bulk PMA Layered crystal structure anisotropy Ex: L1 0 structure (layered face-centered cubic) Usually not lattice-matched to MgO Mattias Borg / More than Moore Future of Electronics 33

35 In-plane or perpendicular MRAM? Assuming other parameters constant, switching current is somewhat higher for IP compared to PP However, IP usually has higher STT efficiency and less magnetic damping PP is scalable below 20 nm, which IP is not really (loses shape anisotropy) PP seems to be most common choice at the moment In-plane Perpendicular (to the) Plane Mattias Borg / More than Moore Future of Electronics 34

36 MRAM state-of-the-art 2016: IBM and Samsung 11 nm device 7.5 µa switching current Reset voltage = +/-0.7V 10 ns switching time < 100 fj switching energy - Write error rate = 7 x Smallest devices still have a bit too low energy barrier - In production within 3 years 10 years retention Mattias Borg / More than Moore Future of Electronics 35

37 Summary Technology Data retention Endurance (cycles) Energy (fj/bit) Speed Size (F 2 ) SRAM > ns 120 DRAM ms >10 16 > ns 6 PCM 10 years ns 6 STT-MRAM >10 years >10 ns 4 Mattias Borg / More than Moore Future of Electronics 36