Embedded MRAM Technology For logic VLSI Application

Transcription

1 th Non-Volatile Memory Technology Symposium Embedded MRAM Technology For logic VLSI Application November 7, 2011 Naoki Kasai 1, Shoji Ikeda 1,2, Takahiro Hanyu 1,3, Tetsuo Endoh 1,4, and Hideo Ohno 1,2 1 Center for Spintronics Integrated Systems, Tohoku University, JAPAN 2 Laboratory for Nanoelectronics and Spintronics, Research Institute of Electrical Communication, Tohoku University, JAPAN 3 Laboratory for Brainware Systems, Research Institute of Electrical Communication, Tohoku University, JAPAN 4 Center for Interdisciplinary Research, Tohoku University, JAPAN Work supported by the FIRST program of JSPS. 1

2 Existing Embedded Memory Market WW 2010 World Semiconductor Trade Statistics Applications Embedded Memory Micro-processor (PC, Server, ) MOS Micro 61B (US$) Micro-computer (4-32 bit MCUs) SRAM L1-L3 cash SRAM NOR-Flash Requirements Ultra high speed RAM Large capacity RAM Scaling Issues Operation margin (Vth variation) Cell size scaling Key challenge Low Power Voltage scaling High speed RAM Large capacity NVM Cell size scaling Reliable NVM Wide temp. range Low cost MOS Logic 77B (US$) ASIC, ASSP, FPGA (Mobile, Graphic, ) SRAM DRAM High speed RAM Large capacity RAM Wide band width RAM Cell size scaling Low operation power Low standby power Voltage scaling Low cost 2

3 Memory Portfolio High Performance Read Clock Frequency (Hz) Trade-off relation between performance and cost 1G 100M 10M High-speed esram esram SRAM MRAM, FRAM EEPROM edram DRAM eflash NOR Flash NAND Flash Logic esram Logic Logic esram eflash MPU, ASIC... High Speed RAM Logic Compatibility Low Voltage Design MCU High Speed NVM Various Application Wide Temp. Range High Reliability Graphics Cell Area Factor, a ( a =cell area/f 2 ) Low Cost edram Wide Bandwidth Low Power Large Capacity 3

4 Alternative emram No universal embedded MRAM, but some types of MRAMs must be suitable for embedded applications. High Performance Read Clock Frequency (Hz) 1G 100M 10M High-speed esram esram SRAM MRAM, FRAM EEPROM edram DRAM eflash NOR Flash NAND Flash High speed emram High density emram Cell Area Factor, a ( a =cell area/f 2 ) Low Cost 4

5 Embedded MRAM Issues Standard CMOS Process compatible Suitable memory cell structure Number of cell components; MTJ, transistor, wiring Data write scheme; Magnetic Field, STT,. MTJ: Magnetic Tunnel Junction MR ratio Magnetic anisotropy; in-plane anisotropy perpendicular anisotropy Free Layer Tunnel Barrier Fixed Layer Free Layer Tunnel Barrier Fixed Layer Materials of stacked thin magnetic layers and tunnel barrier film 5

6 CMOS Process Compatible MTJs formed in back-end of line, BEOL CMOS characteristics unchanged No Yoke (magnetic clad) lines Cu & low-k interconnect applicable 350 ºC thermal stability in BEOL fabrication process MTJ Formation MTJ Standard CMOS Logic Spintronics CMOS Logic 6

7 Typical MRAM Cells Cell Type Data Write Scheme Magnetic Field No Transistor 0Tr + 1MTJ One Transistor 1Tr + 1MTJ Write bit-line Two Transistors 2Tr + 1MTJ induced by write current through metal wires MTJ MTJ MTJ write word-line Spin Transfer Torque (STT) by current through MTJ unselected cell selected cell MTJ unselected cell selected cell Domain Wall Motion (DWM) by current through free layer half-selected cell Probability Read Write Barrier Breakdown MTJ Current Domain Wall 7

8 High Density emram Cell Requirements Simple cell structure without snake path Random access read/write in cell array Scalable MTJ size & write current Large magneto-resistance(mr) ratio BEOL process temperature 350 ºC Reliability Low tunnel current density Non-volatality Δ=E/k BT Choices 0Tr + 1MTJ 1Tr + 1MTJ 2Tr + 1MTJ Magnetic Field STT DWM Al2O5 MgO In plane Perpendicular MgO 8

9 CoFeB/MgO/CoFeB MTJ Large MR Ratio In-plane anisotropy pseudo-sv Cr/Au Ru (5) Ta(5) CoFeB(6) MgO(2.1) CoFeB(5 ) Ta(5) Ru(10) Ta(5) SiO 2 /Si sub. CoFeB MgO CoFeB bcc (001) rock salt (001) bcc(001) トンネル磁気抵抗比 TMR ratio (%) (%) %@RT(1144%@5K) Tohoku Univ. & Hitachi MgO-barrier MTJs CanonANELVA & AIST IBM AIST AlO x -barrier MTJs Tohoku Univ Year 年 AIST AIST S. Ikeda et. al., Appl. Phys. Lett. 93, (2008). 9

10 Dependence of tcofeb on Anisotropy Perpendicular Anisotropy MgO(1) CoFeB(t CoFeB ) Ta(5) Ru(10) Ta(5) SiO 2 /Si sub. T a =300 o C, 4 koe, 1h M (T) t CoFeB = 2.0 nm T a =300 o C t CoFeB = 1.3 nm T a =300 o C in-plane out-of-plane m 0 H s_in-plane = 0.34 T M s = 1.58 T K = 2.1x10 5 J/m µ 0 H (T) In-plane anisotropy Perpendicular anisotropy Ikeda et al., Nat. Mat., 9 (2010) pp

11 CoFeB/MgO/CoFeB MTJ Perpendicular Anisotropy V - Al 2 O 3 Cr/Au Ru (5) Ta(5) CoFeB(1.5 ) MgO(0.9) CoFeB(0.9 ) Ta(5) Ru(10) Ta(5) V + R (kω) Antiparallel Parallel SiO 2 /Si sub. (nm) µ 0 H (T) 40 nm Ikeda et al., Nat. Mat., 9 (2010) pp

12 CoFeB/MgO/CoFeB MTJ Cr/Au Ru (5) Ta(5) CoFeB(1.7) MgO(0.85) CoFeB(1.0 ) Ta(5) Ru(10) Ta(5) SiO 2 /Si sub. 40 nm Spin Transfer Torque switching R (kω) J C (MA/cm 2 ) µ 0 H (T) J (MA/cm 2 ) AP P τ P (sec) τ P = 300 µsec 1.0 sec ln(τ P /τ 0 ) P AP Ikeda et al., Nat. Mat., 9 (2010) pp I C (µa) TMR ratio =124% RA = 18 Ωμm 2 H shift = 37 mt IC0 = 50 µa (P-> AP) - 20 µa (AP-> P) E/kBT = ( P ) ( AP ) Free Reference N S N S Parallel state Low resistance S N N S Antiparallel state High resistance Different polarity =Stable The same polarity =Unstable 12

13 Stability Enhancement Structure Conventional structure Stepped structure 100 nm 100 nm 1.5 nm 0.9 nm 0.9 nm 100 nm CoFeB MgO CoFeB Free Layer Reference Layer 300 nm 100 nm CoFeB MgO CoFeB H s AP E/k B T 1 0 P H s E/k B T 1 0 AP P dipole interlayer coupling field K. Miura et al., 2011 VLSI Technology, 11B-3. 13

14 Stability Enhancement Structure Conventional structure Stepped structure Resistance (kω) TMR Ratio (%) RA (Ωµm 2 ) H s (mt) 22 5 Resistance (kω) Magnetic field (mt) Magnetic field (mt) Probability AP -> P P -> AP Magnetic field (mt) P AP Probability AP -> P P -> AP Magnetic field (mt) K. Miura et al., 2011 VLSI Technology, 11B-3. 14

15 Alternative High Density RAM 1T+1R STT MRAM must have potential to be substituted for not only embedded DRAM but also commodity DRAM. Read Clock Frequency (Hz) 1G 100M 10M High-speed esram esram SRAM MRAM, FRAM EEPROM edram DRAM eflash NOR Flash NAND Flash STTRAM (1T+1R) DRAM (1T+1C) Cell Area Factor, a ( a =cell area/f ) 15

16 Alternative High Speed RAM Read Clock Frequency (Hz) 1G 100M 10M High-speed esram esram SRAM MRAM, FRAM EEPROM edram DRAM eflash NOR Flash NAND Flash Cell Area Factor, a ( a =cell area/f 2 ) Write Current Read Current Current Path (Read & Write) High speed RAM MRAM (2T+1R) SRAM (6T) High density RAM Probability Read Write Current Barrier Breakdown STTRAM (1T+1R) DRAM (1T+1C) 16

17 High Speed emram Cell Requirements Disturb free cell structure High speed random access read/write Scalable MTJ size & write current Large magneto-resistance(mr) ratio BEOL process temperature 350 ºC Reliability Low tunnel current density Non-volatality Δ=E/k BT Choices 0Tr + 1MTJ 1Tr + 1MTJ 2Tr + 1MTJ Magnetic Field STT DWM Al2O5 MgO In plane Perpendicular Domain Wall 17

18 Domain Wall Motion(DWM) Writing Perpendicular Anisotropy Two Pinning Layers (PL) DWM Free Layer (FL) Hc(PL) >> Hc(FL) Fixed Free Region Fixed Sense Layer Reference Layer Pinning Layer (1) Pinning Layer (2) Write Current Spin Transfer Torque Free Layer Domain Wall R. Nebashi, et. al., Sym. VLSI Circuits. p. 300, H. Honjo, et. al., 56th MMM Conference, Spin Transfer Torque Write Current 18

19 Domain Wall Motion(DWM) Reading In-plane Anisotropy Sense Layer (SL) Reference Layer (RL) Hc(RL) >> Hc(SL) Reference Layer Pinning Layer (1) Sense Layer Pinning Layer (2) Sense layer magnetic direction is changed by stray field from DWM free layer Read Current MTJ parallel 0 Free Layer Domain Wall MTJ anti-parallel R. Nebashi, et. al., Sym. VLSI Circuits. p. 300, H. Honjo, et. al., 56th MMM Conference, HR-10,

20 Cell Area (a.u.) Write Current ( Iw ) Target Iw < 0.5mA Competitive in cost against esram 2T1MTJ Cell Area emram with normal logic rule 6T- esram emram with modified rule Write Current (ma) I write (ma) S. Fukami, et. al., Sym. VLSI Tech. p. 230, R Hall (Ohm) S. Fukami,et. al. Appl. Phys. Lett. Vol. 98, , W Co/Pt Co/Ni Domain wall W (nm) Current (µa) [Co/Ni] n CoFeB 20

21 DWM NVM Fabrication 140nm Side view R. Nebashi, et. al., Sym. VLSI Circuits. p. 300, th -Metal line Front view In Plane MTJ (Sense FL) PL1 PL2 4 th -Via 4 th -Via 21

22 FIRST Program Target Non-volatile logic-in-memory architecture Logic with NVM Logic Non-volatile memory NV logic-in-memory Static Power Reduction By NVM 2 terminal STT 3 terminal MRAM Please visit our homepage New Energy Saving System on a Chip for Variety of applications Storage / Logic merged NV full adder NV TCAM NV flip-flop NV NV nsec Dynamic Power Reduction 22

23 Summary 1T+1MTJ STT(Spin Torque Transfer) MRAM has the potentials for substitution of embedded DRAM to apply high density embedded NVM application. 2T+1MTJ DWM(Domain Wall Motion) MRAM has the potentials for substitution of embedded SRAM to apply high speed NVM application. These embedded MRAM technology leads to logic-inmemory architecture for future new energy saving SoC(System on a Chip). 23

24 Acknowledgements This research is granted by the Japan Society for the Promotion of Science (JSPS) through the Funding Program for World- Leading Innovative R&D on Science and Technology (FIRST Program), initiated by the Council for Science and Technology Policy (CSTP). Prof. Hideo Ohno has been conducting the program Research and Development of Ultra-low Power Spintronics-based VLSIs as the core researcher. Thanks to K. Miura, H. Yamamoto, K. Misunuma, H. D. Gan, M, Endo, S. Kanai, J. Hayakawa, F. Matsukura, M. Yamanouchi, J. Hayakawa, R. Kiizumi, S. Fukami, T. Suzuki, K. Nagahara, N. Ohshima, Y. Ozaki, S. Saito, R. Nebashi, N. Sakimura, H. Honjo, K. Mori, C. Igarashi, S. Miura, N. Ishiwata, K. Kinoshita, Y. Nakatani, Y. Tsuji, R. Nebashi, N. Sakimura, H. Honjo, K. Mori, H. Tanigawa, S. Miura, and T. Sugibayashi 24