N ano scale l S il ii lco i n B ased N o nvo lat l i atl ie l M em ory r Chungwoo Kim, Ph.D.

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1

2 Acknowledgements Collaboration Funding

3 Outline Introduction Current research status Nano fabrication Process Nanoscale patterning SiN thin film Si Nanoparticle Nano devices Nanoscale SONOS memory Vertical channel memory Future Work

4 Environment of Memory New application, unification Diversfied from PC into digital application Increasing capacity of voice, motion picture information Need higher density of memory Increasing demand for unified memory Uncertainty of DRAM & Flash Memory scalability Memory Market: $35 billion (2001), $72 billion (2010), 8.3% increase/year Settop box Game Player Digital TV PDA HHP Internet PC

5 Flash Memory Roadmap Feature Size nm Develop. Stage Research Stage Uncertain Stage M M 128M-1G 256M-1G 256M-2G 512M-4G 512M-4G Unit Cell Production 2G-16G Scale limit? 4G-64G Year

6 Flash Technology Requirements Year of Production Flash tech. Node, F[nm] NOR highest W/E Voltage[V] NAND highest W/E Voltage[V] NOR tunnel dielectric thickness[nm] NAND tunnel dielectric thickness[nm] NOR interpoly dielectric thickness[nm] NAND interpoly dielectric thickness[nm] : ITRS Solutions Exist Solutions are Known Solutions are NOT Known

7 Problems of conventional technologies What s the limits of flash scaling? Floating poly Stack Active (STI)

8 Discrete traps e e Control Gate Blocking oxide e e e e e e e Tunnel Oxide Floating gate n+ n+ p-well Overcome e Control Gate Blocking oxide e e e Tunnel Oxide e Discrete traps n+ n+ p-well Flash memory SONOS Memory Discrete traps (SiN traps or Nanocrystal) * SONOS (Silicon-Oxide-Nitride-Oxide-Silicon)

9 Motivation for SONOS 30nm 30 nm US Patent # ( ) < Advantages > Compatibility of SONOS with CMOS with the use of thin nitride Lower programming voltage Smaller dimension capability than FG EEPROM Longer retention & low defect induced tunneling leakage (Nitride instead of poly Si ) Higher programming speed (depends on ONO thickness)

10 Comparison of Memory Technologies FRAM MRAM PRAM SONOS Cell size 8~25 F 2 8~9 F 2 6 F 2 4~10 F 2 Read time 30~200 ns 10~100 ns 10~100 ns 20~120 ns Write time 30 ns 10~15 ns 10~100 ns 1 µs ~ 1 ms Retention > 10 > 10 > 10 >10 Endurance > 10E12 > 1E13 > 10E13 > 1E5 Current/Power Low High High Low Cost High High Low Low Process Special Special Special CMOS Issues Etching process Cost Retention, Fatigue Etching process Uniform thin films Cost Power consumption Thin Oxide film Faster P/E time

11 SONOS Memory Development 130 nm 70 nm Source 70nm Drain Gate 30 nm

12 Nano Lithography 21 nm Positive Resist : PMMA 32 nm Sidewall Patterning Negative Resist : Calixarene

13 Si Nanoparticle Fabrication by Aerosol Laser Ablation 6x10 4 Concentration (/cm 3 ) 5x10 4 4x10 4 3x10 4 2x10 4 1x10 4 D <10nm ρ ~ /cm Nanoparticle Size (nm) 5nm 5nm

14 30nm SONOS Memory by SWP Threshold Voltage [V] ONO=23/120/45 Å Vg=10 Vg=-10 Vg=-10/Vd=1 Vg=-10/Vd=2 Vg=-10/Vd=3 Vg=-10/Vd= Write/Erase Time [Sec] Key Features of SONOS Cell Memory Node Size: 30 x 30 nm2 Write/ Erase Voltage: <10V Write/Erase Time: 1 msec Endurance: >10 6 cycles Retention =

15 Key Characteristics of SONOS Memory Drain Current [A] Drain Current [A] 3.60E E E E E E E E E E E-6 1E-7 1E-8 1E-9 1E-10 1E-11 1E-12 1E-13 ONO=23/120/45 Å W/L=30nm/30nm ONO=23/120/45 A Vds [V] V DS =1V V DS =0.1V DIBL = 105mV S.S = 89mV/dec V th =-0.05V 1E Vgs [V] 1.0V 0.8V 0.6V 0.4V 0.2V V GS =0V Vth [V] Vth (V) [V] At Program Erase state Time [sec] Cycles (number)

16 SONOS Memory by E-beam Lithography Drain Gate Source SONOS Cell by E-beam Lithography W/L : 33nm / 46nm

17 ONO layer TEM & AES Analysis 100 SiO 2 =90Å Si 3 N 4 = 70Å SiO 2 = 20Å Relative ACP(%) Si N O 20Å / 70Å / 90Å Sputter Time [sec.] TEM of the ONO (2 nm/7 nm/9 nm) stack Auger profile showing the stoichiometric of ONO layer.

18 Program & Erase Characterisics Threshold Voltage[V] V 10V 11V 12V 13V E-7 1E-6 1E-5 1E-4 1E Write Time[sec] Threshold Voltage[V] E-7 1E-6 1E-5 1E-4 1E Erase Time[sec] 9V 10V 11V 12V 13V Vth ~ 2.4V Trapped Charge density = 4.1 ~ 5.9 x cm 2 2 No. of e -- = 61 ~ 88 for 33nm x 46nm node size

19 Memory Window Comparison Id [A] 1x10-5 1x10-6 1x10-7 1x10-8 1x10-9 1x x x x x W g /L g g =90nm/100nm / Vg [V] Id [A] 1x10-5 1x10-6 1x10-7 1x10-8 1x10-9 1x x x x x W g /L g =62nm/60nm / 60nm Vg [V] Id [A] 1x10-5 1x10-6 1x10-7 1x10-8 1x10-9 1x x x x x W g /L g =75nm/100nm / Vg [V] Vg [V] Memory window is nearly similar for SONOS devices with different memory node areas Id [A] 1x10-5 1x10-6 1x10-7 1x10-8 1x10-9 1x x x x x W / g /L g =33nm/46nm

20 Retention Time Endurance Threshold Voltage [V] Temp=85C Write 10V, 10msec Erase -10V, 1msec Wg/Lg=75nm / 100nm Retention Time[sec] Threshold Voltage [V] Temp=85C Write 12V/10msec Erase -10V/1msec 0.8 W g /L g =33nm / 46nm Write/Erase Cycle Retention time is good with 75nm width and 100 nm length at 85. It remains unchanged up to 10 5 cycles, indicating superior endurance characteristics at 85.

21 Memory Effect at 30 nm dimensions 1.4x10-9 W g /L g =35nm / 39nm 1.2x10-9 ID [A] 1.0x x x10-10 Before write After write(10ms, 10V ) 4.0x x VG [V] W g = 35.4 nm L g = 39 nm Single electron charging effect at 30 nm dimensions.

22 Vertical Channel SONOS Poly Silcon Programmed Cell I d =1nA, V d =0.5V Vg 6/7/8V N+ N+ V th (V) Vg -6/-7/-8V BOX Erased Cell 1E E Write/Erase Time(sec) Schematic of VC SONOS 8/-8V &10ms

23 TEM images source gate drain CVD oxide Vertical channel Gate Gate O/N/O Contact Source Drain Vertical channel bulk

24 Future Work Nano fabrication process for Integration Improvement of SONOS memory characteristics High-k materials New memory cell structure Optimal bias conditions Device physics Single electron effect Reliability failure mechanism Memory cell Modeling/Simulation

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