74HC86. Quad 2 Input Exclusive OR Gate. High Performance Silicon Gate CMOS
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1 Quad 2 Input Exclusive OR Gate MARKING DIAGRAMS High Performance Silicon Gate CMOS The is identical in pinout to the LS86. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. SOIC D SUFFIX CASE 5A HC86G AWLYWW Features Output Drive Capability: 0 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Range: to Low Input Current:.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with JEDEC Standard No. A Requirements ESD Performance: HBM 2000 ; Machine Model 200 Chip Complexity: 56 FETs or Equivalent Gates These are Pb Free Devices TSSOP DT SUFFIX CASE 948G HC86 = Device Code A = Assembly Location L, WL = Wafer Lot Y = Year W = Work Week G or = Pb Free Package HC 86 ALYW (Note: Microdot may be in either location) Semiconductor Components Industries, LLC, 200 March, 200 Rev. Publication Order Number: /D
2 PIN ASSIGNMENT LOGIC DIAGRAM A B 2 3 B4 A B 2 3 Y Y A2 B A4 Y4 B3 A2 B Y2 Y2 GND A3 Y3 A3 B Y3 FUNCTION TABLE Inputs A B L L L H H L H H Output Y L H H L 2 A4 3 B4 Y = A B = AB + AB PIN = PIN = GND Y4 2
3 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS Symbol Parameter alue Unit DC Supply (Referenced to GND) 0.5 to +.0 in DC Input (Referenced to GND) 0.5 to out DC Output (Referenced to GND) 0.5 to I in DC Input Current, per Pin ±20 ma I out DC Output Current, per Pin ±25 ma I CC DC Supply Current, and GND Pins ±50 ma P D Power Dissipation in Still Air, SOIC Package TSSOP Package mw T stg Storage Temperature 65 to + 50 C T L Lead Temperature, mm from Case for 0 Seconds C (SOIC or TSSOP Package) 260 Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. Derating SOIC Package: mw/ C from 65 to 25 C TSSOP Package: 6. mw/ C from 65 to 25 C For high frequency or heavy load considerations, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit DC Supply (Referenced to GND) in, out DC Input, Output (Referenced to 0 GND) T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time = ns (Figure ) = = This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, in and out should be constrained to the range GND ( in or out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or ). Unused outputs must be left open. 3
4 DC ELECTRICAL CHARACTERISTICS (s Referenced to GND) Symbol Parameter Test Conditions IH IL OH OL Minimum High Level Input Maximum Low Level Input Minimum High Level Output Maximum Low Level Output out = 0. or 0. out = 0. or 0. I out 2.4 ma I out 4.0 ma I out 5.2 ma I out 2.4 ma I out 4.0 ma I out 5.2 ma () Guaranteed Limit 55 to 25 C 85 C 25 C I in Maximum Input Leakage Current in = or GND ±0. ±.0 ±.0 A I CC Maximum Quiescent Supply Current (per Package) in = or GND I out = 0 A Unit A NOTE: Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, Input t, = t f = 6 ns) Symbol t PLH, t PHL t TLH, t THL Parameter Maximum Propagation Delay, Input A or B to Output Y (Figures and 2) Maximum Output Transition Time, Any Output (Figures and 2) () Guaranteed Limit 55 to 25 C 85 C 25 C C in Maximum Input Capacitance pf NOTES:. For propagation delays with loads other than 50 pf, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). 2. Information on typical parametric values can be found in Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D) C, = 5.0 C PD Power Dissipation Capacitance (Per Gate)* 33 pf * Used to determine the no load dynamic power consumption: P D = C PD 2 CC f + I CC. For load considerations, see Chapter 2 of the ON Semiconductor High Speed CMOS Data Book (DL29/D). Unit ns ns 4
5 t r t f INPUT A OR B 90% 50% 0% GND TEST POINT t PLH OUTPUT Y 90% 50% 0% t PHL DEICE UNDER TEST OUTPUT C L * t TLH Figure. Switching Waveforms t THL *Includes all probe and jig capacitance Figure 2. Test Circuit A Y B Figure 3. Expanded Logic Diagram (/4 of Device) 5
6 PACKAGE DIMENSIONS SOIC CASE 5A 03 ISSUE H T SEATING PLANE G A 8 D PL B K P PL C 0.25 (0.00) M T B S A S 0.25 (0.00) M B M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.2 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES R X 45 F DIM MIN MAX MIN MAX A B C D M J F G.2 BSC BSC J K M 0 0 P R SOLDERING FOOTPRINT* X 0.58 X.04 X.52.2 PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 6
7 PACKAGE DIMENSIONS TSSOP CASE 948G 0 ISSUE B 0.5 (0.006) T 0.5 (0.006) T L 0.0 (0.004) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D C X K REF 0.0 (0.004) M T U S S N (0.00) M B U A G H N J J F DETAIL E K K ÇÇÇ ÉÉÉ SECTION N N DETAIL E W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY.. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M SOLDERING FOOTPRINT* PITCH X 0.36 X.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has four identical 2-input multiplexers with
Dual 4-Input Data Selector/Multiplexer High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C153A Dual 4-Input Data Selector/Multiplexer igh-performance Silicon-ate CMOS The IN74C153A is identical in pinout to the LS/ALS153. The device inputs are compatible with standard CMOS
SN74LS153D 74LS153 LOW POWER SCHOTTKY
74LS153 The LSTTL/MSI SN74LS153 is a very high speed Dual 4-Input Multiplexer with common select inputs and individual enable inputs for each section. It can select two bits of data from four sources.
Hex 3-State Noninverting Buffer with Common Enables High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C365A ex 3-State Noninverting Buffer with Common Enables igh-performance Silicon-ate CMOS The IN74C365A is identical in pinout to the LS/ALS365. The device inputs are compatible with
Dual 4-Input AND Gate
TENIAL DATA Dual 4-Input AND ate The is high-speed Si-gate MOS device and is pin compatible with low power Schottky TTL (LSTTL). The device provide the Dual 4-input AND function. Outputs Directly Interface
8-Input Data Selector/Multiplexer with 3-State Outputs High-Performance Silicon-Gate CMOS
TECNICAL DATA IN74C251A 8-Input Data Selector/Multiplexer with 3-State Outputs igh-performance Silicon-ate CMOS The IN74C251A is identical in pinout to the LS/ALS251. The device inputs are compatible with
MM74HC164 8-Bit Serial-in/Parallel-out Shift Register
8-Bit Serial-in/Parallel-out Shift Register General Description Ordering Code: September 1983 Revised February 1999 The MM74HC164 utilizes advanced silicon-gate CMOS technology. It has the high noise immunity
MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
February 1990 Revised May 1999 MM74HCT573 MM74HCT574 Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT573 octal D-type latches and MM74HCT574 octal D-type flip-flop advanced
74HC123; 74HCT123. Dual retriggerable monostable multivibrator with reset
Product data sheet 1. General description 2. Features The are high-speed Si-gate CMOS devices and are pin compatible with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard
74VHC00 Quad 2-Input NAND Gate
Quad 2-Input NAND Gate General Description The HC00 is an advanced high-speed CMOS 2-Input NAND Gate fabricated with silicon gate CMOS technology. It achieves the high-speed operation similar to equivalent
NL27WZ126. Dual Buffer with 3 State Outputs. The NL27WZ126 is a high performance dual noninverting buffer operating from a 1.65 V to 5.5 V supply.
Dual Buffer with 3 State Outputs The NL27WZ126 is a high performance dual noninverting buffer operating from a 1.65 to 5.5 supply. Features Extremely igh Speed: t PD 2.6 ns (typical) at = 5.0 Designed
Battery Monitors Notebooks and PDA s General Purpose Portable Devices General Purpose Low Voltage Applications +V CC.
LMV33, NCV33, LMV393, LMV339 Single, Dual, Quad General Purpose, Low Voltage Comparators The LMV33 is a CMOS single channel, general purpose, low voltage comparator. The LMV393 and LMV339 are dual and
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop
MM74HCT373 MM74HCT374 3-STATE Octal D-Type Latch 3-STATE Octal D-Type Flip-Flop General Description The MM74HCT373 octal D-type latches and MM74HCT374 Octal D-type flip flops advanced silicon-gate CMOS
Triple 3-Input NOR Gate
TENIAL DATA IN4T2A Triple 3-Input NOR ate The IN4T2A is high-speed Si-gate MOS device and is pin compatible with low power Schottky TTL (LSTTL). The device provide the Triple 3-input NOR function. Outputs
MC74AC00, MC74ACT00. Quad 2 Input NAND Gate. High Performance Silicon Gate CMOS
Quad 2Input NAND Gate ighperformance SiliconGate CMOS Features Output Drive Capability: 24 ma Operating oltage Range: 2 to 6 AC00; to ACT00 ow Input Current:.0 A igh Noise Immunity Characteristic of CMOS