IN74HC164А 8-Bit Serial-Input/Parallel-Output Shift Register

Size: px

Start display at page:

Download "IN74HC164А 8-Bit Serial-Input/Parallel-Output Shift Register"

Noel Harrell
5 years ago
Views:

1 TECHNICAL DATA IN74HC164А 8-Bit Serial-Input/Parallel-Output Shift Register High-Performance Silicon-Gate CMOS The IN74HC164 is identical in pinout to the LS/ALS164. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. The IN74HC164 is an 8-bit, serial-input to parallel-output shift register. Two serial data inputs, A1 and A2, are provided so that one input may be used as a data enable. Data is entered on each rising edge of the clock. The active-low asynchronous Reset overrides theclock and Serial Data inputs. Outputs Directly Interface to CMOS, NMOS, and TTL Operating oltage Range: to Low Input Current: 1.0 μa High Noise Immunity Characteristic of CMOS Devices ORDERING INFORMATION IN74HC164АN Plastic IN74HC164АD SOIC IZ74HC164A Chip T A = - to 12 C for all packages PIN ASSIGNMENT LOGIC DIAGRAM FUNCTION TABLE PIN 14 = CC PIN 7 = GND Inputs Outputs RESET CLOCK A1 A2 QA QB QH L X X X L L L H X X no change H H D D QAn QGn H D H D QAn QGn D = data input X = don t care Q An - Q Gn = data shifted from the previous stage on a rising edge at the clock input. 1

2 MAXIMUM RATINGS * Symbol Parameter alue Unit CC DC Supply oltage (Referenced to GND) -0. to +7.0 IN DC Input oltage (Referenced to GND) -1. to CC +1. OUT DC Output oltage (Referenced to GND) -0. to CC +0. I IN DC Input Current, per Pin ± ma I OUT DC Output Current, per Pin ±2 ma I CC DC Supply Current, CC and GND Pi ±0 ma P D Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Tstg Storage Temperature -6 to +10 C T L Lead Temperature, 1 mm from Case for 10 Seconds 260 C (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditio. +Derating - Plastic DIP: - 10 mw/ C from 6 to 12 C SOIC Package: : - 7 mw/ C from 6 to 12 C mw RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to GND) IN, OUT DC Input oltage, Output oltage (Referenced to GND) 0 CC T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time (Figure 1) CC = CC =4. CC = This device contai protection circuitry to guard agait damage due to high static voltages or electric fields. However, precautio must be taken to avoid applicatio of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, IN and OUT should be cotrained to the range GND ( IN or OUT ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or CC ). Unused outputs must be left open. 2

3 DC ELECTRICAL CHARACTERISTICS(oltages Referenced to GND) Symbol Parameter Test Conditio 2 C to - C IH Minimum High- Level Input oltage IL Maximum Low - Level Input oltage OH Minimum High- Level Output oltage OUT = or CC - I OUT μa OUT = or CC - I OUT μa IN = IH or IL I OUT μa CC Guaranteed Limit C C Unit IN = IH or IL I OUT 4.0 ma I OUT.2 ma OL Maximum Low- Level Output oltage IN = IH or IL I OUT μa 4. I IN I CC Maximum Input Leakage Current Maximum Quiescent Supply Current (per Package) IN = IH or IL I OUT 4.0 ma I OUT.2 ma IN = CC or GND ± ±1.0 ±1.0 μa IN = CC or GND I OUT =0μA μa 3

4 AC ELECTRICAL CHARACTERISTICS(C L =0pF,Input t r =t f = ) CC Symbol Parameter 2 C to - C f max t PLH, t PHL t PHL t TLH, t THL Maximum Clock Frequency (0% Duty Cycle) (Figures 1 and 4) Maximum Propagation Delay,Clock to Q (Figures 1 and 4) Maximum Propagation Delay,Reset to Q (Figures 2 and 4) Maximum Output Traition Time, Any Output (Figures 1 and 4) Guaranteed Limit 8 C 12 C Unit C IN Maximum Input Capacitance pf t SU Minimum Setup Time,A1 or A2 to Clock (Figure 3) t h t rec Minimum Hold Time, Clock to A1 or A2 (Figure 3) Minimum Recovery Time, Reset Inactive to Clock (Figure 2) t w Minimum Pulse Width, Reset (Figure 2) 4. t w Minimum Pulse Width, Clock (Figure 1) 4. t r, t f Maximum Input Rise and Fall Times (Figure 1) MHz C PD Power Dissipation Capacitance (Per Package) Used to determine the no-load dynamic power coumption: P D =C PD CC 2 f+i CC CC C, CC = pf 4

5 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms TIMING DIAGRAM Figure 4. Test Circuit EXPANDED LOGIC DIAGRAM

6 CHIP PAD DIAGRAM Chip marking 164 c ± (0,0) 1.9 ± 0.03 Location of marking (mm): left lower corner х=0.282, у= 1.28; right lower corner х=0.374,у=1.288 Chip thickness: 0.46±0.02 mm PAD LOCATION Pad No Symbol Location (left lower corner), mm Pad size, mm X Y 01 А х А х QA х QB х 06 0 QC х QD х GND х CLOCK х RESET х QE х QF х QG х QH х cc х 06 Note: Location is given as per passivation layer 6

Octal 3-State Noninverting Transparent Latch

SL74HC73 Octal 3-State Noninverting Traparent Latch High-Performance Silicon-Gate CMOS The SL74HC73 is identical in pinout to the LS/ALS73. The device inputs are compatible with standard CMOS outputs;