74LS195 SN74LS195AD LOW POWER SCHOTTKY

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The SN74LS95A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications.

1 The SN74LS95A is a high speed 4-Bit Shift Register offering typical shift frequencies of 39 MHz. It is useful for a wide variety of register and counting applications. It utilizes the Schottky diode clamped process to achieve high speeds and is fully compatible with all ON Semiconductor TTL products. Typical Shift Right Frequency of 39 MHz Asynchronous Master Reset, K Inputs to First Stage Fully Synchronous Serial or Parallel Data Transfers Input Clamp Diodes Limit High Speed Termination Effects 74LS95 LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage V T A Operating Ambient Temperature Range C I OH Output Current High 0.4 ma I OL Output Current Low 8.0 ma 6 PLASTIC N SUFFIX CASE SOIC D SUFFIX CASE 75B Device SN74LS95AN SN74LS95AD Package 6 Pin DIP 6 Pin

2 CONNECTION DIAGRAM DIP (TOP VIEW) V CC Q 0 Q Q 2 Q 3 Q 3 PE NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package MR K P 0 P P 2 P 3 GND LOADING (Note a) PIN NAMES HIGH LOW PE P 0 P 3 K MR Q 0 Q 3 Q 3 Parallel Enable (Active LOW) Input Parallel Data Inputs First Stage (Active HIGH) Input First Stage K (Active LOW) Input Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input Parallel Outputs Complementary Last Stage Output 0 U.L. 0 U.L. 5 U.L. 5 U.L. NOTES: a) TTL Unit Load (U.L.) = 40 A HIGH/.6 ma LOW. LOGIC SYMBOL PE P 0 P P 2 P 3 Q 3 K MR Q 0 Q Q 2 Q V CC = PIN 6 GND = PIN 8 2 2

3 9 LOGIC DIAGRAM PE K P 0 P P 2 P 3 MR R C D Q 0 S Q 0 R C D S Q 0 R C D S Q 2 R C D Q 3 S Q 3 V CC = PIN 6 GND = PIN 8 = PIN NUMBERS Q 0 Q Q 2 Q 3 Q 3 FUNCTIONAL DESCRIPTION The Logic Diagram and Truth Table indicate the functional characteristics of the LS95A 4-Bit Shift Register. The device is useful in a wide variety of shifting, counting and storage applications. It performs serial, parallel, serial to parallel, or parallel to serial data transfers at very high speeds. The LS95A has two primary modes of operation, shift right (Q 0 Q ) and parallel load which are controlled by the state of the Parallel Enable (PE) input. When the PE input is HIGH, serial data enters the first flip-flop Q 0 via the and K inputs and is shifted one bit in the direction Q 0 Q Q 2 Q 3 following each LOW to HIGH clock transition. The K inputs provide the flexibility of the K type input for special applications, and the simple D type input for general applications by tying the two pins together. When the PE input is LOW, the LS95A appears as four common clocked D flip-flops. The data on the parallel inputs P 0, P, P 2, P 3 is transferred to the respective Q 0, Q, Q 2, Q 3 outputs following the LOW to HIGH clock transition. Shift left operations (Q 3 Q 2 ) can be achieved by tying the Q n Outputs to the P n inputs and holding the PE input LOW. All serial and parallel data transfers are synchronous, occurring after each LOW to HIGH clock transition. Since the LS95A utilizes edge-triggering, there is no restriction on the activity of the, K, P n and PE inputs for logic operation except for the set-up and release time requirements. A LOW on the asynchronous Master Reset (MR) input sets all Q outputs LOW, independent of any other input condition. MODE SELECT TRUTH TABLE OPERATING MODES INPUTS OUTPUTS MR PE K P n Q 0 Q Q 2 Q 3 Q 3 Asynchronous Reset L X X X X L L L L H Shift, Set First Stage H h h h X H q 0 q q 2 q 2 Shift, Reset First H h I I X L q 0 q q 2 q 2 Shift, Toggle First Stage H h h I X q 0 q 0 q q 2 q 2 Shift, Retain First Stage H h I h X q 0 q 0 q q 2 q 2 Parallel Load H I X X p n p 0 p p 2 p 3 p 3 L = LOW voltage levels H = HIGH voltage levels X = Don t Care I = LOW voltage level one set-up time prior to the LOW to HIGH clock transition. h = HIGH voltage level one set-up time prior to the LOW to HIGH clock transition. p n (q n ) = Lower case letters indicate the state of the referenced input (or output) one set-up time prior to the LOW to HIGH clock transition. 3

4 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions V IH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs V IL Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage for All Inputs V IK Input Clamp Diode Voltage V V CC = MIN, I IN = 8 ma V OH Output HIGH Voltage V V CC = MIN, I OH = MAX, V IN = V IH or V IL per Truth Table V OL Output LOW Voltage V I OL = 4.0 ma V CC = V CC MIN, V IN =V IL or V IH V I OL = 8.0 ma per Truth Table I IH Input HIGH Current 20 µa V CC = MAX, V IN = 2.7 V 0. ma V CC = MAX, V IN = 7.0 V I IL Input LOW Current 0.4 ma V CC = MAX, V IN = 0.4 V I OS Short Circuit Current (Note ) ma V CC = MAX I CC Power Supply Current 2 ma V CC = MAX Note : Not more than one output should be shorted at a time, nor for more than second. AC CHARACTERISTICS (T A = 25 C) Limits Symbol Parameter Min Typ Max Unit Test Conditions f MAX Maximum Clock Frequency MHz t PLH Propagation Delay, Clock to Output Propagation Delay, MR to Output AC SETUP REQUIREMENTS (T A = 25 C) ns 9 30 ns Limits V CC = 5.0 V C L = 5 pf Symbol Parameter Min Typ Max Unit Test Conditions t W Clock Pulse Width 6 ns t W MR Pulse Width 2 ns t s PE Setup Time 25 ns t s Data Setup Time 5 ns V CC = 5.0 V t rec Recovery Time 25 ns t rel PE Release Time 0 ns t h Data Hold Time 0 ns 4

5 DEFINITIONS OF TERMS SETUP TIME(t s ) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOLD TIME (t h ) is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (t rec ) is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH Data to the Q outputs. AC WAVEFORMS The shaded areas indicate when the input is permitted to change for predictable output performance. PE t W & K t s (L) t s (H) t h (L) = 0 t h (H) = 0 OUTPUT t PLH P 0 P P 2 P 3 t h (L) = 0 OUTPUT* t s (L) t s (H) t h (H) = 0 CONDITIONS: = PE = MR = H K = L Figure. Clock to Output Delays and Clock Pulse Width CONDITIONS: MR = H * AND K SET UP TIME AFFECTS Q 0 ONLY Figure 3. Setup (t s ) and Hold (t h ) Time for Serial Data ( & K) and Parallel Data (P 0, P, P 2, P 3 ) MR OUTPUT t W CONDITIONS: PE = L PO = P = P 2 = P 3 = H Figure 2. Master Reset Pulse Width, Master Reset to Output Delay and Master Reset to Clock Recovery Time t rec PE OUTPUT LOAD PARALLEL DATA t s (L) t rel t s (H) LOAD SERIAL DATA SHIFT RIGHT Q n = P n Q n * = Q n CONDITIONS: MR = H *Q 0 STATE WILL BE DETERMINED BY AND K INPUTS. Figure 4. Setup (t s ) and Hold (t h ) Time for PE Input t rel 5

6 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE ISSUE R 6 A 8 H G F 9 D 6 PL B S C K 0.25 (0.00) M T SEATING T PLANE A M L M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G 0.00 BSC 2.54 BSC H BSC.27 BSC K L M S

7 D SUFFIX PLASTIC SOIC PACKAGE CASE 75B 05 ISSUE T SEATING PLANE G A K B D 6 PL 0.25 (0.00) M T B S A S P 8 PL 0.25 (0.00) M B S C M R X 45 F NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G.27 BSC BSC K M P R

SN74LS153D 74LS153 LOW POWER SCHOTTKY

SN74LS153D 74LS153 LOW POWER SCHOTTKY 74LS153 The LSTTL/MSI SN74LS153 is a very high speed Dual 4-Input Multiplexer with common select inputs and individual enable inputs for each section. It can select two bits of data from four sources.