NTE40194B Integrated Circuit CMOS, 4 Bit Bidirectional Universal Shift Register

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Abraham Ross
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NTE4194B Integrated Circuit CMOS, 4Bit Bidirectional Universal Shift Register Description: The NTE4194B is a universal shift register in a 16Lead DIP type package featuring parallel inputs, parallel

1 NTE4194B Integrated Circuit CMOS, 4Bit Bidirectional Universal Shift Register Description: The NTE4194B is a universal shift register in a 16Lead DIP type package featuring parallel inputs, parallel outputs SHIFT RIGHT and SHIFT LEFT serial inputs, an a direct overriding clear input. In the parallelload mode (S and S1 are high), dat is loaded into the associated flipflop and appears at the output after the positive traition of the CLOCK input. During loading, serial data flow is inhibited. Shift right and shift left are accomplished synchronously on the positive clock edge with data entered at the SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clocking of the register is inhibited when both mode control inputs are low. When low, the RESET input resets all stages and forces all outputs low. Features: MediumSpeed Operation: f CL = 12Mhz (TYP) at = V Full Static Operation Synchronous Parallel or Serial Operation Asynchronous Master Reset Standardized, Symmetrical Output Characteristics 5V, V, and V Parametric Ratings Applicatio: Arithmetic Unit Bus Registers Serial/Parallel Conversio GeneralPurpose Register for BusOrganized Systems GeneralPurpose Registers Absolute imum Ratings: DC Supply Voltage Range (Voltages Referenced to V SS ),....5 to +2V Input Voltage Range (All Inputs)....5 to +.5V DC Input Current (Any One Input)... ±ma Power Dissipation (Per Package), P D For T A = 55 to + C... 5mW For T A = + to +125 C... Derate Linearly at 12mW/ C to 2mW Device Dissipation (Per Output Traistor) For T A = Full Package Temperature Range... mw Operating Temperature Range, T A to +125 C Storage Temperature Range, T stg to + C Lead Temperature (During Soldering, sec), T L C

2 Recommended Operating Conditio: (T A = +25 C, Note 1 unless otherwise specified) Parameter Symbol Min Limits Supply Voltage Range (Full T A = Full Package Temperature Range) 3 18 V Setup Time D, D3, SR IN, SL IN to Clock t S 5 SELECT, SELECT 1 to Clock 5 Hold Time D, D3, SR IN, SL IN to Clock t H 5 SELECT, SELECT 1 to Clock 5 Clock Pulse Width t W 5 Clock Input Frequency f CL 5 Clock Input Rise or Fall Time t r CL, t f CL Reset Pulse Width t WR Unit Mhz Mhz MHz Note 1. For maximum reliability, nominal operating conditio should be selected so that operation is always within the above ranges. Static Electrical Characteristics: Characteristic Conditio Limits at Indicated Temperature ( C) Units Quiescent Device Current, I DD Output Low (Sink) Current I OL Min. Output High (Source) Current I OH Min. V O V IN 55 C 4 C +85 C +125 C +25 C Min. Typ.., μa, μa, μa, μa.4, ma.5, ma 1.5, ma 4.6, ma ma 9.5, ma 13.5, ma

3 Static Electrical Characteristics (Cont d): Characteristic Conditio Limits at Indicated Temperature ( C) Units V O V IN 55 C 4 C +85 C +125 C +25 C Min. Typ.. Output Voltage, V LowLevel V OL.,.5.5 V,.5.5 V Output Voltage, V HighLevel V OH Min., V, V Input Voltage.5, V LowLevel V IL. 1, V 1.5, V Input Voltage.5, V HighLevel V IH Min V 1.5, V Input Current, I IN.,18 18 ±.1 ±.1 ±1. ±1. ± 5 ±.1 μa 3State Output Leakage Current, I OUT.,18,18 18 ±.4 ±.4 ±12 ±12 ± 4 ±.4 μa Dynamic Electrical Characteristics: (T A = +25 C, C L = 5pF, R L = 2kΩ, t r and t f = 2 unless otherwise specified) Parameter Symbol Test Conditio Min Typ Unit Clock Operation Propagation Delay Time t PHL or t PLH = 5V Clock to Q = V 2 = V 7 14 Output Traition Time t THL, t TLH = 5V 2 = V 5 = V 4 8 Minimum Setup Time: t s = 5V 8 16 D, D3, SR IN, L IN to Clock = V 35 7 = V 2 5 SELECT, SELECT 1 to Clock = 5V 2 4 = V 1 22 = V Minimum Hold Time: t H = 5V 65 D, D3, SR IN, L IN to Clock = V 25 = V SELECT, SELECT 1 to Clock = 5V 17 = V 95 = V 55

4 Dynamic Electrical Characteristics (Cont d): (T A = +25 C, C L = 5pF, R L = 2kΩ, t r and t f = 2 unless otherwise specified) Parameter Symbol Test Conditio Min Typ Unit Minimum Clock Pulse Width t W = 5V 9 18 = V 4 8 = V 25 5 imum Clock Input Frequency f CL = 5V MHz = V MHz = V 8.. MHz imum Clock Rise or Fall Time t r CL, = 5V t f CL = V = V Minimum Reset Pulse Width t WR = 5V 3 = V 2 = V 7 14 Reset Propagation Delay t PRHL = 5V = V 9 18 = V Input Capacitance C IN Any Input pf Control Truth Table Mode Select CLOCK S S 1 RESET Action X 1 No Change 1 1 Shift Right (Q toward Q3) 1 1 Shift Left (Q3 toward Q) Parallel Load X X X Reset 1 = High Level = Low Level X = Don t Care

5 Pin Connection Diagram Reset 1 16 Shift Right 2 Q D 3 14 Q1 D Q2 D2 D3 Shift Left Q3 11 Clock S1 V SS 8 9 S (22.).26 (6.6).2 (5.8). (2.54).99 (2.5) Min.7 (17.78)

NTE40160B, NTE40161B NTE40162B, NTE40163B Integrated Circuit CMOS, Synchronous Programmable 4 Bit Counters

NTE40160B, NTE40161B NTE40162B, NTE40163B Integrated Circuit CMOS, Synchronous Programmable 4Bit Counters Description: The NTE40160B (Decade w/asynchronous Clear), NTE40161B (Binary w/asynchronous Clear),