Octal 3-State Noninverting Transparent Latch

Transcription

1 TECNICAL DATA IN74CT373A Octal 3-State Noninverting Transparent Latch The IN74CT373A may be used as a level converter for interfacing TTL or NMOS outputs to igh-speed CMOS inputs. The IN74CT373A is identical in pinout to the LS/ALS373. The eight latches of the IN74CT373A are transparent D-type latches. While the Latch Enable is high the Q outputs follow the Data Inputs. When Latch Enable is taken low, data meeting the setup and hold times becomes latched. The Output Enable does not affect the state of the latch, but when Output Enable is high, all outputs are forced to the high-impedance state. Thus, data may be latched even when the outputs are not enabled. TTL/NMOS-Compatible Input Levels Outputs Directly Interface to CMOS, NMOS, and TTL Operating oltage Range: to Low Input Current: 1.0 µa ORDERIN INFORMATION IN74CT373AN Plastic IN74CT373ADW SOIC T A = -55 to 125 C for all packages PIN ASSINMENT LOIC DIARAM FUNCTION TABLE PIN 20= CC PIN 10 = ND Output Enable Inputs Latch Enable D Output Q L L L L L L X No Change X X Z X = Don t Care Z = igh Impedance

2 MAXIMUM RATINS * Symbol Parameter alue Unit CC DC Supply oltage (Referenced to ND) -0.5 to +7.0 IN DC Input oltage (Referenced to ND) -1.5 to CC +1.5 OUT DC Output oltage (Referenced to ND) -0.5 to CC +0.5 I IN DC Input Current, per Pin ±20 ma I OUT DC Output Current, per Pin ±35 ma I CC DC Supply Current, CC and ND Pins ±75 ma P D Power Dissipation in Still Air, Plastic DIP** SOIC Package** Tstg Storage Temperature -65 to +150 C T L Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. **Derating - Plastic DIP: - 10 mw/ C from 65 to 125 C SOIC Package: : - 7 mw/ C from 65 to 125 C mw 260 C RECOMMENDED OPERATIN CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to ND) IN, OUT DC Input oltage, Output oltage (Referenced to ND) 0 CC T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time (Figure 1) ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. owever, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, IN and OUT should be constrained to the range ND ( IN or OUT ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either ND or CC ). Unused outputs must be left open.

3 DC ELECTRICAL CARACTERISTICS (oltages Referenced to ND) Symbol Parameter Test Conditions 25 C to -55 C I Minimum igh- Level Input oltage IL Maximum Low - Level Input oltage O Minimum igh- Level Output oltage OUT = or CC - I OUT 20 µa OUT = or CC - I OUT 20 µa IN = I or IL I OUT 20 µa CC uaranteed Limit C C Unit IN = I or IL I OUT 6.0 ma OL Maximum Low- Level Output oltage IN = IL or I I OUT 20 µa I IN I OZ I CC I CC Maximum Input Leakage Current Maximum Three- State Leakage Current Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current IN = IL or I I OUT 6.0 ma IN = CC or ND ± ±1.0 ±1.0 µa Output in igh-impedance State IN = IL or I OUT = CC or ND IN = CC or ND I OUT =0µA IN =2.4, Any One Input IN = CC or ND, Other Inputs ±0.5 ±5.0 ±10 µa µa -55 C 25 C to 125 C I OUT =0µA ma

4 AC ELECTRICAL CARACTERISTICS ( CC =5.0 ± 10%, C L =50pF, t r =t f =6.0 ns) Symbol Parameter 25 C to -55 C t PL, t PL t PL, t PL t PLZ, t PZ t PZL, t PZ t TL, t TL Maximum Propagation Delay, Input D to Q (Figures 1 and 5) Maximum Propagation Delay, Latch Enable to Q (Figures 2 and 5) Maximum Propagation Delay,Output Enable to Q (Figures 3 and 6) Maximum Propagation Delay, Output Enable to Q (Figures 3 and 6) Maximum Output Transition Time, Any Output (Figures 1 and 5) uaranteed Limit 85 C 125 C Unit ns ns ns ns ns C IN Maximum Input Capacitance pf C OUT C PD t SU t h Maximum Three-State Output Capacitance (Output in igh-impedance State) Power Dissipation Capacitance (Per Latch) Used to determine the no-load dynamic power consumption: P D =C PD CC 2 f+i CC CC Minimum Setup Time, Input D to Latch Enable (Figure 4) Minimum old Time,Latch Enable to Input D (Figure 4) pf T A =25 C, CC = pf ns ns t w Minimum Pulse Width, Latch Enable (Figure 2) ns t r, t f Maximum Input Rise and Fall Times (Figure 1) ns

5 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Switching Waveforms Figure 5. Test Circuit Figure 6. Test Circuit EXPANDED LOIC DIARAM

6 N SUFFIX PLASTIC DIP (MS - 001AD) 20 1 A B Dimension, mm Symbol MIN MAX A B C 5.33 F L D F D N C -T- K SEATIN PLANE M J J 0 10 K NOTES: 0.25 (0.010) M T 1. Dimensions A, B do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. L M N 0.38 D SUFFIX SOIC (MS - 013AC) -T D A (0.010) M T C M B K P C SEATIN PLANE Symbol MIN MAX A B C D F NOTES: J Dimensions A and B do not include mold flash or protrusion. K Maximum mold flash or protrusion 5 mm (0.006) per side M for A; for B 0.25 mm (0.010) per side. P J R x 45 F M Dimension, mm R