CD54/74HC367, CD54/74HCT367, CD54/74HC368, CD74HCT368

Transcription

1 CD/HC, CD/HCT, CD/HC, CDHCT Data sheet acquired from Harris Semiconductor SCHSD November - Revised October 00 High-Speed CMOS Logic Hex Buffer/Line Driver, Three-State Non-Inverting and Inverting [ /Title (CD HC, CD HCT, CD HC, CD HCT ) /Subject (High Speed Features Buffered Inputs High Bus Driver Outputs Two Independent Three-State Enable Controls Typical Propagation Delay t PLH,t PHL = ns at =V, C L = pf, T A = o C Fanout (Over Temperature Range) - Standard Outputs LS - Bus Driver Outputs LS Wide Operating Temperature Range... - o C to o C Balanced Propagation Delay and Transition Times Significant Power Reduction Compared to LSTTL Logic ICs HC Types - V to V Operation - High Noise Immunity: N IL = 0%, N IH = 0% of at = V HCT Types -.V to.v Operation - Direct LSTTL Input Logic Compatibility, V IL = 0.V (Max), V IH = V (Min) - CMOS Input Compatibility, I l µa at V OL, V OH Description The HC, HCT, HC, and CDHCT silicon gate CMOS three-state buffers are general purpose high-speed non-inverting and inverting buffers. They have high drive current outputs which enable high speed operation even when driving large bus capacitances. These circuits possess the low power dissipation of CMOS circuitry, yet have speeds comparable to low power Schottky TTL circuits. Both circuits are capable of driving up to low power Schottky inputs. The HC and HCT are non-inverting buffers, whereas the HC and CDHCT are inverting buffers. These devices have two output enables, one enable (OE) controls gates and the other (OE) controls the remaining gates. The HCT and CDHCT logic families are speed, function and pin compatible with the standard LS logic family. Ordering Information PART NUMBER TEMP. RANGE ( o C) PACKAGE CDHCFA - to Ld CERDIP CDHCFA - to Ld CERDIP CDHCTFA - to Ld CERDIP CDHCE - to Ld PDIP CDHCM - to Ld SOIC CDHCMT - to Ld SOIC CDHCM - to Ld SOIC CDHCE - to Ld PDIP CDHCM - to Ld SOIC CDHCMT - to Ld SOIC CDHCM - to Ld SOIC CDHCTE - to Ld PDIP CDHCTM - to Ld SOIC CDHCTMT - to Ld SOIC CDHCTM - to Ld SOIC CDHCTE - to Ld PDIP CDHCTM - to Ld SOIC CDHCTMT - to Ld SOIC CDHCTM - to Ld SOIC NOTE: When ordering, use the entire part number. The suffix denotes tape and reel. The suffix T denotes a small-quantity reel of 0. CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright 00, Texas Instruments Incorporated

2 CD/HC, CD/HCT, CD/HC, CDHCT Pinouts CDHC, CDHCT (CERDIP) CDHC, CDHCT (PDIP, SOIC) TOP VIEW CDHC (CERDIP) CDHC, CDHCT (PDIP, SOIC) TOP VIEW OE OE A OE A OE Y A Y A A Y A Y Y A Y A A Y A Y Y 0 A Y 0 A Y Y Functional Diagrams HC, HCT HC, CDHCT OE OE A OE A OE Y A Y A A Y A Y Y A Y A A Y A Y Y 0 A Y 0 A Y Y TRUTH TABLE INPUTS S (Y) OE A HC/HCT HC/HCT L L L H L H H L H X (Z) (Z) H = High Level L = Low Level X = Don t Care Z = High Impedance (OFF) State

3 Logic Diagram CD/HC, CD/HCT, CD/HC, CDHCT ONE OF SIX IDENTICAL CIRCUITS A (NOTE ) Y OE OE A A Y Y 0 A Y A A Y Y NOTE:. Inverter not included in HC/HCT FIGURE. LOGIC DIAGRAM FOR THE HC/HCT AND HC/HCT (S FOR HC/HCT ARE COMPLEMENTS OF THOSE SHOWN, i.e., Y, Y, ETC.)

4 CD/HC, CD/HCT, CD/HC, CDHCT Absolute Maximum Ratings DC Supply, V to V DC Input Diode, I IK For V I < -0.V or V I > + 0.V ±0mA DC Output Diode, I OK For V O < -0.V or V O > + 0.V ±0mA DC Drain, per Output, I O For -0.V < V O < + 0.V ±mA DC or Ground, I CC ±0mA Thermal Information Thermal Resistance (Typical, Note ) θ JA ( o C/W) E (PDIP) Package M (SOIC) Package Maximum Junction Temperature o C Maximum Storage Temperature Range o C to 0 o C Maximum Lead Temperature (Soldering 0s) o C (SOIC - Lead Tips Only) Operating Conditions Temperature Range, T A o C to o C Supply Range, HC Types V to V HCT Types V to.v DC Input or Output, V I, V O V to Input Rise and Fall Time V ns (Max).V ns (Max) V ns (Max) CAUTION: Stresses above those listed in Absolute Maximum Ratings may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE:. The package thermal impedance is calculated in accordance with JESD -. DC Electrical Specifications HC TYPES High Level Input Low Level Input Input Leakage Quiescent Device Three-State Leakage o C -0 o C TO o C - o C TO o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V IH V V V V IL V V V V OH V OL I I I CC I OZ V IH or V V IL V V V V V IH or V V IL V V or or V IL or V IH V O = or V V ±0. - ± - ± µa µa - - ±0. - ±.0 - ±0 µa

5 CD/HC, CD/HCT, CD/HC, CDHCT DC Electrical Specifications (Continued) HCT TYPES High Level Input Low Level Input Input Leakage Quiescent Device Additional Quiescent Device Per Input Pin: Unit Load Three-State Leakage V IH - -. to. V IL - -. to. V OH V OL I I I CC I CC (Note ) I OZ o C -0 o C TO o C - o C TO o C V I (V) I O (ma) (V) MIN TYP MAX MIN MAX MIN MAX V V V IH or V V IL V V IH or V V IL to or -. V IL or V IH V O = or V ±0. - ± - ± µa µa -. to µa. - - ±0. - ±.0 - ±0 µa NOTE:. For dual-supply systems theoretical worst case (V I =.V, =.V) specification is.ma. HCT Input Loading Table INPUT UNIT LOADS OE 0. All Others 0. NOTE: Unit Load is I CC limit specified in DC Electrical Specifications table, e.g., 0µA max at o C. Switching Specifications Input t r, t f = ns HC TYPES HC/HCT (V) o C -0 o C TO o C - o C TO o C TYP MAX MAX MAX t PLH, t PHL C L = 0pF ns. - ns - ns C L = pf ns

6 CD/HC, CD/HCT, CD/HC, CDHCT Switching Specifications Input t r, t f = ns (Continued) HC/HCT t PLH, t PHL C L = 0pF ns. - ns - ns C L = pf ns t PLH, t PHL C L = 0pF ns Output Enable and Disable to Outputs. - 0 ns - ns C L = pf ns Output Transition Time t TLH, t THL C L = 0pF ns. - ns - 0 ns Input Capacitance C I pf Three-State Output Capacitance C O pf Power Dissipation Capacitance (Notes, ) (V) o C -0 o C TO o C C PD pf HCT TYPES t PLH, t PHL C L = 0pF. - ns HC/HCT C L = pf ns t PLH, t PHL C L = 0pF. - 0 ns HC/HCT C L = pf ns t PLH, t PHL C L = 0pF. - ns Output Enable and Disable to Outputs C L = pf ns Output Transition Time t TLH, t THL C L = 0pF. - ns Input Capacitance C IN pf Three-State Capacitance C O pf Power Dissipation Capacitance (Notes, ) C PD pf NOTES:. C PD is used to determine the dynamic power consumption, per buffer.. P D = V CC fi (C PD + C L ) where f i = Input Frequency, C L = Output Load Capacitance, = Supply. - o C TO o C TYP MAX MAX MAX

7 CD/HC, CD/HCT, CD/HC, CDHCT Test Circuits and Waveforms t r = ns t f = ns t r = ns t f = ns INPUT 0% INPUT.V.V 0.V V t THL t TLH t THL t TLH INVERTING t PHL t PLH 0% INVERTING t PHL t PLH.V FIGURE. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC FIGURE. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC ns DISABLE 0% ns t r DISABLE ns t f.. 0. ns V tplz t PZL t PLZ t PZL LOW 0% LOW.V HIGH t PHZ t PZH 0% HIGH t PHZ t PZH.V S S DISABLED S S S DISABLED S FIGURE. HC THREE-STATE PROPAGATION DELAY WAVEFORM FIGURE. HCT THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW DISABLE IC WITH THREE- STATE R L = kω C L 0pF FOR t PLZ AND t PZL FOR t PHZ AND t PZH NOTE: Open drain waveforms t PLZ and t PZL are the same as those for three-state shown on the left. The test circuit is Output R L =kω to, C L = 0pF. FIGURE. HC AND HCT THREE-STATE PROPAGATION DELAY CIRCUIT