74LVC574A Octal D-type flip-flop with 5-volt tolerant inputs/outputs; positive edge-trigger (3-State)
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1 INTEGRATED CIRCUITS inputs/outputs; positive edge-trigger (3-State) 1998 Jul 29
2 FEATURES 5-volt tolerant inputs/outputs, for interfacing with 5-volt logic Supply voltage range of 2.7 to 3.6 Complies with JEDEC standard no. 8-1A Inputs accept voltages up to 5.5 CMOS low power consumption Direct interface with TTL levels igh impedance when CC = 0 8-bit positive edge-triggered register Independent register and 3-State buffer operation Flow-through pin-out architecture DESCRIPTION The is a high-performance, low-power, low-voltage, Si-gate CMOS device, superior to most advanced CMOS compatible TTL families. Inputs can be driven from either 3.3 or 5 devices. In 3-State operation, outputs can handle 5. This feature allows the use of these devices as translators in a mixed 3.3/5 environment. The is an octal D-type flip-flop featuring separate D-type inputs for each flip-flop and 3-State outputs for bus-oriented applications. A clock (CP) and an output enable (OE) input are common to all flip-flops. The eight flip-flops will store the state of their individual D-inputs that meet the setup and hold times requirements on the LOW-to-IG CP transition. When OE is LOW, the contents of the eight flip-flops is available at the outputs. When OE is IG, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The 574A is functionally identical to the 374A, but the 374A has a different pin arrangement. QUICK REFERENCE DATA = 0; T amb =25 C; t r = t f 2.5ns SYMBOL PARAMETER CONDITIONS TYPICAL UNIT t PL /t PL Propagation delay CP to Q n C L = 50pF CC = f max maximum clock frequency 150 Mz C I Input capacitance 5.0 pf C PD Power dissipation capacitance per flip-flop Notes 1 and 2 20 pf NOTE: 1. C PD is used to determine the dynamic power dissipation (P D in W): P D = C PD x 2 CC x f i + (C L x 2 CC x f o ) where: f i = input frequency in Mz; C L = output load capacity in pf; f o = output frequency in Mz; CC = supply voltage in ; (C L x 2 CC x f o ) = sum of outputs. 2. The condition is I = to CC ORDERING INFORMATION ns PACKAGES TEMPERATURE RANGE OUTSIDE NORT AMERICA NORT AMERICA PKG. DWG. # 20-Pin Plastic Shrink Small Outline (SO) 40 C to +85 C D D SOT Pin Plastic Shrink Small Outline (SSOP) Type II 40 C to +85 C DB DB SOT Pin Plastic Thin Shrink Small Outline (TSSOP) Type I 40 C to +85 C PW 7LC574APW D SOT Jul
3 PIN DESCRIPTION PIN NUMBER SYMBOL FUNCTION 1 OE Output enable input (active-low) 2, 3, 4, 5, 6, 7, 8, 9 19, 18, 17, 16, 15, 14, 13, 12 D0-D7 Q0-Q7 Data inputs Data outputs 10 Ground (0) 11 CP Clock input (LOW-to-IG, edge-triggered) 20 CC Positive supply voltage PIN CONFIGURATION LOGIC SYMBOL (IEEE/IEC) 1 C1 11 EN 2 1D OE 1 20 CC SA00402 D0 D Q0 Q1 FUNCTIONAL DIAGRAM D Q2 D3 D4 D5 D6 D Q3 Q4 Q5 Q6 Q7 CP 2 3 D1 Q D0 D2 5 D3 Q3 16 FF! to 3-State 6 D4 Q4 15 FF8 OUTPUTS 7 D5 Q5 14 Q0 Q SA D6 Q D7 Q7 12 LOGIC SYMBOL 11 1 CP OE 11 SA D0 CP Q D1 Q D2 Q D3 Q D4 Q D5 Q D6 Q D7 OE Q SA Jul 29 3
4 LOGIC DIAGRAM D0 D1 D2 D3 D4 D5 D6 D7 D Q D Q D Q D Q D Q D Q D Q D Q CP CP CP CP CP CP CP CP FF1 FF2 FF3 FF4 FF5 FF6 FF7 FF8 CP OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 SA00404 FUNCTION TABLE OPERATING MODES Load and read register Load register and disable outputs = IG voltage level INPUTS OE LE D n INTERNAL FLIP-FLOPS L L h = IG voltage level one setup time prior to the LOW-to-IG CP transition L = LOW voltage level l = LOW voltage level one setup time prior to the LOW-to-IG CP transition Z = igh impedance OFF-state = LOW-to-IG clock transition l h l h L L OUTPUTS Q 0 to Q 7 L Z Z RECOMMENDED OPERATING CONDITIONS LIMITS SYMBOL PARAMETER CONDITIONS MIN MAX DC supply voltage (for max. speed performance) CC DC supply voltage (for low-voltage applications) UNIT I DC Input voltage range O DC output voltage range; output IG or LOW state 0 CC DC output voltage range; output 3-State T amb Operating ambient temperature range in free-air C t r, t f Input rise and fall times CC = 1.2 to 2.7 CC = 2.7 to ns/ 1998 Jul 29 4
5 ABSOLUTE MAXIMUM RATINGS 1 In accordance with the Absolute Maximum Rating System (IEC 134) oltages are referenced to (ground = 0) SYMBOL PARAMETER CONDITIONS RATING UNIT CC DC supply voltage 0.5 to +6.5 I IK DC input diode current I 0 50 ma I DC input voltage Note to +6.5 I OK DC output diode current O CC or O 0 50 ma DC output voltage; output IG or LOW state Note to CC +0.5 O DC output voltage; output 3-State Note to 6.5 I O DC output source or sink current O = 0 to CC 50 ma I, I CC DC CC or current 100 ma T stg Storage temperature range 65 to +150 C Power dissipation per package P TOT plastic mini-pack (SO) above +70 C derate linearly with 8 mw/k 500 plastic shrink mini-pack (SSOP and TSSOP) above +60 C derate linearly with 5.5 mw/k 500 NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. DC ELECTRICAL CARACTERISTICS Over recommended operating conditions voltages are referenced to (ground = 0) LIMITS SYMBOL PARAMETER TEST CONDITIONS Temp = -40 C to +85 C UNIT MIN TYP 1 MAX mw I IL IG level Input voltage LOW level Input voltage CC = 1.2 CC = 2.7 to 3.6 CC 2.0 CC = 1.2 CC = 2.7 to CC = 2.7; I = I or IL ;I O = 12mA CC 0.5 O IG level output voltage CC = 3.0; I = I or IL ;I O = 100µA CC 0.2 CC CC = 3.0; I = I or IL; I O = 18mA CC 0.6 CC = 3.0; I = I or IL; I O = 24mA CC 0.8 CC = 2.7; I = I or IL ;I O = 12mA 0.40 OL LOW level output voltage CC = 3.0; I = I or IL ;I O = 100µA 0.20 CC = 3.0; I = I or IL; I O = 24mA 0.55 I I Input leakage current 2 CC =36; 3.6; I = or µa I OZ 3-State output OFF-state current CC = 3.6; I = I or IL ; O = 5.5 or µa I off Power off leakage supply CC = 0.0; I or O = µa I CC Quiescent supply current CC = 3.6; I = CC or ; I O = µa I CC Additional quiescent supply current per input pin CC = 2.7 to 3.6; I = CC 0.6; I O = µa NOTES: 1. All typical values are at CC = 3.3 and T amb = 25 C. 2. The specified overdrive current at the data input forces the data input to the opposite logic input state Jul 29 5
6 AC CARACTERISTICS = 0; t r = t f 2.5ns; C L = 50pF; R L = 500Ω; T amb = 40 C to +85 C. LIMITS SYMBOL PARAMETER WAEFORM CC = 3.3 ±0.3 CC = 2.7 CC = 1.2 UNIT MIN TYP 1 MAX MIN MAX TYP t PL Propagation delay t PL CP to Q n 1, ns t PZ 3-State output enable time t PZL OE to Q n 2, ns t PZ 3-State output disable time t PLZ OE to Q n 2, ns t W Clock pulse width IG or LOW ns t SU Setup time D n to CP ns t h old time D n to CP ns f max Maximum clock pulse frequency Mz NOTE: 1. Unless otherwise stated, all typical values are at CC = 3.3 and T amb = 25 C. AC WAEFORMS = 1.5 at CC 2.7; = 0.5 CC at CC 2.7. OL and O are the typical output voltage drop that occur with the output load. X = OL at CC 2.7; X = OL CC at CC 2.7 Y = O 0.3 at CC 2.7; Y = O 0.1 CC at CC 2.7 I noe INPUT 1/f max t PLZ t PZL CP INPUT Qn OUTPUT I O OL t w t PL tpl SA00394 Waveform 1. Clock (CP) to output (Q n ) propagation delays, the clock pulse width, output transition times and the maximum clock pulse frequency. I CP INPUT ÉÉÉÉ I ÉÉÉÉ Dn INPUT t su t h t su ÉÉÉÉ É ÉÉÉÉÉÉ t h CC Q n OUTPUT LOW-to-OFF OFF-to-LOW OL O Q n OUTPUT IG-to-OFF OFF-to-IG t PZ outputs enabled X Y outputs disabled Waveform 3. 3-State enable and disable times. TEST CIRCUIT PULSE GENERATOR I R T CC D.U.T. O C L 50pF t PZ S 1 500Ω 500Ω outputs enabled SW x CC Open O Qn OUTPUT Test S 1 NOTE: OL The shaded areas indicate when the input is permitted to change for predictable output performance. SW00107 Waveform 2. Data setup and hold times for the D n input to the CP input. CC I t PL /t PL Open 2.7 CC t PLZ /t PZL 2 x CC t PZ /t PZ SY00003 Waveform 4. Load circuitry for switching times Jul 29 6
7 SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT Jul 29 7
8 SSOP20: plastic shrink small outline package; 20 leads; body width 5.3 mm SOT Jul 29 8
9 TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT Jul 29 9
10 Data sheet status Data sheet status Product status Definition [1] Objective specification Preliminary specification Product specification Development Qualification Production This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product. [1] Please consult the most recently issued datasheet before initiating or completing a design. Definitions Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Disclaimers Life support These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California Telephone Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Date of release: Document order number: yyyy mmm dd 10
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EN: This Datasheet is presented by the m anufacturer. Please v isit our website for pricing and availability at www.hest ore.hu. INTEGRTED CIRCUITS DT SHEET Supersedes data of 1990 Dec 01 2003 Jul 25 FETURES
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Rev. 5 17 November 2011 Product data sheet 1. General description The is 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications.
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Rev. 04 11 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G02 and 74HCT1G02 are high speed Si-gate CMOS devices. They provide a 2-input NOR function. The HC
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INTEGRTED CIRCUITS DT SHEET Quad 2-input NND gate Supersedes data of 1997 ug 26 2003 Jun 30 Quad 2-input NND gate FETURES Complies with JEDEC standard no. 8-1 ESD protection: HBM EI/JESD22-114- exceeds
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Rev. 04 20 July 2007 Product data sheet 1. General description 2. Features 3. Ordering information 74HC1G86 and 74HCT1G86 are high-speed Si-gate CMOS devices. They provide a 2-input EXCLUSIVE-OR function.
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Rev. 0 September 200 Product data sheet 1. General description 2. Features The is a high-performance, low-voltage, Si-gate CMOS device and superior to most advanced CMOS compatible TTL families. The input
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Rev. 01 3 September 2009 Product data sheet 1. General description 2. Features 3. Ordering information is a high-speed Si-gate CMOS device. It provides a 2-input OR function. Symmetrical output impedance
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Rev. 01 29 November 2005 Product data sheet 1. General description 2. Features 3. pplications he is a low-voltage Si-gate CMOS device and is pin and function compatible with the 74HC4020 and 74HC4020.
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Rev. 6 10 July 2012 Product data sheet 1. General description The is 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications. Incorporates
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Rev. 07 18 July 2007 Product data sheet 1. General description 2. Features The provides the single 2-input NOR function. Input can be driven from either 3.3 V or 5 V devices. These features allow the use
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Rev. 02 15 May 2008 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance
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Rev. 04 27 pril 2009 Product data sheet 1. General description 2. Features 3. Ordering information The 74HC2G126 and 74HCT2G126 are high-speed Si-gate CMOS devices. They provide a dual non-inverting buffer/line
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More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS
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Rev. 01 6 October 2006 Product data sheet 1. General description 2. Features 3. Ordering information The is a high-speed Si-gate CMOS device. The provides two buffers. Wide supply voltage range from 2.0
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More informationINTEGRATED CIRCUITS. For a complete data sheet, please also download:
INTEGRATED CIRCUITS DATA SEET For a complete data sheet, please also download: The IC06 74C/CT/CU/CMOS ogic Family Specifications The IC06 74C/CT/CU/CMOS ogic Package Information The IC06 74C/CT/CU/CMOS
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