MM74HC151 8-Channel Digital Multiplexer
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- Blake Waters
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1 8-Channel Digital Multiplexer General Description The MM74HC151 high speed Digital multiplexer utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power dissipation of standard CMOS integrated circuits, it possesses the ability to drive 10 LS-TTL loads. The MM74HC151 selects one of the 8 data sources, depending on the address presented on the A, B, and C inputs. It features both true (Y) and complement (W) outputs. The STROBE input must be at a low logic level to enable this multiplexer. A high logic level at the STROBE forces the W output HIGH and the Y output LOW. Ordering Code: September 1983 Revised February 1999 The 74HC logic family is functionally as well as pin-out compatible with the standard 74LS logic family. All inputs are protected from damage due to static discharge by internal diode clamps to V CC and ground. Features Typical propagation delay data select to output Y: 26 ns Wide operating supply voltage range: 2 6V Low input current: 1 µa maximum Low quiescent supply current: 80 µa maximum (74HC) High output drive current: 4 ma minimum MM74HC151 8-Channel Digital Multiplexer Order Number Package Number Package Description MM74HC151M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, Narrow MM74HC151SJ M16D 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide MM74HC151MTC MTC16 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide MM74HC151N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter X to the ordering code. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View Truth Table Inputs Outputs Select Strobe C B A S Y W X X X H L H L L L L D0 D0 L L H L D1 D1 L H L L D2 D2 L H H L D3 D3 H L L L D4 D4 H L H L D5 D5 H H L L D6 D6 H H H L D7 D7 H = HIGH Level, L = LOW Level, X = Don't Care D0, D1...D7 = the level of the respective D input
2 Logic Diagram
3 Absolute Maximum Ratings(Note 1) (Note 2) Supply Voltage (V CC ) 0.5 to +7.0V DC Input Voltage (V IN ) 1.5 to V CC +1.5V DC Output Voltage (V OUT ) 0.5 to V CC +0.5V Clamp Diode Current (I IK, I OK ) ±20 ma DC Output Current, per pin (I OUT ) ±25 ma DC V CC or GND Current, per pin (I CC ) ±50 ma Storage Temperature Range (T STG ) 65 C to +150 C Power Dissipation (P D ) (Note 3) 600 mw S.O. Package only 500 mw Lead Temperature (T L ) 260 C (Soldering 10 seconds) Recommended Operating Conditions Min Max Units Supply Voltage (V CC ) 2 6 V DC Input or Output Voltage 0 V CC V (V IN, V OUT ) Operating Temperature Range (T A ) C Input Rise or Fall Times (t r, t f ) V CC = 2.0V 1000 ns V CC = 4.5V 500 ns V CC = 6.0V 400 ns Note 1: Absolute Maximum Ratings are those values beyond which damage to the device may occur. Note 2: Unless otherwise specified all voltages are referenced to ground. Note 3: Power Dissipation temperature derating plastic N package: 12 mw/ C from 65 C to 85 C. MM74HC151 DC Electrical Characteristics (Note 4) Symbol Parameter Conditions V CC T A = 25 C T A = 40 to 85 C T A = 55 to 125 C Units Typ Guaranteed Limits V IH Minimum HIGH Level 2.0V V Input Voltage 4.5V V 6.0V V V IL Maximum LOW Level 2.0V V Input Voltage 4.5V V 6.0V V V OH Minimum HIGH Level V IN = V IH or V IL Output Voltage I OUT 20 µa 2.0V V 4.5V V 6.0V V V IN = V IH or V IL I OUT 4.0 ma 4.5V V I OUT 5.2 ma 6.0V V V OL Maximum LOW Level V IN = V IH or V IL Output Voltage I OUT 20 µa 2.0V V 4.5V V 6.0V V V IN = V IH or V IL I OUT 4.0 ma 4.5V V I OUT 5.2 ma 6.0V V I IN Maximum Input V IN = V CC or GND 6.0V ±0.1 ±1.0 ±1.0 µa Current I CC Maximum Quiescent V IN = V CC or GND 6.0V µa Supply Current I OUT = 0 µa Note 4: For a power supply of 5V ±10% the worst case output voltages (V OH, and V OL ) occur for HC at 4.5V. Thus the 4.5V values should be used when designing with this supply. Worst case V IH and V IL occur at V CC = 5.5V and 4.5V respectively. (The V IH value at 5.5V is 3.85V.) The worst case leakage current (I IN, I CC, and I OZ ) occur for CMOS at the higher voltage and so the 6.0V values should be used.
4 AC Electrical Characteristics V CC = 5V, T A = 25 C, C L = 15 pf, t r = t f = 6 ns Guaranteed Symbol Parameter Conditions Typ Limit Units t PHL, t PLH Maximum Propagation Delay ns A, B or C to Y t PHL, t PLH Maximum Propagation Delay ns A, B or C to W t PHL, t PLH Maximum Propagation Delay ns Any D to Y t PHL, t PLH Maximum Propagation Delay ns any D to W t PHL, t PLH Maximum Propagation Delay ns Strobe to Y t PHL, t PLH Maximum Propagation Delay ns Strobe to W AC Electrical Characteristics C L = 50 pf, t r = t f = 6 ns (unless otherwise specified) Symbol Parameter Conditions V CC T A = 25 C T A = 40 to 85 C T A = 55 to 125 C Units Typ Guaranteed Limits t PHL, t PLH Maximum Propagation Delay 2.0V ns A, B or C to Y 4.5V ns 6.0V ns t PHL, t PLH Maximum Propagation Delay 2.0V ns A, B or C to W 4.5V ns 6.0V ns t PHL, t PLH Maximum Propagation Delay 2.0V ns any D to Y 4.5V ns 6.0V ns t PHL, t PLH Maximum Propagation Delay 2.0V ns any D to W 4.5V ns 6.0V ns t PHL, t PLH Maximum Propagation Delay 2.0V ns Strobe to Y 4.5V ns 6.0V ns t PHL, t PLH Maximum Propagation Delay 2.0V ns Strobe to W 4.5V ns 6.0V ns t TLH, t THL Maximum Output Rise 2.0V ns and Fall Time 4.5V ns 6.0V ns C PD Power Dissipation (per package) 110 pf Capacitance (Note 5) C IN Maximum Input pf Capacitance Note 5: C PD determines the no load dynamic power consumption, P D = C PD V CC 2 f + I CC V CC, and the no load dynamic current consumption, I S = C PD V CC f + I CC.
5 Physical Dimensions inches (millimeters) unless otherwise noted MM74HC Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, Narrow Package Number M16A 16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M16D
6 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide Package Number MTC16
7 Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, Wide Package Number N16E MM74HC151 8-Channel Digital Multiplexer
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MM54HC173 MM74HC173 TRI-STATE Quad D Flip-Flop General Description The MM54HC173 MM74HC173 is a high speed TRI-STATE QUAD D TYPE FLIP-FLOP that utilizes advanced silicongate CMOS technology It possesses
M74HCT688TTR 8 BIT EQUALITY COMPARATOR
8 BIT EQUALITY COMPARATOR HIGH SPEED: t PD = 21ns (TYP.) at V CC = 4.5V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V IL = 0.8V (MAX) SYMMETRICAL
74LS75 Quad Latch. DM74LS75 Quad Latch. General Description. Ordering Code: Logic Diagram. Connection Diagram. Function Table (Each Latch)
74LS75 Quad Latch General Description These latches are ideally suited for use as temporary storage for binary information between processing units and input/output or indicator units. Information present
MM54HC194 MM74HC194 4-Bit Bidirectional Universal Shift Register
MM54HC194 MM74HC194 4-Bit Bidirectional Universal Shift Register General Description This 4-bit high speed bidirectional shift register utilizes advanced silicon-gate CMOS technology to achieve the low
74F139 Dual 1-of-4 Decoder/Demultiplexer
74F139 Dual 1-of-4 Decoder/Demultiplexer General Description The F139 is a high-speed, dual 1-of-4 decoder/demultiplexer. The device has two independent decoders, each accepting two inputs and providing
Features Y Wide supply voltage range 3 0V to 15V. Y High noise immunity 0 45 VDD (typ ) Y Low power TTL fan out of 2 driving 74L
CD4025 CD4023BM CD4023BC Buffered Triple 3-Input NAND Gate CD4025BM CD4025BC Buffered Triple 3-Input NOR Gate General Description These triple gates are monolithic complementary MOS (CMOS) integrated circuits
M74HC20TTR DUAL 4-INPUT NAND GATE
DUAL 4-INPUT NAND GATE HIGH SPEED: t PD = 9ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 1µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
74LCX112 Low Voltage Dual J-K Negative Edge-Triggered Flip-Flop with 5V Tolerant Inputs
June 1998 Revised February 2001 74LCX112 Low oltage Dual J-K Negative Edge-Triggered Flip-Flop with 5 Tolerant Inputs General Description The LCX112 is a dual J-K flip-flop. Each flip-flop has independent
CD54HC11, CD74HC11, CD54HCT11, CD74HCT11
CDHC, CD7HC, CDHCT, CD7HCT Data sheet acquired from Harris Semiconductor SCHS7E August 997 - Revised September 00 High-Speed CMOS Logic Triple -Input AND Gate [ /Title (CD HCT, CD7 HC, CD7 HCT ) /Subject
74VHC273 Octal D-Type Flip-Flop
74VHC273 Octal D-Type Flip-Flop General Description The VHC273 is an advanced high speed CMOS Octal D-type flip-flop fabricated with silicon gate CMOS technology. It achieves the high speed operation similar
74AC169 4-Stage Synchronous Bidirectional Counter
74AC169 4-Stage Synchronous Bidirectional Counter General Description The AC169 is fully synchronous 4-stage up/down counter. The AC169 is a modulo-16 binary counter. It features a preset capability for
Obsolete Product(s) - Obsolete Product(s)
8-INPUT NAND GATE HIGH SPEED: t PD = 13ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 1µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: I