8-BIT SERIAL-INPUT/PARALLEL-OUTPUT SHIFT RESISTER High-Performance Silicon-Gate CMOS
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1 TECNICAL DATA 8-BIT SERIAL-INPUT/PARALLEL-OUTPUT SIFT RESISTER igh-performance Silicon-ate CMOS The may be used as a level converter for interfacing TTL or NMOS outputs to high-speed CMOS inputs. The is identical in pin out to the LS/ALS164. TTL/NMOS-Compatible Input Levels. Outputs Directly Interface to CMOS, NMOS and TTL. Operating Range: 4.5 to 5.5 Low Input Current: 1.0 µa ORDERIN INFORMATION N Plastic D SOIC T A = -55 to 125 C for all packages LOIC DIARAM PIN ASSINMENT PIN 14 = CC PIN 7 = ND FUNCTION TABLE Inputs Outputs Reset Clock A1 A2 Q A Q B... Q L X X X L L... L X X no change D D Q An... Q n D D Q An... Q n D = data input X = don t care Q An - Q n = data shifted from the previous stage on a rising edge at the clock input.
2 MAXIMUM RATINS * Symbol Parameter alue Unit CC DC Supply (Referenced to ND) -0.5 to +7.0 IN DC Input (Referenced to ND) -1.5 to CC +1.5 OUT DC Output (Referenced to ND) -0.5 to CC +0.5 I IN DC Input Current, per Pin ±20 ma I OUT DC Output Current, per Pin ±25 ma I CC DC Supply Current, CC and ND Pins ±50 ma P D Power Dissipation in Still Air, Plastic DIP+ 750 mw SOIC Package+ 500 Tstg Storage Temperature -65 to +150 C T L Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) 260 C * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. +Derating - Plastic DIP: - 10 mw/ C from -55 to 125 C SOIC Package: : - 7 mw/ C from -55 to 125 C RECOMMENDED OPERATIN CONDITIONS Symbol Parameter Min Max Unit CC DC Supply (Referenced to ND) IN, OUT DC Input, Output (Referenced to ND) 0 CC T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time (Figure 1) ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. owever, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, IN and OUT should be constrained to the range ND ( IN or OUT ) CC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either ND or CC ). Unused outputs must be left open.
3 DC ELECTRICAL CARACTERISTICS(s Referenced to ND) Symbol Parameter Test Conditions 25 C to -55 C I Minimum igh- Level Input IL Maximum Low - Level Input O Minimum igh- Level Output OL Maximum Low- Level Output I IN Maximum Input Leakage Current I CC Maximum Quiescent Supply Current (per Package) Additional Quiescent Supply Current I CC OUT =0.1 or CC -0.1 I OUT 20 µa OUT = CC -0.1 I OUT 20 µa IN = I or IL I OUT 20 µa C C uaranteed Limit C C IN = I or IL I OUT 4.0 ma IN = I I OUT 20 µa Unit IN = I I OUT 4.0 ma IN = CC or ND 5.5 ±0.1 ±1.0 ±1.0 µa IN = CC or ND I OUT =0µA IN = 2.4, Any One Input IN = CC or ND, Other Inputs I OUT =0µA µa -55 C 25 C to 125 C ma
4 AC ELECTRICAL CARACTERISTICS( CC =5.0 ± 10%, C L =50pF, Input t r =t f =6.0 ns) Symbol Parameter 25 C to -55 C uaranteed Limit 85 C 125 C f max Maximum Clock Frequency (50% Duty Mz Cycle) (Figures 1 and 4) t PL, t PL Maximum Propagation Delay,Clock to Q ns (Figures 1 and 4) t PL Maximum Propagation Delay,Reset to Q ns (Figures 2 and 4) t TL, t TL Maximum Output Transition Time, Any ns Output (Figures 1 and 4) C IN Maximum Input Capacitance 10 pf Unit C PD Power Dissipation Capacitance (Per Package) Used to determine the no-load dynamic power consumption: P D =C PD 2 CC f+i CC CC C, CC = pf TIMIN REQUIREMENTS (C L =50pF,Input t r =t f =6.0 ns) uaranteed Limit Symbol Parameter 25 C to 85 C 125 C Unit -55 C t SU Minimum Setup Time,A1 or A2 to Clock (Figure 3) ns t h Minimum old Time, ns Clock to A1 or A2 (Figure 3) t rec Minimum Recovery Time, Reset Inactive to Clock (Figure 2) ns t w Minimum Pulse Width, ns Reset (Figure 2) t w Minimum Pulse Width, ns Clock (Figure 1)
5 Figure 1. Switching Waveforms Figure 2. Switching Waveforms Figure 3. Switching Waveforms Figure 4. Test Circuit TIMIN DIARAM EXPANDED LOIC DIARAM
6 N SUFFIX PLASTIC DIP (MS - 001AA) NOTES: 14 1 A F 0.25 (0.010) M T 1. Dimensions A, B do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. 8 7 D N B -T- SEATIN 5.27 PLANE K D M J F J (0.010) M T C M NOTES: K Dimensions A and B do not include mold flash or protrusion. M Maximum mold flash or protrusion 0.15 mm (0.006) per side P for A; for B 0.25 mm (0.010) per side. R C -T- K SEATIN PLANE M L J Dimension, mm Symbol MIN MAX A B C 5.33 D F J 0 10 K L M N 0.38 D SUFFIX SOIC (MS - 012AB) 14 1 A 8 7 B P C Symbol MIN MAX A B C D F R x 45 Dimension, mm 1.27
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74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to:
Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has octal D-type transparent latches featuring separate
NTE40194B Integrated Circuit CMOS, 4 Bit Bidirectional Universal Shift Register
NTE4194B Integrated Circuit CMOS, 4Bit Bidirectional Universal Shift Register Description: The NTE4194B is a universal shift register in a 16Lead DIP type package featuring parallel inputs, parallel outputs
Obsolete Product(s) - Obsolete Product(s)
3 TO 8 LINE DECODER HIGH SPEED: t PD = 15ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
SN74LS153D 74LS153 LOW POWER SCHOTTKY
74LS153 The LSTTL/MSI SN74LS153 is a very high speed Dual 4-Input Multiplexer with common select inputs and individual enable inputs for each section. It can select two bits of data from four sources.
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74HC393; 74HCT393. Dual 4-bit binary ripple counter
Product data sheet 1. General description 2. Features 3. Quick reference data The 74HC393; HCT393 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified
CD4028BC BCD-to-Decimal Decoder
BCD-to-Decimal Decoder General Description The is a BCD-to-decimal or binary-to-octal decoder consisting of 4 inputs, decoding logic gates, and 10 output buffers. A BCD code applied to the 4 inputs, A,
Obsolete Product(s) - Obsolete Product(s)
DUAL 4 CHANNEL MULTIPLEXER 3 STATE OUTPUT HIGH SPEED: t PD = 16ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL
74HC573; 74HCT573. Octal D-type transparent latch; 3-state. The 74HC573; 74HCT573 is functionally identical to:
Product data sheet 1. General description The is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The has octal D-type transparent latches featuring separate
NTE40160B, NTE40161B NTE40162B, NTE40163B Integrated Circuit CMOS, Synchronous Programmable 4 Bit Counters
NTE40160B, NTE40161B NTE40162B, NTE40163B Integrated Circuit CMOS, Synchronous Programmable 4Bit Counters Description: The NTE40160B (Decade w/asynchronous Clear), NTE40161B (Binary w/asynchronous Clear),
MM74HC244 Octal 3-STATE Buffer
MM74HC244 Octal 3-STATE Buffer General Description The MM74HC244 is a non-inverting buffer and has two active low enables (1G and 2G); each enable independently controls 4 buffers. This device does not
74HC of 8 Decoder/ Demultiplexer. High Performance Silicon Gate CMOS
of 8 Decoder/ Demultiplexer High Performance Silicon Gate CMOS The 74HC38 is identical in pinout to the LS38. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are