NTE40160B, NTE40161B NTE40162B, NTE40163B Integrated Circuit CMOS, Synchronous Programmable 4 Bit Counters

Size: px

Start display at page:

Download "NTE40160B, NTE40161B NTE40162B, NTE40163B Integrated Circuit CMOS, Synchronous Programmable 4 Bit Counters"

Antonia Hart
5 years ago
Views:

NTE40160B, NTE40161B NTE40162B, NTE40163B Integrated Circuit CMOS, Synchronous Programmable 4Bit Counters Description: The NTE40160B (Decade w/asynchronous Clear), NTE40161B (Binary w/asynchronous

1 NTE40160B, NTE40161B NTE40162B, NTE40163B Integrated Circuit CMOS, Synchronous Programmable 4Bit Counters Description: The NTE40160B (Decade w/asynchronous Clear), NTE40161B (Binary w/asynchronous Clear), NTE40162B (Decade w/synchronous Clear), and NTE40163B (Binary w/synchronous Clear) are 4bit synchronous programmable counters in a 16Lead DIP type package. The CLEAR function of the NTE40162B and NTE40163B is synchronous and a low level at the CLEAR input sets all four outputs low on the next positive CLOCK edge. The CLEAR function of the NTE40160B and NTE40161B is asynchronous and a low level at the CLEAR input sets all four outputs low regardless of the state of the CLOCK, LOAD, or ENABLE inputs. A low level at the LOAD input disables the counter and causes the output to agree with the setup data after the next CLOCK pulse regardless of the conditio of the EN- ABLE inputs. The carry lookahead circuitry provides for cascading counters for nbit synchronous applicatio without additional gating. Itrumental in accomplishing this function are two countenable inputs and a carry output (C OUT ). Counting is enabled when both PE and TE inputs are high. The TE input is fed forward to enable C OUT. This enabled output produces a positive output pulse with a duration approximately equal to the positive portion of the Q1 output. This positive overflow carry pulse can be used to enable successive cascaded stages. Logic traitio at the PE or TE inputs may occur when the clock is either high or low. Features: Internal LookAhead for Fast Counting Carry Output for Cascading Synchronous Programmable Clear Asynchronous Input: NTE40160B, NTE40161B Clear Synchronous Input: NTE40162B, NTE40163B Synchronous Load Control Input LowPower TTL Compatibility Standardized, Symmetrical Output Characteristics imum Input Current of 1μA at 18V over Full Package Temperature Range; 0nA at 18V and +25 C Noise Margin (over Full Package Temperature Range): 1V at V DD = 5V, 2V at V DD = V, 2.5V at V DD = V 5V, V, and V Parametric Ratings Applicatio: Programmable Binary and Decade Counting Counter Control/Timers Frequency Dividing

2 Absolute imum Ratings: DC Supply Voltage Range (Voltages Referenced to V SS ), V DD to +20V Input Voltage Range (All Inputs) to V DD +0.5V DC Input Current (Any One Input)... ±ma Power Dissipation (Per Package), P D For T A = 55 to +0 C mW For T A = +0 to +125 C... Derate Linearly at 12mW/ C to 200mW Device Dissipation (Per Output Traistor) For T A = Full Package Temperature Range... 0mW Operating Temperature Range, T A to +125 C Storage Temperature Range, T stg to +0 C Lead Temperature (During Soldering, sec), T L C Recommended Operating Conditio: (T A = +25 C, Note 1 unless otherwise specified) Parameter Symbol V DD Limits Supply Voltage Range (Full T A = Full Package Temperature Range) 3 18 V Setup Time Data to Clock t SU 5 Load to Clock 5 PE o TE to Clock 5 Clear to Clock (NTE40162B, NTE40163B ONLY) 5 All Hold Times t H 5 Clear Removal Time (NTE40160B, NTE40161B ONLY) t rem 5 Clear Pulse Width (NTE40160B, NTE40161B ONLY) t WL 5 Clock Input Frequency f CL 5 Clock Pulse Width t W 5 Clock Rise or Fall Time Min Unit Mhz Mhz MHz Note 1. For maximum reliability, nominal operating conditio should be selected so that operation is always within the above ranges. t r CL t f CL μs μs μs

3 Static Electrical Characteristics: Characteristic Conditio Limits at Indicated Temperature ( C) Units Quiescent Device Current, I DD Output Low (Sink) Current I OL Min. Output High (Source) Current I OH Min. Output Voltage LowLevel V OL. Output Voltage HighLevel V OH Min. Input Voltage LowLevel V IL. Input Voltage HighLevel V IH Min. V O V IN V DD 55 C 40 C +85 C +125 C +25 C Min. Typ.. 0, μa 0, μa 0, μa 0, μa 0.4 0, ma 0.5 0, ma 1.5 0, ma 4.6 0, ma ma 9.5 0, ma , ma 0, V 0, V 0, V 0, V 0, V 0, V 0.5, V 1, V 1.5, V 0.5, V V 1.5, V Input Current, I IN. 0,18 18 ±0.1 ±0.1 ±1.0 ±1.0 ± 5 ±0.1 μa Dynamic Electrical Characteristics: (T A = +25 C, C L = 50pF, R L = 200kΩ, t r and t f = 20 unless otherwise specified) Parameter Symbol Test Conditio Min Typ Unit Clock Operation Propagation Delay Time t PHL or t PLH V DD = 5V Clock to Q V DD = V V DD = V Clock to C OUT V DD = 5V V DD = V V DD = V 140 TE to C OUT V DD = 5V V DD = V 55 1 V DD = V 40 80

4 Dynamic Electrical Characteristics (Cont d): (T A = +25 C, C L = 50pF, R L = 200kΩ, t r and t f = 20 unless otherwise specified) Parameter Symbol Test Conditio Min Typ Unit Minimum Setup Time t SU V DD = 5V Data to Clock V DD = V V DD = V Load to Clock V DD = 5V V DD = V V DD = V PE to TE to Clock V DD = 5V V DD = V 140 V DD = V 50 0 Minimum Hold Time t H V DD = 5V 0 V DD = V 0 V DD = V 0 Traition Time t THL, t TLH V DD = 5V V DD = V 50 0 V DD = V Minimum Clock Pulse Width t W V DD = 5V 85 1 V DD = V 35 V DD = V imum Clock Frequency f CL V DD = 5V MHz V DD = V MHz V DD = V MHz imum Clock Rise or Fall Time (Note 2) t Wr CL, t f CL V DD = 5V 200 μs Clear Operation Propagation Delay Time NTE40160B, NTE40161B ONLY Clear to Q Minimum Setup Time NTE40162B, NTE40163B ONLY Clear to Clock Minimum Hold Time NTE40162B, NTE40163B ONLY Clear to Clock V DD = V μs V DD = V μs t PHL V DD = 5V V DD = V V DD = V t SU V DD = 5V V DD = V 140 V DD = V 50 0 t H V DD = 5V 0 V DD = V 0 V DD = V 0 Note 2. If more than one unit is cascaded in the parallel clocked application, t r CL should be made less than or equal to the sum of the fixed propagation delay at 50pF and the traition time of the carry output driving stage for the estimated capacitive load.

5 Dynamic Electrical Characteristics (Cont d): (T A = +25 C, C L = 50pF, R L = 200kΩ, t r and t f = 20 unless otherwise specified) Parameter Symbol Test Conditio Min Typ Unit Minimum Clear Removal Time NTE40160B, NTE40161B ONLY t rem V DD = 5V V DD = V 50 0 V DD = V 35 Minimum Clear Pulse Width NTE40160B, NTE40161B ONLY t WL V DD = 5V 85 1 V DD = V 35 V DD = V Truth Table CLOCK CLR LOAD PE TE Operation 1 0 X X PRESET X NC 1 1 X 0 NC COUNT X 0 X X X RESET (NTE40160B, NTE40161B) 1 = High Level 0 = Low Level X = Don t Care NC = No Change 0 X X X RESET (NTE40162B, NTE40163B) 1 X X X NC (NTE40162B, NTE40163B) Pin Connection Diagram CLEAR 1 16 V DD CLOCK 2 CARRY OUT P Q1 P Q2 P3 P4 PE Q3 11 Q4 TE V SS 8 9 LOAD

6 (22.0).260 (6.6).200 (5.08).0 (2.54).099 (2.5) Min.0 (17.78)

NTE40194B Integrated Circuit CMOS, 4 Bit Bidirectional Universal Shift Register

NTE40194B Integrated Circuit CMOS, 4 Bit Bidirectional Universal Shift Register NTE4194B Integrated Circuit CMOS, 4Bit Bidirectional Universal Shift Register Description: The NTE4194B is a universal shift register in a 16Lead DIP type package featuring parallel inputs, parallel outputs