NTE4514B & NTE4515B Integrated Circuit CMOS, 4 Bit Latch/4 to 16 Line Decoder
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1 NTE4514B & NTE4515B Integrated Circuit CMOS, 4 Bit Latch/4 to 16 Line Decoder Description: The NTE4514B (output active high option) and NTE4515B (output active low option) are two output options of a 4 to 16 line decoder with latched inputs. The NTE4514B presents a logical 1 at the selected output, whereas the NTE4515B presents a logical 0 at the selected output. The latches are R S type flip flops which hold the last input data presented prior to the strobe transition from 1 to 0. These high and low options of a 4 bit latch/4 to 16 line decoder are constructed with N channel and P channel enhancement mode devices in a single monolithic structure. The latches are R S type flip flops and data admitted upon a signal incident at the strobe input, decoded, and presented at the output. These complementary circuits find primary use in decoding applications where low power dissipation and/or high immunity is desired. Features: Quiescent Current = 5nA/Package (Typ) at 5Vdc Noise Immunity = 45% of (Typ) Supply Voltage Range: 3Vdc to 18Vdc Capable of Driving Two Low Power TTL Loads, One Low Power Schottky TTL Load or Two HTL Loads Over the Rated Temperature Range Single Supply Operation Positive or Negative Input Impedance = Ohms (Typ) Absolute Maximum Ratings: (Voltages referenced to V SS, Note 1) DC Supply Voltage, to +18.0V Input Voltage (All Inputs), V in to to +0.5V DC Current Drain (Per Pin), I... 10mA Operating Temperature Range, T A to +125 C Storage Temperature Range, T stg to +150 C Note 1. Maximum Ratings are those values beyond which damage to the device may occur. Note 2. These devices contain circuitry to protect the inputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than maximum rated voltages to this high impedance circuit. For proper operation, it is recommended that V in and V out be constrained to the range V SS (V in or V out ). Unused inputs must always be tied to an appropriate logic level (e.g., either V SS or ).
2 Electrical Characteristics: (Voltages referenced to V SS, Note 3) Parameter Symbol Vdc 55 C +25 C +125 C Min Max Min Typ Max Min Max Output Voltage 0 Level V OL Vdc V in = or Vdc Unit Vdc 1 Level V OH Vdc V in = 0 or Vdc Vdc Input Voltage (Note 5) 0 Level (V O = 4.5 or 0.5Vdc) V IL Vdc (V O = 9.0 or 1.0Vdc) Vdc (V O = 13.5 or 1.5Vdc) Vdc 1 Level (V O = 0.5 or 4.5Vdc) V IH Vdc (V O = 1.0 or 9.0Vdc) Vdc (V O = 1.5 or 13.5Vdc) Vdc Output Drive Current Source (V OH = 2.5Vdc) I OH madc (V OH = 4.6Vdc) madc (V OH = 9.5Vdc) madc (V OH = 13.5Vdc) madc Sink (V OL = 0.4Vdc) I OL madc (V OL = 0.5Vdc) madc (V OL = 1.5Vdc) madc Input Current I in 15 ±0.1 ± ±0.1 ±0.1 μadc Input Capacitance (V IN = 0) C in pf Quiescent Current I DD μadc (Per Package) μadc Total Supply Current (Dynamic plus Quiescent, Per Package, C L = 50pF on all outputs, all buffers switching, Note 4, Note 6) μadc I T 5.0 I T = (1.35μA/kHz) f + I DD μadc 10 I T = (2.70μA/kHz) f + I DD μadc 15 I T = (4.05μA/kHz) f + I DD μadc Note 3. Data labeled Typ is not to be used for design purposes but is intended as an indication of the device s potential performance. Note 4. The formulas given are for the typical characteristics only at +25 C. Note 5. Noise immunity specified for worst case input combination. Noise margin for both 1 and 0 = 1.0Vdc = 5Vdc 2.0Vdc = 10Vdc 2.5Vdc = 15Vdc Note 6. To calculate total supply current at loads other than 50pF: I T (C L ) = I T (50pF) + 2 x 10 3 (C L 50) f where: I T is in μa (per package), C L in pf, in Vdc, f in khz is input frequency.
3 Switching Characteristics: (C L = 50pF, T A = +25 C, Note 3) Parameter Symbol Vdc Min Typ Max Unit Output Rise Time t TLH t TLH = (3.0ns/pf) C L + 30ns ns t TLH = (1.5ns/pf) C L + 15ns ns t TLH = (1.1ns/pf) C L + 10ns ns Output Fall Time t THL t THL = (1.5ns/pf) C L + 25ns ns t THL = (0.75ns/pf) C L ns ns t THL = (0.55ns/pf) C L + 9.5ns ns Propagation Delay Time t PLH, t PHL = (1.7ns/pf) C L + 465ns t PLH, t PHL ns t PLH, t PHL = (0.66ns/pf) C L + 192ns ns t PLH, t PHL = (0.5ns/pf) C L + 125ns ns Inhibit Propagation Delay Times t PLH, t PHL = (1.7ns/pf) C L + 315ns t PLH, t PHL ns t PLH, t PHL = (0.66ns/pf) C L + 117ns ns t PLH, t PHL = (0.5ns/pf) C L + 75ns ns Setup Time t su ns ns ns Strobe Pulse Width t WH ns ns ns Note 3. Data labeled Typ is not to be used for design purposes but is intended as an indication of the device s potential performance. Note 4. The formulas given are for the typical characteristics only at +25 C.
4 Truth Table Data Inputs Selected Output NTE4514B = Logic 1 Inhibit D C B A NTE4515B = Logic S S S S S S S S S S S S S S S S15 1 X X X X All Outputs = 0, NTE4514B All Output = 1, NTE4515B X = Don t Care Pin Connection Diagram Strobe Data 1 Data 2 S7 S6 S5 V SS Inhibit Data 4 Data 3 20 S10 19 S11 S4 S S8 S9 S S14 S S15 S S S13
5 (33.02) Max.520 (13.2).225 (5.73) Max.100 (2.54) (27.94).126 (3.22) Min.600 (15.24)
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MM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer
September 1983 Revised February 1999 MM74HC540 MM74HC541 Inverting Octal 3-STATE Buffer Octal 3-STATE Buffer General Description The MM74HC540 and MM74HC541 3-STATE buffers utilize advanced silicon-gate
CD74HC109, CD74HCT109
Data sheet acquired from Harris Semiconductor SCHS140 March 1998 CD74HC109, CD74HCT109 Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger [ /Title (CD74H C109, CD74H CT109) /Subject Dual J- Fliplop
Obsolete Product(s) - Obsolete Product(s)
DUAL 4 CHANNEL MULTIPLEXER 3 STATE OUTPUT HIGH SPEED: t PD = 16ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL
Obsolete Product(s) - Obsolete Product(s)
8-BIT PRIORITY ENCODER CONVERTS FROM 1 TO 8 TO INPUTS BINARY PROVIDES CASCADING FEATURE TO HANDLE ANY NUMBER OF INPUTS GROUP SELECT INDICATES ONE OR MORE PRIORITY INPUTS QUIESCENT CURRENT SPECIFIED UP
CD4723BM CD4723BC Dual 4-Bit Addressable Latch CD4724BM CD4724BC 8-Bit Addressable Latch
CD4723BM CD4723BC Dual 4-Bit Addressable Latch CD4724BM CD4724BC 8-Bit Addressable Latch General Description The CD4723B is a dual 4-bit addressable latch with common control inputs including two address
M74HCT138TTR 3 TO 8 LINE DECODER (INVERTING)
3 TO 8 LINE DECODER (INVERTING) HIGH SPEED: t PD = 16ns (TYP.) at V CC = 4.5V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C COMPATIBLE WITH TTL OUTPUTS : V IH = 2V (MIN.) V IL = 0.8V (MAX) SYMMETRICAL
8-BIT SERIAL-INPUT/PARALLEL-OUTPUT SHIFT RESISTER High-Performance Silicon-Gate CMOS
TECNICAL DATA 8-BIT SERIAL-INPUT/PARALLEL-OUTPUT SIFT RESISTER igh-performance Silicon-ate CMOS The may be used as a level converter for interfacing TTL or NMOS outputs to high-speed CMOS inputs. The is
Obsolete Product(s) - Obsolete Product(s)
3 TO 8 LINE DECODER HIGH SPEED: t PD = 15ns (TYP.) at V CC = 6V LOW POWER DISSIPATION: I CC = 4µA(MAX.) at T A =25 C HIGH NOISE IMMUNITY: V NIH = V NIL = 28 % V CC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:
MM54HC154 MM74HC154 4-to-16 Line Decoder
MM54HC154 MM74HC154 4-to-16 Line Decoder General Description This decoder utilizes advanced silicon-gate CMOS technology and is well suited to memory address decoding or data routing applications It possesses
MM54HC194 MM74HC194 4-Bit Bidirectional Universal Shift Register
MM54HC194 MM74HC194 4-Bit Bidirectional Universal Shift Register General Description This 4-bit high speed bidirectional shift register utilizes advanced silicon-gate CMOS technology to achieve the low
CD4071BC CD4081BC Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate
Quad 2-Input OR Buffered B Series Gate Quad 2-Input AND Buffered B Series Gate General Description The CD4071BC and CD4081BC quad gates are monolithic complementary MOS (CMOS) integrated circuits cotructed
74HC General description. 2. Features. 3-to-8 line decoder, demultiplexer with address latches; inverting
3-to-8 line decoder, demultiplexer with address latches; inverting Rev. 03 11 November 2004 Product data sheet 1. General description 2. Features The is a high-speed Si-gate CMOS device and is pin compatible
UNISONIC TECHNOLOGIES CO., LTD U74HC14
UNISONIC TECHNOLOGIES CO., LTD U74HC14 HIGH-SPEED CMOS LOGIC HEX INVERTING SCHMITT TRIGGER DESCRIPTION The UTC U74HC14 each contain six inverting Schmitt triggers in one package. Each of them perform the
HCF4543B BCD-TO-7-SEGMENT LATCH/DECODER/LCD DRIVER
BCD-TO-7-SEGMENT LATCH/DECODER/LCD DRIVER DISPLAY BLANKING OF ALL ILLEGAL INPUT COMBINATIONS LATCH STORAGE OF CODE INSTRUMENT DISPLAY DRIVER DASHBOARD DISPLAY DRIVER COMPUTER/CALCULATOR DISPLAY DRIVER
DM74LS670 3-STATE 4-by-4 Register File
DM74LS670 3-STATE 4-by-4 Register File General Description August 1986 Revised March 2000 These register files are organized as 4 words of 4 bits each, and separate on-chip decoding is provided for addressing