SN74LS153D 74LS153 LOW POWER SCHOTTKY
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1 74LS153 The LSTTL/MSI SN74LS153 is a very high speed Dual 4-Input Multiplexer with common select inputs and individual enable inputs for each section. It can select two bits of data from four sources. The two buffered outputs present data in the true (non-inverted) form. In addition to multiplexer operation, the LS153 can generate any two functions of three variables. The LS153 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families. Multifunction Capability Non-Inverting Outputs Separate Enable for Each Multiplexer Input Clamp Diodes Limit High Speed Termination Effects LOW POWER SCHOTTKY GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage V T A Operating Ambient Temperature Range C I OH Output Current High 0.4 ma I OL Output Current Low 8.0 ma 1 PLASTIC N SUFFIX CASE SOIC D SUFFIX CASE 751B ORDERING INFORMATION Device Package Shipping SN74LS153N Pin DIP 2000 Units/Box SN74LS153D Pin 2500/Tape & Reel 1
2 CONNECTION DIAGRAM DIP (TOP VIEW) V CC E b S 0 I 3b I 2b I 1b I 0b Z b NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package E a S 1 I 3a I 2a I 1a I 0a Z a GND LOADING (Note a) PIN NAMES HIGH LOW S 0 E I 0, I 1 Z Common Select Input Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L U.L U.L U.L. 5 U.L. NOTES: a) 1 TTL Unit Load (U.L.) = 40 A HIGH/1.6 ma LOW. LOGIC SYMBOL S 0 E a I 0a I 1a I 2a I 3a I 0b I 1b I 2b I 3b E b 2 S a Z a Z b 7 9 V CC = PIN GND = PIN 8 2
3 LOGIC DIAGRAM E a I 0a I 1a I 2a I 3a S 1 S 0 I 0b I 1b I 2b I 3b E b Z a V CC = PIN GND = PIN 8 = PIN NUMBERS 9 Z b FUNCTIONAL DESCRIPTION The LS153 is a Dual 4-input Multiplexer fabricated with Low Power, Schottky barrier diode process for high speed. It can select two bits of data from up to four sources under the control of the common Select Inputs (S 0, S 1 ). The two 4-input multiplexer circuits have individual active LOW Enables (E a, E b ) which can be used to strobe the outputs independently. When the Enables (E a, E b ) are HIGH, the corresponding outputs (Z a, Z b ) are forced LOW. The LS153 is the logic implementation of a 2-pole, 4-position switch, where the position of the switch is determined by the logic levels supplied to the two Select Inputs. The logic equations for the outputs are shown below. Z a = E a (I 0a S 1 S 0 + I 1a S 1 S 0 + I 2a S 1 S 0 + I 3a S 1 S 0 ) Z b = E b (I 0b S 1 S 0 + I 1b S 1 S 0 + I 2b S 1 S 0 + I 3b S 1 S 0 ) The LS153 can be used to move data from a group of registers to a common output bus. The particular register from which the data came would be determined by the state of the Select Inputs. A less obvious application is a function generator. The LS153 can generate two functions of three variables. This is useful for implementing highly irregular random logic. TRUTH TABLE SELECT INPUTS INPUTS (a or b) OUTPUT S 0 S 1 E I 0 I 1 I 2 I 3 Z X X H X X X X L L L L L X X X L L L L H X X X H H L L X L X X L H L L X H X X H L H L X X L X L L H L X X H X H H H L X X X L L H H L X X X H H H = HIGH Voltage Level L = LOW Voltage Level X = Don t Care 3
4 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol Parameter Min Typ Max Unit Test Conditions V IH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs V IL Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage for All Inputs V IK Input Clamp Diode Voltage V V CC = MIN, I IN = 18 ma V OH Output HIGH Voltage V V CC = MIN, I OH = MAX, V IN = V IH or V IL per Truth Table V OL Output LOW Voltage V I OL = 4.0 ma V CC = V CC MIN, V IN =V IL or V IH V I OL = 8.0 ma per Truth Table I IH Input HIGH Current 20 µa V CC = MAX, V IN = 2.7 V 0.1 ma V CC = MAX, V IN = 7.0 V I IL Input LOW Current 0.4 ma V CC = MAX, V IN = 0.4 V I OS Short Circuit Current (Note 1) ma V CC = MAX I CC Power Supply Current 10 ma V CC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (T A = 25 C) Limits Symbol Parameter Min Typ Max Unit Test Conditions Propagation Delay Data to Output ns Figure 2 Propagation Delay Select to Output ns Figure 1 V CC = 5.0 V C L = 15 pf Propagation Delay Enable to Output ns Figure 2 AC WAVEFORMS V IN V IN V OUT V OUT Figure 1. Figure 2. 4
5 PACKAGE DIMENSIONS N SUFFIX PLASTIC PACKAGE CASE ISSUE R A 1 8 H G F 9 D PL B S C K 0.25 (0.010) M T SEATING T PLANE A M J L M NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. INCHES MILLIMETERS DIM MIN MAX MIN MAX A B C D F G BSC 2.54 BSC H BSC 1.27 BSC J K L M S
6 PACKAGE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751B 05 ISSUE J A G B P 8 PL 0.25 (0.010) M B S NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. T SEATING PLANE K C D PL 0.25 (0.010) M T B S A S M R X 45 J F MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 1.27 BSC BSC J K M P R
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