MC74AC74, MC74ACT74. Dual D Type Positive Edge Triggered Flip Flop
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1 Dual D Type Positive Edge Triggered Flip Flop The MC74/T74 is a dual D type flip flop with Asynchronous Clear and Set inputs and complementary (Q,Q) outputs. Information at the input is traferred to the outputs on the positive edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the traition time of the positive-going pulse. After the Clock Pulse input threshold voltage has been passed, the Data input is locked out and information present will not be traferred to the outputs until the next rising edge of the Clock Pulse input. Asynchronous Inputs: LOW input to S D (Set) sets Q to HIGH level LOW input to C D (Clear) sets Q to LOW level Clear and Set are independent of clock Simultaneous LOW on C D and S D makes both Q and Q HIGH Features Outputs Source/Sink 24 ma ACT74 Has TTL Compatible Inputs Pb Free Packages are Available V CC C D2 D 2 CP 2 S D2 Q 2 Q C D S D2 D Q CP 2 Q2 CP S D Q D 2 CD2 Q PDIP 4 N SUFFIX CASE 646 D SUFFIX CASE 75A TSSOP 4 DT SUFFIX CASE 948G SOEIAJ 4 M SUFFIX CASE 965 ORDERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 7 of this data sheet C D D CP S D Q Q GND Figure. Pinout: 4 Lead Packages Conductors (Top View) PIN ASSIGNMENT PIN D, D 2 CP, CP 2 C D, C D2 S D, S D2 Q, Q, Q 2, Q 2 FUNCTION Data Inputs Clock Pulse Inputs Direct Clear Inputs Direct Set Inputs Outputs Semiconductor Components Industries, LLC, 2006 Publication Order Number: MC74/D
2 TRUTH TABLE (Each Half) NOTE: Inputs Outputs S D C D CP D Q Q L H X X H L H L X X L H L L X X H H H H H H L H H L L H H H L X Q 0 Q 0 H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial; = LOW-to-HIGH Clock Traition Q 0 (Q 0 ) = Previous Q(Q) before LOW-to-HIGH Traition of Clock D D CP D Q 2 S D2 D 2 CP 2 Q 2 CD 2 Figure 2. Logic Symbol S D D Q CP Q C D NOTE: This diagram is provided only for the understanding of logic operatio and should not be used to estimate propagation delays. Figure 3. Logic Diagram MAXIMUM RATINGS Symbol Parameter Value Unit V CC DC Supply Voltage (Referenced to GND) 0.5 to +7.0 V V in DC Input Voltage (Referenced to GND) 0.5 to V CC +0.5 V V out DC Output Voltage (Referenced to GND) 0.5 to V CC +0.5 V I in DC Input Current, per Pin ±20 ma I out DC Output Sink/Source Current, per Pin ±50 ma I CC DC V CC or GND Current per Output Pin ±50 ma T stg Storage Temperature 65 to +50 C Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditio is not implied. Extended exposure to stresses above the Recommended Operating Conditio may affect device reliability. 2
3 RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Typ Max Unit V CC Supply Voltage AC ACT V in, V out DC Input Voltage, Output Voltage (Ref. to GND) 0 V CC V t r, t f Input Rise and Fall Time (Note ) AC Devices except Schmitt Inputs t r, t f Input Rise and Fall Time (Note ) ACT Devices except Schmitt Inputs V 3.0 V 50 V 4.5 V 40 /V V 5.5 V 25 V 4.5 V 0 V 5.5 V 8.0 T J Junction Temperature (PDIP) 40 C T A Operating Ambient Temperature Range C I OH Output Current High 24 ma I OL Output Current Low 24 ma. V in from 30% to 70% V CC ; see individual Data Sheets for devices that differ from the typical input rise and fall times. 2. V in from 0.8 V to 2.0 V; see individual Data Sheets for devices that differ from the typical input rise and fall times. DC CHARACTERISTICS V IH V IL Symbol Parameter V OH Minimum High Level Input Voltage Maximum Low Level Input Voltage Minimum High Level Output Voltage V CC (V) T A = +25 C Typ T A = 40 C to +85 C Guaranteed Limits Unit V /V Conditio V OUT = 0. V V or V CC 0. V V OUT = 0. V V or V CC 0. V I OUT = 50 A V V OL Maximum Low Level Output Voltage *V IN = V IL or V IH ma V I OH 24 ma ma I OUT = 50 A V I IN Maximum Input Leakage Current *V IN = V IL or V IH ma V I OL 24 ma ma 5.5 ±0. ±.0 A V I = V CC, GND I OLD Minimum Dynamic ma V OLD =.65 V Max I OHD Output Current ma V OHD = 3.85 V Min I CC Maximum Quiescent Supply Current A V IN = V CC or GND *All outputs loaded; thresholds on input associated with output under test. Maximum test duration 2.0 ms, one output loaded at a time. NOTE: I IN and I 3.0 V are guaranteed to be less than or equal to the respective 5.5 V V CC. 3
4 AC CHARACTERISTICS (For Figures and Waveforms See Section 3 of the ON Semiconductor FACT Data Book, DL38/D) Symbol Parameter V CC * (V) T A = +25 C T A = 40 C to +85 C Min Typ Max Min Max f max Maximum Clock Frequency t PLH C Dn or S Dn to Q n or Q n t PHL C Dn or S Dn to Q n or Q n t PLH C Pn to Q n or Q n t PHL C Pn to Q n or Q n *Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. Unit MHz Fig. No. 3 3 AC OPERATING REQUIREMENTS Symbol Parameter V CC * (V) Typ T A = +25 C T A = 40 C to +85 C Guaranteed Minimum Set-up Time, HIGH or LOW t s D n to CP n Hold Time, HIGH or LOW t h D n to CP n C Pn or C Dn or S Dn t w Pulse Width Recovery TIme t rec C Dn or S Dn to CP *Voltage Range 3.3 V is 3.3 V ±0.3 V. Voltage Range 5.0 V is 5.0 V ±0.5 V. Unit Fig. No
5 ORDERING INFORMATION Device Package Shipping MC74N MC74NG MCT74N MCT74NG MC74D MC74DG MC74DR2 MC74DR2G MCT74D MCT74DG MCT74DR2 MCT74DR2G PDIP 4 PDIP 4 PDIP 4 PDIP 4 25 Units/Rail 55 Units/Rail 55 Units/Rail MC74DT TSSOP 4* 96 Units/Rail MC74DTR2 MC74DTR2G TSSOP 4* TSSOP 4* MCT74DT TSSOP 4* 96 Units/Rail MCT74DTR2 MCT74DTR2G MC74MEL MC74MELG MCT74MEL MCT74MELG TSSOP 4* TSSOP 4* SOEIAJ 4 SOEIAJ 4 SOEIAJ 4 SOEIAJ /Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD80/D. *This package is inherently Pb Free. 7
6 PACKAGE DIMENSIONS PDIP 4 CASE ISSUE P B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. N T SEATING PLANE A INCHES MILLIMETERS DIM MIN MAX MIN MAX A B F L C D C F G 0.00 BSC 2.54 BSC H J K K J L M 0 0 H G D 4 PL M N (0.005) M 9
7 CASE 75A 03 ISSUE H T SEATING PLANE A 4 8 G 7 B P 7 PL 0.25 (0.00) M B M NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES C R X 45 F DIM MIN MAX MIN MAX A B C D D 4 PL K M J F G.27 BSC BSC 0.25 (0.00) M T B S A S J K M P R SOLDERING FOOTPRINT* 4X X X PITCH DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 0
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74F194 4-Bit Bidirectional Universal Shift Register
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74F175 Quad D-Type Flip-Flop
Quad D-Type Flip-Flop General Description The 74F175 is a high-speed quad D-type flip-flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information
74VHC393 Dual 4-Bit Binary Counter
Dual 4-Bit Binary Counter General Description March 1993 Revised March 1999 The HC393 is an advanced high speed CMOS 4-bit Binary Counter fabricated with silicon gate CMOS technology. It achieves the high
LM317L, NCV317LB. 100 ma Adjustable Output, Positive Voltage Regulator LOW CURRENT THREE-TERMINAL ADJUSTABLE POSITIVE VOLTAGE REGULATOR
100 ma Adjustable Output, Positive Voltage Regulator The LM317L is an adjustable 3terminal positive voltage regulator capable of supplying in excess of 100 ma over an output voltage range of 1.2 V to 37
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear
MM74HC74A Dual D-Type Flip-Flop with Preset and Clear General Description The MM74HC74A utilizes advanced silicon-gate CMOS technology to achieve operating speeds similar to the equivalent LS-TTL part.
Presettable Counters High-Performance Silicon-Gate CMOS
TECHNICAL DATA IN74HC1A Presettable Counters High-Performance Silicon-Gate CMOS The IN74HC1A is identical in pinout to the LS/ALS1. The device inputs are compatible with standard CMOS outputs; with pullup
74F579 8-Bit Bidirectional Binary Counter with 3-STATE Outputs
April 1988 Revised October 2000 74F579 8-Bit Bidirectional Binary Counter with 3-STATE Outputs General Description The 74F579 is a fully synchronous 8-stage up/down counter with multiplexed 3-STATE I/O
Figure 1. Pinout: 16 Lead Packages Conductors (Top View) ORDERING INFORMATION Figure 2. Logic Symbol PIN ASSIGNMENT
The MC74AC138/74ACT138 is a high speed 1 of 8 decoder/demultiplexer. This device is ideally suited for high speed bipolar memory chip select address decoding. The multiple input enables allow parallel
SN74LS175MEL. Quad D Flip Flop LOW POWER SCHOTTKY
uad Flip Flop The LSTTL/MSI SN74LS75 is a high speed uad Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the inputs is stored
MC14049B, MC14050B. Hex Buffer
MC4049B, MC4050B Hex Buffer The MC4049B Hex Inverter/Buffer and MC4050B Noninverting Hex Buffer are constructed with MOS PChannel and NChannel enhancement mode devices in a single monolithic structure.
74LVX374 Low Voltage Octal D-Type Flip-Flop with 3-STATE Outputs
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MM74HC595 8-Bit Shift Register with Output Latches
MM74HC595 8-Bit Shift Register with Output Latches Features Low Quiescent current: 80µA Maximum (74HC Series) Low Input Current: 1µA Maximum 8-Bit Serial-In, Parallel-Out Shift Register with Storage Wide
MC14514B, MC14515B. 4 Bit Transparent Latch / 4 to 16 Line Decoder
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MM74HC374 3-STATE Octal D-Type Flip-Flop
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54AC299 54ACT299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins General Description The AC/ ACT299 is an 8-bit universal shift/storage register with TRI-STATE outputs. Four modes
1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS
1-OF-8 DECODER/DEMULTIPLEXER High-Speed Silicon-Gate CMOS The IN74ACT138 is identical in pinout to the LS/ALS138, HC/HCT138. The IN74ACT138 may be used as a level converter for interfacing TTL or NMOS
MM74HC574 3-STATE Octal D-Type Edge-Triggered Flip-Flop
3-STATE Octal D-Type Edge-Triggered Flip-Flop General Description The MM74HC574 high speed octal D-type flip-flops utilize advanced silicon-gate P-well CMOS technology. They possess the high noise immunity
74F269 8-Bit Bidirectional Binary Counter
74F269 8-Bit Bidirectional Binary Counter General Description The 74F269 is a fully synchronous 8-stage up/down counter featuring a preset capability for programmable operation, carry lookahead for easy
MM74HC151 8-Channel Digital Multiplexer
8-Channel Digital Multiplexer General Description The MM74HC151 high speed Digital multiplexer utilizes advanced silicon-gate CMOS technology. Along with the high noise immunity and low power dissipation