MC74LCX74. Low-Voltage CMOS Dual D-Type Flip-Flop. With 5 V Tolerant Inputs

Transcription

1 Low-oltage CMOS Dual D-Type Flip-Flop With 5 Tolerant Inputs The MC74LCX74 is a high performance, dual D type flip flop with asynchronous clear and set inputs and complementary (O, O) outputs. It operates from a 2.3 to 3.6 supply. High impedance TTL compatible inputs significantly reduce current loading to input drivers while TTL compatible outputs offer improved switching noise performance. A I specification of 5.5 allows MC74LCX74 inputs to be safely driven from 5. devices. The MC74LCX74 consists of 2 edge triggered flip flops with individual D type inputs. The flip flop will store the state of individual D inputs, that meet the setup and hold time requirements, on the LOW to HIGH Clock (CP) transition. Features Designed for 2.3 to 3.6 CC Operation 5. Tolerant Inputs Interface Capability With 5. TTL Logic LTTL Compatible LCMOS Compatible 24 ma Balanced Output Sink and Source Capability Near Zero Static Supply Current in All Three Logic States (0 A) Substantially Reduces System Power Requirements Latchup Performance Exceeds 500 ma ESD Performance: Human Body Model >200 Machine Model >20 These Devices are Pb Free, Halogen Free/BFR Free and are RoHS Compliant SOIC 4 D SUFFIX CASE 75A TSSOP 4 DT SUFFIX CASE 948G MARKING DIAGRAMS LCX74G AWLYWW LCX 74 ALYW ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 3 of this data sheet. 4 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week G or = Pb Free Package (Note: Microdot may be in either location) Semiconductor Components Industries, LLC, 202 October, 202 Rev. 8 Publication Order Number: MC74LCX74/D

2 SD 4 D 2 D SD Q 5 O CC CD2 D2 CP2 SD2 O2 O CP 3 CP CD Q 6 O CD SD CD D CP SD O O GND Figure. Pinout: 4 Lead (Top iew) D2 2 D SD Q 9 O2 CP2 CP Q 8 O2 CD CD2 3 Figure 2. Logic Diagram PIN NAMES Pins CP, CP2 D D2 CD, CD2 SD, SD2 On On Function Clock Pulse Inputs Data Inputs Direct Clear Inputs Direct Set Inputs Outputs TRUTH TABLE Inputs Outputs SDn CDn CPn Dn On On Operating Mode L H X X H L Asynchronous Set H L X X L H Asynchronous Clear L L X X H H Undetermined H H h H L H H l L H Load and Read Register H H X NC NC Hold H = High oltage Level h = High oltage Level One Setup Time Prior to the Low to High Clock Transition L = Low oltage Level l = Low oltage Level One Setup Time Prior to the Low to High Clock Transition NC = No Change X = High or Low oltage Level and Transitions are Acceptable = Low to High Transition = Not a Low to High Transition For I CC reasons, DO NOT FLOAT Inputs 2

3 MAXIMUM RATINGS Symbol Parameter alue Condition Units CC DC Supply oltage 0.5 to +7. I DC Input oltage 0.5 I +7. O DC Output oltage 0.5 O CC Output in HIGH or LOW State (Note ) I IK DC Input Diode Current 5 I < GND ma I OK DC Output Diode Current 5 O < GND ma +5 O > CC ma I O DC Output Source/Sink Current 50 ma I CC DC Supply Current Per Supply Pin 00 ma I GND DC Ground Current Per Ground Pin 00 ma T STG Storage Temperature Range 65 to +50 C MSL Moisture Sensitivity Level Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.. I O absolute maximum rating must be observed. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Type Max Units CC Supply oltage Operating Data Retention Only , , 3.3 I Input oltage O Output oltage (HIGH or LOW State) CC I OH I OL HIGH Level Output Current CC = CC = CC = LOW Level Output Current CC = CC = CC = T A Operating Free Air Temperature C t/ Input Transition Rise or Fall Rate, IN from 0.8 to 2., CC = ns/ ma ma ORDERING INFORMATION MC74LCX74DG MC74LCX74DR2G MC74LCX74DTG MC74LCX74DTR2G Device Package Shipping SOIC 4 (Pb Free) SOIC 4 (Pb Free) TSSOP 4 (Pb Free) TSSOP 4 (Pb Free) 55 Units / Rail 2500 Tape & Reel 96 Units / Rail 2500 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. 3

4 DC ELECTRICAL CHARACTERISTICS T A = 40 C to +85 C Symbol Characteristic Condition Min Max Units IH HIGH Level Input oltage (Note 2) 2.3 CC CC IL LOW Level Input oltage (Note 2) 2.3 CC CC OH HIGH Level Output oltage 2.3 CC 3.6 ; I OH = 00 A CC 0.2 CC = 2.3 ; I OH = 8 ma.8 CC = 2.7 ; I OH = 2 ma 2.2 CC = 3.; I OH = 8 ma 2.4 CC = 3.; I OH = 24 ma 2.2 OL LOW Level Output oltage 2.3 CC 3.6 ; I OL = 00 A 0.2 CC = 2.3 ; I OL = 8 ma 0.6 CC = 2.7 ; I OL = 2 ma 0.4 CC = 3.; I OL = 6 ma 0.4 CC = 3.; I OL = 24 ma 0.55 I OFF Power Off Leakage Current CC = 0, IN = 5.5 or OUT = A I IN Input Leakage Current CC = 3.6, IN = 5.5 or GND 5 A I CC Quiescent Supply Current CC = 3.6, IN = 5.5 or GND 0 A I CC Increase in I CC per Input 2.3 CC 3.6 ; IH = CC A 2. These values of I are used to test DC electrical characteristics only. AC CHARACTERISTICS (t R = t F = 2.5 ns; R L = 500 ) Limits T A = 40 C to +85 C CC = CC = 2.7 CC = C L = 50 pf C L = 50 pf C L = 30 pf Symbol Parameter Waveform Min Max Min Max Min Max Units f max Clock Pulse Frequency MHz t PLH t PHL Propagation Delay CPn to On or On ns t PLH t PHL Propagation Delay SDn or CDn to On or On ns t s Setup Time, HIGH or LOW Dn to CPn ns t h Hold Time, HIGH or LOW Dn to CPn 2.0 ns CPn Pulse Width, HIGH or LOW SDn or CDn Pulse Width, LOW ns t rec Recovery Time SDn or CDn to CPn ns t OSHL Output to Output Skew (Note 3).0 t OSLH.0 ns 3. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate outputs of the same device. The specification applies to any outputs switching in the same direction, either HIGH to LOW (t OSHL ) or LOW to HIGH (t OSLH ); parameter guaranteed by design. 4

5 DYNAMIC SWITCHING CHARACTERISTICS T A = +25 C Symbol Characteristic Condition Min Typ Max Units OLP OL Dynamic LOW Peak oltage (Note 4) Dynamic LOW alley oltage (Note 4) CC = 3.3, C L = 50 pf, IH = 3.3, IL = CC = 2.5, C L = 30 pf, IH = 2.5, IL = CC = 3.3, C L = 50 pf, IH = 3.3, IL = CC = 2.5, C L = 30 pf, IH = 2.5, IL = 4. Number of outputs defined as n. Measured with n outputs switching from HIGH to LOW or LOW to HIGH. The remaining output is measured in the LOW state. CAPACITIE CHARACTERISTICS Symbol Parameter Condition Typical Units C IN Input Capacitance CC = 3.3, I = or CC 7 pf C OUT Output Capacitance CC = 3.3, I = or CC 8 pf C PD Power Dissipation Capacitance 0 MHz, CC = 3.3, I = or CC 25 pf Dn CPn t s t h On, On t PLH, t PHL f max OH OL WAEFORM PROPAGATION DELAYS, SETUP AND HOLD TIMES t R = t F = 2.5 ns, 0% to 90%; f = MHz; t W = 500 ns SDn CDn t PLH t PHL On OL On t PHL t PLH OH WAEFORM 2 PROPAGATION DELAYS t R = t F = 2.5 ns, 0% to 90%; f = MHz; t W = 500 ns Figure 3. AC Waveforms 5

6 SDn, CDn t rec CPn WAEFORM 3 RECOERY TIME t R = t F = 2.5 ns from 0% to 90%; f = MHz; = 500 ns CPn SDn, CDn, CPn WAEFORM 4 PULSE WIDTH t R = t F = 2.5 ns (or fast as required) from 0% to 90%; Output requirements: OL 0.8, OH 2. Symbol /2 /2 Figure 3. AC Waveforms (Continued) CC PULSE GENERATOR DUT R T C L R L C L = 50 pf at CC = or equivalent (includes jig and probe capacitance) C L = 30 pf at CC = or equivalent (includes jig and probe capacitance) R L = R = 500 or equivalent R T = Z OUT of pulse generator (typically 50 ) Figure 4. Test Circuit 6

7 PACKAGE DIMENSIONS 0.5 (0.006) T 0.5 (0.006) T L 0.0 (0.004) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D C 4 G 4X K REF A 0.0 (0.004) M T U S S 8 7 B U H N TSSOP 4 CASE 948G ISSUE B N J J F DETAIL E DETAIL E 0.25 (0.00) K K M ÇÇÇ ÉÉÉ SECTION N N W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y4.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M SOLDERING FOOTPRINT* PITCH 4X X.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 7

8 PACKAGE DIMENSIONS H M B M e D 7 3X b A B E 0.25 M C A S B S A A C SEATING PLANE SOIC 4 NB CASE 75A 03 ISSUE K DETAIL A h X 45 M L A3 DETAIL A NOTES:. DIMENSIONING AND TOLERANCING PER ASME Y4.5M, CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE PROTRUSION SHALL BE 0.3 TOTAL IN EXCESS OF AT MAXIMUM MATERIAL CONDITION. 4. DIMENSIONS D AND E DO NOT INCLUDE MOLD PROTRUSIONS. 5. MAXIMUM MOLD PROTRUSION 0.5 PER SIDE. MILLIMETERS INCHES DIM MIN MAX MIN MAX A A A b D E e.27 BSC BSC H h L M SOLDERING FOOTPRINT* X.8.27 PITCH 4X 0.58 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC s product/patent coverage may be accessed aww.onsemi.com/site/pdf/patent Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative MC74LCX74/D