74HC245. Octal 3 State Noninverting Bus Transceiver. High Performance Silicon Gate CMOS

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1 Octal 3 State Noninverting Bus Traceiver High Performance Silicon Gate CMOS The 74HC245 is identical in pinout to the LS245. The device inputs are compatible with standard CMOS outputs; with pull up resistors, they are compatible with LSTTL outputs. The HC245 is a 3 state noninverting traceiver that is used for 2 way asynchronous communication between data buses. The device has an active low Output Enable pin, which is used to place the I/O ports into high impedance states. The Direction control determines whether data flows from A to B or from B to A. Features Output Drive Capability: LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating oltage Range: to Low Input Current:.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A ESD Performance: HBM 2000 ; Machine Model 200 Chip Complexity: 308 FETs or 77 Equivalent Gates This is a Pb Free Device 20 TSSOP 20 DT SUFFIX CASE 948E 20 MARKING DIAGRAMS HC 245 ALYW HC245 = Device Code A = Assembly Location L = Wafer Lot Y = Year W = Work Week = Pb Free Package (Note: Microdot may be in either location) ORDERING INFORMATION See detailed ordering and shipping information in the package dimeio section on page 2 of this data sheet. Semiconductor Components Industries, LLC, 2007 March, 2007 Rev. Publication Order Number: 74HC245/D

2 DIRECTION A 2 A2 3 A3 4 A4 5 A5 6 A CC OUTPUT ENABLE B B2 B3 B4 B5 A DATA PORT A A2 A3 A4 A5 A6 A7 A B 7 B2 6 B3 B4 4 B5 3 B6 2 B7 B8 B DATA PORT A7 A8 GND B6 B7 B8 DIRECTION OUTPUT ENABLE PIN 0 = GND PIN 20 = CC Figure. Pin Assignment Figure 2. Logic Diagram Control Inputs FUNCTION TABLE Output Enable Direction Operation L L Data Tramitted from Bus B to Bus A L H Data Tramitted from Bus A to Bus B H X Buses Isolated (High Impedance State) X = don t care ORDERING INFORMATION Device Package Shipping 74HC245DTR2G TSSOP 20* 2500 / Tape & Reel For information on tape and reel specificatio, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specificatio Brochure, BRD80/D. *This package is inherently Pb Free. 2

3 MAXIMUM RATINGS (Note ) Symbol Parameter alue Unit CC DC Supply oltage 0.5 to 7.0 IN DC Input oltage 0.5 to CC 0.5 OUT DC Output oltage (Note 2) 0.5 to CC 0.5 I IK DC Input Diode Current 20 ma I OK DC Output Diode Current 35 ma I OUT DC Output Sink Current 35 ma I CC DC Supply Current per Supply Pin 75 ma I GND DC Ground Current per Ground Pin 75 ma T STG Storage Temperature Range 65 to 0 C T L Lead Temperature, mm from Case for 0 Seconds 260 C T J Junction Temperature Under Bias 0 C JA Thermal Resistance TSSOP 28 C/W P D Power Dissipation in Still Air at 85 C TSSOP 450 mw MSL Moisture Seitivity Level F R Flammability Rating Oxygen Index: 30% to 35% UL in ESD ESD Withstand oltage Human Body Model (Note 3) Machine Model (Note 4) I LATCHUP Latchup Performance Above CC and Below GND at 85 C (Note 5) 300 ma Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditio is not implied. Extended exposure to stresses above the Recommended Operating Conditio may affect device reliability.. Measured with minimum pad spacing on an FR4 board, using 0 mm by inch, 20 ounce copper trace with no air flow. 2. I O absolute maximum rating must observed. 3. Tested to EIA/JESD22 A4 A. 4. Tested to EIA/JESD22 A A. 5. Tested to EIA/JESD78. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit CC DC Supply oltage (Referenced to GND) in, out DC Input oltage, Output oltage (Referenced to GND) 0 CC T A Operating Temperature, All Package Types C t r, t f Input Rise and Fall Time CC = (Figure 3) CC = CC =

4 DC ELECTRICAL CHARACTERISTICS (oltages Referenced to GND) Symbol Parameter Test Conditio IH Minimum High Level Input oltage out = CC I out 20 A IL Maximum Low Level Input oltage out = I out 20 A OH OL Minimum High Level Output oltage Maximum Low Level Output oltage in = IH I out 20 A in = IH I out 2.4 ma I out ma I out 7.8 ma in = IL I out 20 A in = IL I out 2.4 ma I out ma I out 7.8 ma CC Guaranteed Limit 55 to 25 C 85 C 25 C Unit I in Maximum Input Leakage Current in = CC or GND ± ±.0 ±.0 A I OZ Maximum Three State Leakage Current Output in High Impedance State in = IL or IH out = CC or GND ±0.5 ±5.0 ±0 A I CC Maximum Quiescent Supply Current (per Package) in = CC or GND I out = 0 A A 6. Information on typical parametric values and high frequency or heavy load coideratio can be found in the ON Semiconductor High Speed CMOS Data Book (DL29/D). AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, Input t r = t f = 6 ) Symbol t PLH, t PHL t PLZ, t PHZ t PZL, t PZH t TLH, t THL Parameter Maximum Propagation Delay, A to B, B to A (Figures and 3) Maximum Propagation Delay, Direction or Output Enable to A or B (Figures 2 and 4) Maximum Propagation Delay, Output Enable to A or B (Figures 2 and 4) Maximum Output Traition Time, Any Output (Figures and 3) CC Guaranteed Limit 55 to 25 C 85 C 25 C C in Maximum Input Capacitance (Pin or Pin ) pf C out Maximum Three State I/O Capacitance pf (I/O in High Impedance State) 7. For propagation delays with loads other than 50 pf, and information on typical parametric values, see the ON Semiconductor High Speed CMOS Data Book (DL29/D) C, CC = 5.0 C PD Power Dissipation Capacitance (Per Traceiver Channel) (Note 8) 40 pf 8. Used to determine the no load dynamic power coumption: P D = C PD 2 CC f + I CC CC. For load coideratio, see the ON Semiconductor High Speed CMOS Data Book (DL29/D). Unit 4

5 INPUT A OR B OUTPUT B OR A t r t PLH t TLH 0% 90% 0% 90% t f CC GND t PHL t THL DIRECTION OUTPUT ENABLE A OR B A OR B t PZL t PZH t PLZ t PHZ 0% 90% CC GND CC GND HIGH IMPEDANCE OL OH HIGH IMPEDANCE Figure 3. Switching Waveform Figure 4. Switching Waveform TEST POINT TEST POINT DEICE UNDER TEST OUTPUT C L * DEICE UNDER TEST OUTPUT k C L * CONNECT TO CC WHEN TESTING t PLZ AND t PZL. CONNECT TO GND WHEN TESTING t PHZ AND t PZH. *Includes all probe and jig capacitance *Includes all probe and jig capacitance Figure 5. Test Circuit Figure 6. Test Circuit 5

6 A 2 8 B A2 3 7 B2 A3 4 6 B3 A4 5 A DATA PORT A5 6 B4 B DATA PORT 4 B5 A6 7 3 B6 A7 8 2 B7 A8 9 B8 DIRECTION OUTPUT ENABLE Figure 7. Expanded Logic Diagram 6

7 PACKAGE DIMENSIONS TSSOP 20 CASE 948E 02 ISSUE C 5 (0.006) T L 5 (0.006) T U 2X L/2 PIN IDENT U S S C (0.004) T SEATING PLANE 20X K REF 0 (0.004) M T U S S 0 A D G H B U J J K K ÍÍÍÍ ÍÍÍÍ SECTION N N N 0.25 (0.00) M N F DETAIL E DETAIL E W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI YM, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M SOLDERING FOOTPRINT* PITCH 6X X.26 DIMENSIONS: MILLIMETERS *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. 7

8 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, coequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specificatio can and do vary in different applicatio and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any licee under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applicatio intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless agait all claims, costs, damages, and expees, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 563, Denver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@oemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative 74HC245/D