MC74HC132A. Quad 2 Input NAND Gate with Schmitt Trigger Inputs. High Performance Silicon Gate CMOS

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1 Quad 2 Input NAND Gate with Schmitt Trigger Inputs High Performance Silicon Gate CMOS The is identical in pinout to the LS32. The device inputs are compatible with standard CMOS outputs; with pull up resistors, they are compatible with LSTTL outputs. The HC32A can be used to enhance noise immunity or to square up slowly changing waveforms. Features Output Drive Capability: 0 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2.0 to 6.0 V Low Input Current:.0 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements as Defined by JEDEC Standard No. 7A Chip Complexity: 72 FETs or 8 Equivalent Gates Pb Free Packages are Available* PDIP N SUFFIX CASE 646 SOIC D SUFFIX CASE 75A TSSOP DT SUFFIX CASE 948G MARKING DIAGRAMS N AWLYYWW HC32A AWLYWW HC 32A ALYW A B Y A2 B B4 A4 Y4 B3 A = Assembly Location L, WL = Wafer Lot Y, YY = Year W, WW = Work Week Y2 6 9 A3 GND 7 8 Y3 FUNCTION TABLE Figure. Pin Assignment Inputs Output A B Y L L H L H H H L H H H L ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 2 of this data sheet. *For additional information on our Pb Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. Semiconductor Components Industries, LLC, 2005 January, 2005 Rev. 0 Publication Order Number: /D

2 A B A Y B2 A3 B3 A Y2 Y = AB 8 Y3 B4 3 Y4 PIN = PIN 7 = GND Figure 2. Logic Diagram ORDERING INFORMATION Device Order Number Package Shipping N PDIP 2000 Units / Box NG PDIP (Pb Free) 2000 Units / Box D SOIC 55 Units / Rail DG SOIC (Pb Free) 55 Units / Rail DR2 SOIC 2500 Tape & Reel DR2G SOIC (Pb Free) 2500 Tape & Reel DT TSSOP * 96 Units / Rail DTR2 TSSOP * 2500 Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D. *This package is inherently Pb Free. 2

3 MAXIMUM RATINGS Symbol Parameter Value Unit Positive DC Supply Voltage 0.5 to 7.0 V V IN Digital Input Voltage 0.5 to 7.0 V V OUT DC Output Voltage Output in 3 State High or Low State 0.5 to to 0.5 I IK Input Diode Current 20 ma I OK Output Diode Current 20 ma I OUT DC Output Current, per Pin 25 ma I CC DC Supply Current, and GND Pins 75 ma I GND DC Ground Current per Ground Pin 75 ma T STG Storage Temperature Range 65 to 50 C T L Lead Temperature, mm from Case for 0 Seconds 260 C T J Junction Temperature Under Bias 50 C V JA Thermal Resistance PDIP SOIC TSSOP P D Power Dissipation in Still Air at 85 C PDIP SOIC TSSOP C/W mw MSL Moisture Sensitivity Level F R Flammability Rating Oxygen Index: 30% 35% UL in V ESD ESD Withstand Voltage Human Body Model (Note ) Machine Model (Note 2) Charged Device Model (Note 3) I Latch Up Latch Up Performance Above and Below GND at 85 C (Note 4) 300 ma Maximum ratings are those values beyond which device damage can occur. Maximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.. Tested to EIA/JESD22 A A. 2. Tested to EIA/JESD22 A5 A. 3. Tested to JESD22 C0 A. 4. Tested to EIA/JESD For high frequency or heavy load considerations, see Chapter 2the ON Semiconductor High Speed CMOS Data Book (DL29/D). V RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit Î DC Supply Voltage (Referenced to GND) V DC Input Voltage, Output Voltage (Referenced to GND) 0 V Î Operating Temperature, All Package Types C Î Input Rise and Fall Time (Figure 3) No Limit ns (Note 6) Î Î V IN, V OUTÎ Î T A Î t r, t f 6. When V IN 0.5, I CC >> quiescent current. 7. Unused inputs may not be left open. All inputs must be tied to a high logic voltage level or a low logic input voltage level. 3

4 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Guaranteed Limit Symbol Parameter Test Conditions V 55 C to 25 C 85 C 25 C Unit V T+ max Maximum Positive Going ÎÎ V OUT = 0. V Input Threshold Voltage I OUT 20 A ÎÎ V (Figure 5) V T+ min ÎÎ Minimum Positive Going V OUT ÎÎ = 0. V Input Threshold Voltage ÎÎ I OUT 20 A Î ÎÎ V (Figure 5) V T max Maximum Negative Going V Input Threshold Voltage ÎÎ OUT = 0. V V I OUT 20 A 4.5 Î ÎÎ (Figure 5) Î V T min Minimum Negative Going V ÎÎ OUT = 0. V V Input Threshold Voltage I OUT ÎÎ 20 A (Figure 5) 6.0 Î ÎÎ V H max Maximum Hysteresis ÎÎ V OUT = 0. V or 0. V 2.0 Î ÎÎ V (Note 8) Voltage I (Figure 5) ÎÎ OUT 20 A Î ÎÎ V H min Minimum Hysteresis ÎÎ V OUT = 0. V or 0. V (Note 8) Voltage I (Figure 5) ÎÎ OUT 20 A ÎÎ Î ÎÎ V V OH Î Minimum High Level V IN V T min or V T+ ÎÎ max Output Voltage ÎÎ I OUT 20 A Î ÎÎ V ÎÎ ÎÎ ÎÎ V IN V T min or V T+ max I OUT 4.0 ma 4.5 Î ÎÎ V I OUT 5.2 ma Î V OL Maximum Low Level V Output Voltage ÎÎ IN V T+ max V I OUT 20 A 4.5 Î ÎÎ ÎÎ 6.0 Î ÎÎ V IN V T+ max I OUT 4.0 ma 4.5 Î ÎÎ V I OUT 5.2 ma ÎÎ I IN Maximum Input Leakage V Current ÎÎ IN = or GND Î ÎÎ ÎÎ A I CC Maximum Quiescent ÎÎ V IN = or GND Supply Current I OUT = 0 A ÎÎ A (per Package) 8. V H min (V T+ min) (V T max); V H max = (V T+ max) (V T min). 9. Information on typical parametric values can be found in the ON Semiconductor High Speed CMOS Data Book (DL29/D). 4

5 AC ELECTRICAL CHARACTERISTICS (C L = 50 pf, Input t r = t f = 6.0 ns) Guaranteed Limit Symbol Parameter V 55 C to 25 C 85 C 25 C Unit t PLH, Î Maximum Propagation Delay, Input A or B to Output Y t (Figures 3 and 4) PHL ÎÎ ns t TLH ÎÎ, Maximum Output Transition Time, Any Output t THL Î (Figures 3 and 4) Î ÎÎ ns Î ÎÎ Maximum Input Capacitance pf C in 0.For propagation delays with loads other than 50 pf, and information on typical parametric values, see the ON Semiconductor High Speed CMOS Data Book (DL29/D). 25 C, = 5.0 V C PD Power Dissipation Capacitance (per Gate) (Note ) 24 pf. Used to determine the no load dynamic power consumption: P D = C PD 2 f + I CC. For load considerations, see the ON Semiconductor High Speed CMOS Data Book (DL29/D). TEST POINT t r t f INPUT A OR B Y 90% 50% 0% t PHL 90% 50% 0% t PLH GND DEVICE UNDER TEST OUTPUT C L * t THL t TLH *Includes all probe and jig capacitance Figure 3. Switching Waveforms Figure 4. Test Circuit 5

6 V T, TYPICAL INPUT THRESHOLD VOLTAGE (VOLTS) , POWER SUPPLY VOLTAGE (VOLTS) V H typ = (V T + typ) (V T typ) V H typ Figure 5. Typical Input Threshold, V T+, V T Versus Power Supply Voltage V H V H V IN V T + V T V IN V T + V T GND GND V OH V OH V OUT V OUT V OL V OL (a) A SCHMITT TRIGGER SQUARES UP INPUTS (a) WITH SLOW RISE AND FALL TIMES V IN V OUT (b) A SCHMITT TRIGGER OFFERS MAXIMUM NOISE IMMUNITY Figure 6. Typical Schmitt Trigger Applications 6

7 PACKAGE DIMENSIONS PDIP N SUFFIX CASE ISSUE M 8 7 B NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 4. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 5. ROUNDED CORNERS OPTIONAL. T SEATING PLANE N A F C K H G D PL 0.3 (0.005) M INCHES MILLIMETERS DIM MIN MAX MIN MAX L A B C D F G 0.00 BSC 2.54 BSC H J J K L M M 0 0 N SOIC D SUFFIX CASE 75A 03 ISSUE G T SEATING PLANE G A 8 D PL 7 B K P 7 PL C 0.25 (0.00) M T B S A S 0.25 (0.00) M B M R X 45 M J F NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.5 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G.27 BSC BSC J K M P R

8 TSSOP DT SUFFIX CASE 948G 0 ISSUE O 0.5 (0.006) T 0.5 (0.006) T L 0.0 (0.004) T SEATING PLANE U U S 2X L/2 PIN IDENT. S D C X K REF 0.0 (0.004) M T U S V S N (0.00) M B U 7 A V G H N J J F DETAIL E K K ÇÇÇ ÉÉ ÇÇÇ SECTION N N DETAIL E W NOTES:. DIMENSIONING AND TOLERANCING PER ANSI Y.5M, CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.5 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.00) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE W. MILLIMETERS INCHES DIM MIN MAX MIN MAX A B C D F G 0.65 BSC BSC H J J K K L 6.40 BSC BSC M ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 632, Phoenix, Arizona USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2 9 Kamimeguro, Meguro ku, Tokyo, Japan Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. /D