MC14070B, MC14077B CMOS SSI. Quad Exclusive OR and NOR Gates
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- Maude Fowler
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1 C070B, C077B COS SSI Quad Exclusive OR and NOR Gates The C070B quad exclusive OR gate and the C077B quad exclusive NOR gate are constructed with OS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. These complementary OS logic gates find primary use where low power dissipation and/or high noise immunity is desired. Features Supply Voltage Range =.0 to 8 All Outputs Buffered Capable of Driving Two LowPower TTL Loads or One LowPower Schottky TTL Load Over the Rated Temperature Range Double Diode Protection on All Inputs C070B Replacement for CD00B and CD070B Types C077B Replacement for CD077B Type PbFree Packages are Available* AXIU RATINGS oltages Referenced to ) Symbol Parameter Value Unit DC Supply Voltage Range 0. to +8.0 V V in, V out Input or Output Voltage Range (DC or Transient) 0. to + 0. V I in, I out P D Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note ) ±0 ma 00 mw T A Ambient Temperature Range to + C T stg Storage Temperature Range to +0 C T L Lead Temperature (8Second Soldering) 0 C aximum ratings are those values beyond which device damage can occur. aximum ratings applied to the device are individual stress limit values (not normal operating conditions) and are not valid simultaneously. If these limits are exceeded, device functional operation is not implied, damage may occur and reliability may be affected.. Temperature Derating: Plastic P and D/DW Packages: 7.0 mw/ C From C To C xx A WL, L YY, Y WW, W PDIP P SUFFIX CASE SOIC D SUFFIX CASE 7A SOEIAJ F SUFFIX CASE 9 ARKING DIAGRAS C0xxBCP AWLYYWW 0xxB AWLYWW C0xxB AWLYWW = Specific Device Code = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORATION See detailed ordering and shipping information in the package dimensions section on page of this data sheet. This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, V in and V out should be constrained to the range in or V out ). Unused inputs must always be tied to an appropriate logic voltage level (e.g., either or ). Unused outputs must be left open. *For additional information on our PbFree strategy and soldering details, please download the ON Semiconductor Soldering and ounting Techniques Reference anual, SOLDERR/D. Semiconductor Components Industries, LLC, 00 February, 00 Rev. Publication Order Number: C070B/D
2 C070B, C077B PIN ASSIGNENT IN A IN A IN D OUT A IN D OUT B OUT D IN B 0 OUT C IN B 9 IN C 7 8 IN C C070B QUAD Exclusive OR Gate C077B QUAD Exclusive NOR Gate = PIN = PIN 7 (BOTH DEVICES) 0 ns 0 ns 90% 0% 0% V in I DD * V in /f 0% DUTY CYCLE C L *Inverted output on C077B only. Figure. Power Dissipation Test Circuit and Waveform 0 ns 0 ns PULSE GENERATOR # * C L INPUT t PHL OUTPUT 90% 0% 0% t THL *Inverted output on C077B only. #Connect unused input to for C070B, to for C077B. 90% 0% 0% t PLH V OH V OL t TLH Figure. Switching Time Test Circuit and Waveforms
3 C070B, C077B ORDERING INFORATION Device Package Shipping C070BCP PDIP 00 Units / Rail C070BCPG PDIP (PbFree) 00 Units / Rail C070BD SOIC Units / Rail C070BDG SOIC (PbFree) Units / Rail C070BDR SOIC 00 Units / Tape & Reel C070BDRG SOIC (PbFree) 00 Units / Tape & Reel C070BFEL SOEIAJ 000 Units / Tape & Reel C077BCP PDIP 00 Units / Rail C077BCPG PDIP (PbFree) 00 Units / Rail C077BD SOIC Units / Rail C077BDR SOIC 00 Units / Tape & Reel C077BDRG SOIC (PbFree) 00 Units / Tape & Reel C077BFEL SOEIAJ 000 Units / Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD80/D.
4 C070B, C077B ELECTRICAL CHARACTERISTICS oltages Referenced to ) C ÎÎ C ÎÎ C Characteristic Î Symbol ÎÎ Î Î in ax in Î Typ ax in ax Unit (Note ) ÎÎ Output Voltage 0 Level V V in = Î OL or Î Î 0.0 Î Level Î V OH ÎÎ.0 Î.9.9 Î.0.9 V in = 0 or Î Input Voltage 0 Level V IL O =. or 0. ) ÎÎ.0 Î. Î... O = 9.0 or.0 ) O =. or. ) ÎÎ Î.0 Î Level V IH O = 0. or. ) ÎÎ.0 Î.. Î.7. O =.0 or 9.0 ) O =. or. ) ÎÎ Î Î 8. Output Drive Current Î I OH madc OH =. ) SourceÎÎ.0 Î.0.Î..7 OH =. ) OH = 9. ) ÎÎ 0Î..Î. 0.9 OH =. ) ÎÎ Î..Î 8.8. OL = 0. ) SinkÎ I OL ÎÎ.0 Î Î madc OL = 0. ) OL =. ) ÎÎ Î.. Î 8.8. Input Current Î I in ÎÎ Î ± 0. Î ± ± 0. ±.0 Adc Input Capacitance Î C in ÎÎ in = 0) ÎÎ ÎÎ.0 7. ÎÎ pf Quiescent Current Î I DD ÎÎ.0 Î 0. Î Adc (Per Package) Î Î.0 Î Total Supply Current (Notes & ) Î I T ÎÎ.0 I T = (0. A/kHz) f + I DD Adc (Dynamic plus Quiescent, ÎÎ 0 I T = (0. A/kHz) f + I DD Per Package) I (C L = 0 pf on all outputs, all Î T = (0.9 A/kHz) f + I DD buffers switching) Output Rise and Fall Times (Note ) (C L Î t TLH, = 0 pf) t THL ns t TLH, t THL = (. ns/pf) C L + ns ÎÎ t TLH, t THL = (0.0 ns/pf) C L + 0 ns t TLH, t THL = (0.0 ns/pf) C L ÎÎ ÎÎ + 0 ns 0 80 Propagation Delay Times (Note ) t PLH, ns (C L = 0 pf) Î t PHL t PLH, t PHL = (0.90 ns/pf) C L + 0 ns t PLH, t PHL = (0. ns/pf) C L Î + 7 ns t PLH, t PHL = (0. ns/pf) C L + 7 ns ÎÎ Î Î 0. Data labelled Typ is not to be used for design purposes but is intended as an indication of the IC s potential performance.. The formulas given are for the typical characteristics only at C.. To calculate total supply current at loads other than 0 pf: I T (C L ) = I T (0 pf) + (C L 0) Vfk where: I T is in H (per package), C L in pf, V = ( ) in volts, f in khz is input frequency, and k = 0.00.
5 C070B, C077B PACKAGE DIENSIONS PDIP P SUFFIX CASE 0 ISSUE N T N SEATING PLANE 8 B 7 A F C K H G D PL 0. (0.00) J L NOTES:. DIENSIONING AND TOLERANCING PER ANSI Y., 98.. CONTROLLING DIENSION: INCH.. DIENSION L TO CENTER OF LEADS WHEN FORED PARALLEL.. DIENSION B DOES NOT INCLUDE OLD FLASH.. ROUNDED CORNERS OPTIONAL. INCHES ILLIETERS DI IN AX IN AX A B C D F G 0.00 BSC. BSC H J K L N SOIC D SUFFIX CASE 7A0 ISSUE G T SEATING PLANE G A 8 D PL 7 B K P 7 PL C 0. (0.00) T B S A S 0. (0.00) B R X J F NOTES:. DIENSIONING AND TOLERANCING PER ANSI Y., 98.. CONTROLLING DIENSION: ILLIETER.. DIENSIONS A AND B DO NOT INCLUDE OLD PROTRUSION.. AXIU OLD PROTRUSION 0. (0.00) PER SIDE.. DIENSION D DOES NOT INCLUDE DABAR PROTRUSION. ALLOWABLE DABAR PROTRUSION SHALL BE 0.7 (0.00) TOTAL IN EXCESS OF THE D DIENSION AT AXIU ATERIAL CONDITION. ILLIETERS INCHES DI IN AX IN AX A B C D F G.7 BSC 0.00 BSC J K P R
6 C070B, C077B PACKAGE DIENSIONS SOEIAJ F SUFFIX CASE 90 ISSUE O e 8 Z D 7 E A H E VIEW P L E Q L DETAIL P NOTES: DIENSIONING AND TOLERANCING PER ANSI Y., 98. CONTROLLING DIENSION: ILLIETER. DIENSIONS D AND E DO NOT INCLUDE OLD FLASH OR PROTRUSIONS AND ARE EASURED AT THE PARTING LINE. OLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0. (0.00) PER SIDE. TERINAL NUBERS ARE SHOWN FOR REFERENCE ONLY. THE LEAD WIDTH DIENSION (b) DOES NOT INCLUDE DABAR PROTRUSION. ALLOWABLE DABAR PROTRUSION SHALL BE 0.08 (0.00) TOTAL IN EXCESS OF THE LEAD WIDTH DIENSION AT AXIU ATERIAL CONDITION. DABAR CANNOT BE LOCATED ON THE LOWER RADIUS OR THE FOOT. INIU SPACE BETWEEN PROTRUSIONS AND ADJACENT LEAD TO BE 0. ( 0.08). ILLIETERS INCHES A b A A DI IN AX IN AX 0. (0.00) 0.0 (0.00) b c D E e.7 BSC 0.00 BSC H E L E Q Z. 0.0 c ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORATION LITERATURE FULFILLENT: Literature Distribution Center for ON Semiconductor P.O. Box, Phoenix, Arizona 808 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 9 Kamimeguro, eguroku, Tokyo, Japan 00 Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative. C070B/D
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