SN74LS175MEL. Quad D Flip Flop LOW POWER SCHOTTKY

Transcription

1 uad Flip Flop The LSTTL/MSI SN74LS75 is a high speed uad Flip-Flop. The device is useful for general flip-flop requirements where clock and clear inputs are common. The information on the inputs is stored during the LOW to HIGH clock transition. Both true and complemented outputs of each flip-flop are provided. A Master Reset input resets all flip-flops, independent of the Clock or inputs, when LOW. The LS75 is fabricated with the Schottky barrier diode process for high speed and is completely compatible with all ON Semiconductor TTL families. Edge-Triggered -Type Inputs Buffered-Positive Edge-Triggered Clock Clock to Output elays of 30 ns Asynchronous Common Reset True and Complement Output Input Clamp iodes Limit High Speed Termination Effects GUARANTEE OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage V T A Operating Ambient Temperature Range C I OH Output Current High 0.4 ma I OL Output Current Low 8.0 ma 6 LOW POWER SCHOTTKY 6 PLASTIC N SUFFIX CASE 648 SOIC SUFFIX CASE 75B 6 SOEIAJ M SUFFIX CASE 966 ORERING INFORMATION evice Package Shipping SN74LS75N 6 Pin IP 2000 Units/Box SN74LS75 SOIC 6 38 Units/Rail SN74LS75R2 SOIC /Tape & Reel SN74LS75M SOEIAJ 6 See Note SN74LS75MEL SOEIAJ 6 See Note. For ordering information on the EIAJ version of the SOIC package, please contact your local ON Semiconductor representative. Semiconductor Components Industries, LLC, 2006 July, 2006 Rev. 8 Publication Order Number: SN74LS75/

2 CONNECTION IAGRAM IP (TOP VIEW) V CC NOTE: The Flatpak version has the same pinouts (Connection iagram) as the ual In-Line Package GN LOAING (Note a) PIN NAMES HIGH LOW ata Inputs Clock (Active HIGH Going Edge) Input Master Reset (Active LOW) Input True Outputs Complemented Outputs 0.5 U.L. 0.5 U.L. 0.5 U.L. 0 U.L. 0 U.L U.L U.L U.L. 5 U.L. 5 U.L. Мa) TTL Unit Load (U.L.) = 40 A HIGH/.6 ma LOW. LOGIC SYMBOL V CC = PIN 6 GN = PIN 8 LOGIC IAGRAM C C C C V CC = PIN 6 GN = PIN 8 = PIN NUMBERS 2

3 FUNCTIONAL ESCRIPTION The LS75 consists of four edge-triggered flip-flops with individual inputs and and outputs. The Clock and Master Reset are common. The four flip-flops will store the state of their individual inputs on the LOW to HIGH Clock () transition, causing individual and outputs to follow. A LOW input on the Master Reset () will force all outputs LOW and outputs HIGH independent of Clock or ata inputs. The LS75 is useful for general logic applications where a common Master Reset and Clock are acceptable. TRUTH TABLE Inputs (t = n, = H) Outputs (t = n+) Note L L H H H L Note : t = n + indicates conditions after next clock. C CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Min Typ Max V IH Input HIGH Voltage 2.0 V Unit Test Conditions Guaranteed Input HIGH Voltage for All Inputs V IL Input LOW Voltage 0.8 V Guaranteed Input LOW Voltage for All Inputs V IK Input Clamp iode Voltage V V CC = MIN, I IN = 8 ma V OH Output HIGH Voltage V V CC = MIN, I OH = MAX, V IN = V IH or V IL per Truth Table V OL I IH Output LOW Voltage Input HIGH Current V I OL = 4.0 ma V CC = V CC MIN, V IN = V IL or V IH V I OL = 8.0 ma per Truth Table 20 μa V CC = MAX, V IN = 2.7 V 0. ma V CC = MAX, V IN = 7.0 V I IL Input LOW Current 0.4 ma V CC = MAX, V IN = 0.4 V I OS Short Circuit Current (Note 2) ma V CC = MAX I CC Power Supply Current 8 ma V CC = MAX 2. Not more than one output should be shorted at a time, nor for more than second. 3

4 AC CHARACTERISTICS (T A = 25 C) Symbol Parameter Limits Min Typ Max Unit f MAX Maximum Input Clock Frequency MHz Propagation elay, to Output Propagation elay, Clock to Output ns ns Test Conditions V CC = 5.0 V C L = 5 pf AC SETUP REUIREMENTS (T A = 25 C) Limits Symbol Parameter Min Typ Max Unit t W Clock or Pulse Width 20 ns t s ata Setup Time 20 ns t h ata Hold Time 5.0 ns t rec Recovery Time 25 ns Test Conditions V CC = 5.0 V AC WAVEFORMS t s(h) t s(l) t h(h) t h(l) /f max t w t W t rec * *The shaded areas indicate when the input is permitted to *change for predictable output performance. Figure. Clock to Output elays, Clock Pulse Width, Frequency, Setup and Hold Times ata to Clock Figure 2. Master Reset to Output elay, Master Reset Pulse Width, and Master Reset Recovery Time EFINITIONS OF TERMS SETUP TIME (t s ) is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from LOW to HIGH in order to be recognized and transferred to the outputs. HOL TIME (t h ) is defined as the minimum time following the clock transition from LOW to HIGH that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOL TIME indicates that the correct logic level may be released prior to the clock transition from LOW to HIGH and still be recognized. RECOVERY TIME (t rec ) is defined as the minimum time required between the end of the reset pulse and the clock transition from LOW to HIGH in order to recognize and transfer HIGH ata to the outputs. 4

5 PACKAGE IMENSIONS N SUFFIX PLASTIC PACKAGE CASE ISSUE R 6 H A 8 G F 9 6 PL B S C K 0.25 (0.00) M T T SEATING PLANE A M J L M. IMENSIONING AN TOLERANCING PER ANSI Y4.5M, CONTROLLING IMENSION: INCH. 3. IMENSION L TO CENTER OF LEAS WHEN FORME PARALLEL. 4. IMENSION B OES NOT INCLUE MOL FLASH. 5. ROUNE CORNERS OPTIONAL. INCHES MILLIMETERS IM MIN MAX MIN MAX A B C F G 0.00 BSC 2.54 BSC H BSC.27 BSC J K L M S

6 PACKAGE IMENSIONS SUFFIX PLASTIC SOIC PACKAGE CASE 75B 05 ISSUE J T SEATING PLANE G A K B 6 PL 0.25 (0.00) M T B S A S P 8 PL 0.25 (0.00) M B S C M R X 45 J F. IMENSIONING AN TOLERANCING PER ANSI Y4.5M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSIONS A AN B O NOT INCLUE MOL PROTRUSION. 4. MAXIMUM MOL PROTRUSION 0.5 (0.006) PER SIE. 5. IMENSION OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.27 (0.005) TOTAL IN EXCESS OF THE IMENSION AT MAXIMUM MATERIAL CONITION. MILLIMETERS INCHES IM MIN MAX MIN MAX A B C F G.27 BSC BSC J K M P R

7 PACKAGE IMENSIONS M SUFFIX SOEIAJ PACKAGE CASE ISSUE O e 6 9 Z b A H E A 0.3 (0.005) M 0.0 (0.004) 8 E VIEW P M L E L ETAIL P c. IMENSIONING AN TOLERANCING PER ANSI Y4.5M, CONTROLLING IMENSION: MILLIMETER. 3. IMENSIONS AN E O NOT INCLUE MOL FLASH OR PROTRUSIONS AN ARE MEASURE AT THE PARTING LINE. MOL FLASH OR PROTRUSIONS SHALL NOT EXCEE 0.5 (0.006) PER SIE. 4. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 5. THE LEA WITH IMENSION (b) OES NOT INCLUE AMBAR PROTRUSION. ALLOWABLE AMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE LEA WITH IMENSION AT MAXIMUM MATERIAL CONITION. AMBAR CANNOT BE LOCATE ON THE LOWER RAIUS OR THE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AN AJACENT LEA TO BE 0.46 ( 0.08). MILLIMETERS INCHES IM MIN MAX MIN MAX A A b c E e.27 BSC BSC H E L L E M Z ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORERING INFORMATION LITERATURE FULFILLMENT: Literature istribution Center for ON Semiconductor P.O. Box 563, enver, Colorado 8027 USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order Literature: For additional information, please contact your local Sales Representative SN74LS75/