SN74LS166MEL. 8 Bit Shift Registers LOW POWER SCHOTTKY

Transcription

1 8 Bit Shift Registers The SN74S166 is an 8-Bit Shift Register. Designed with all inputs buffered, the drive requirements are lowered to one 74S standard load. By utilizing input clamping diodes, switching transients are minimized and system design simplified. The S166 is a parallel-in or serial-in, serial-out shift register and has a complexity of 77 equivalent gates with gated clock inputs and an overriding clear input. The shift/load input establishes the parallel-in or serial-in mode. When high, this input enables the serial data input and couples the eight flip-flops for serial shifting with each clock pulse. Synchronous loading occurs on the next clock pulse when this is low and the parallel data inputs are enabled. Serial data flow is inhibited during parallel loading. Clocking is done on the low-to-high level edge of the clock pulse via a two input positive NOR gate, which permits one input to be used as a clock enable or clock inhibit function. Clocking is inhibited when either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clock inhibit input should only be done when the clock input is high. A buffered direct clear input overrides all other inputs, including the clock, and sets all flip-flops to zero. Synchronous oad Direct Overriding Clear Parallel to Serial Conversion GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit V CC Supply Voltage V T A Operating Ambient Temperature Range C I O Output Current igh 0.4 ma I O Output Current ow 8.0 ma 16 OW POWER SCOTTKY PASTIC N SUFFIX CASE SOIC D SUFFIX CASE 751B 1 SOEIAJ M SUFFIX CASE 966 ORDERING INFORMATION Device Package Shipping SN74S166N 16 Pin DIP 2000 Units/Box SN74S166D SOIC Units/Rail SN74S166DR2 SOIC /Tape & Reel SN74S166M SOEIAJ 16 See Note 1 SN74S166ME SOEIAJ 16 See Note 1 1. For ordering information on the EIAJ version of the SOIC package, please contact your local ON Semiconductor representative. Semiconductor Components Industries, C, 2006 July, 2006 Rev. 8 1 Publication Order Number: SN74S166/D

2 V CC SIFT/ OAD PARAE PARAE INPUTS INPUT OUTPUT Q G F E CEAR SIFT/ OAD Q G F E SERIA INPUT INIBIT CEAR A B C D CK A B C D INIBIT SERIA INPUT PARAE INPUTS 8 GND CEAR SIFT/ OAD INIBIT INPUTS FUNCTION TABE SERIA PARAE INTERNA OUTPUTS A... Q A Q B OUTPUT Q X X X X X X X X Q A0 Q B0 Q 0 X a... h a b h X Q An Q Gn X Q An Q Gn X X X Q A0 Q B0 Q 0 2

3 Typical Clear, Shift, oad, Inhibit, and Shift Sequences INIIBIT CEAR SERIA INPUT SIFT/OAD PARAE INPUTS A B C D E F G OUTPUT Q CEAR SERIA SIFT CEAR SERIA INPUT SIFT/OAD A (9) (1) (15) (2) OAD INIBIT R CK S SERIA SIFT B C D E F (3) (4) (5) (10) (11) Q A Q B Q C Q D Q E INIBIT (12) G (14) (7) (6) Q F Q G (13) Q 3

4 DC CARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter imits Min Typ Max V I Input IG Voltage 2.0 V Unit Test Conditions Guaranteed Input IG Voltage for All Inputs V I Input OW Voltage 0.8 V Guaranteed Input OW Voltage for All Inputs V IK Input Clamp Diode Voltage V V CC = MIN, I IN = 18 ma V O Output IG Voltage V V CC = MIN, I O = MAX, V IN = V I or V I per Truth Table V O I I Output OW Voltage Input IG Current V I O = 4.0 ma V CC = V CC MIN, V IN = V I or V I V I O = 8.0 ma per Truth Table 20 μa V CC = MAX, V IN = 2.7 V 0.1 ma V CC = MAX, V IN = 7.0 V I I Input OW Current 0.4 ma V CC = MAX, V IN = 0.4 V I OS Short Circuit Current (Note 2) ma V CC = MAX I CC Power Supply Current 38 ma V CC = MAX 2. Not more than one output should be shorted at a time, nor for more than 1 second. 4

5 TEST TABE FOR SYNCRONOUS INPUTS DATA INPUT FOR TEST SIFT/OAD OUTPUT TESTED 0 V Q at t n+1 Serial Input 4.5 V Q at t n+8 AC WAVEFORMS CEAR INPUT t w(clear) t n t n + 1 (SEE NOTE 1) t n t n V 0 V INPUT DATA INPUT (SEE TEST TABE) t w(clock) t su t h t su t h 3 V 0 V 3 V 0 V OUTPUT Q t P (clear-q) t P t P (CK-Q) (CK-Q) V O V O NOTE 1. t n = bit time before clocking transition NOTE 1. t n+1 = bit time after one clocking transition NOTE 1. t n+8 = bit time after eight clocking transition NOTE 1. S166 = 1.3 V. AC CARACTERISTICS (T A = 25 C) Symbol Parameter imits Min Typ Max Unit f MAX Maximum Clock Frequency Mz t P Clear to Output ns t P t P Clock to Output ns Test Conditions V CC = 5.0 V C = 15 pf AC SETUP REQUIREMENTS (T A = 25 C) imits Symbol Parameter Min Typ Max Unit t W Clock Clear Pulse Width 30 ns t s Mode Control Setup Time 30 ns t s Data Setup Time 20 ns t h old Time, Any Input 15 ns Test Conditions V CC = 5.0 V 5

6 PACKAGE DIMENSIONS N SUFFIX PASTIC PACKAGE CASE ISSUE R 16 A 1 8 G F 9 D 16 P B S C K 0.25 (0.010) M T T SEATING PANE A M J M NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y14.5M, CONTROING DIMENSION: INC. 3. DIMENSION TO CENTER OF EADS WEN FORMED PARAE. 4. DIMENSION B DOES NOT INCUDE MOD FAS. 5. ROUNDED CORNERS OPTIONA. INCES MIIMETERS DIM MIN MAX MIN MAX A B C D F G BSC 2.54 BSC BSC 1.27 BSC J K M S

7 PACKAGE DIMENSIONS D SUFFIX PASTIC SOIC PACKAGE CASE 751B 05 ISSUE J T SEATING PANE G A K B D 16 P 0.25 (0.010) M T B S A S P 8 P 0.25 (0.010) M B S C M R X 45 J F NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y14.5M, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS A AND B DO NOT INCUDE MOD PROTRUSION. 4. MAXIMUM MOD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE (0.005) TOTA IN EXCESS OF TE D DIMENSION AT MAXIMUM MATERIA CONDITION. MIIMETERS INCES DIM MIN MAX MIN MAX A B C D F G 1.27 BSC BSC J K M P R

8 PACKAGE DIMENSIONS M SUFFIX SOEIAJ PACKAGE CASE ISSUE O e Z b D A E A (0.005) M 0.10 (0.004) 8 E VIEW P M E Q 1 DETAI P c NOTES: 1. DIMENSIONING AND TOERANCING PER ANSI Y14.5M, CONTROING DIMENSION: MIIMETER. 3. DIMENSIONS D AND E DO NOT INCUDE MOD FAS OR PROTRUSIONS AND ARE MEASURED AT TE PARTING INE. MOD FAS OR PROTRUSIONS SA NOT EXCEED 0.15 (0.006) PER SIDE. 4. TERMINA NUMBERS ARE SOWN FOR REFERENCE ONY. 5. TE EAD WIDT DIMENSION (b) DOES NOT INCUDE DAMBAR PROTRUSION. AOWABE DAMBAR PROTRUSION SA BE 0.08 (0.003) TOTA IN EXCESS OF TE EAD WIDT DIMENSION AT MAXIMUM MATERIA CONDITION. DAMBAR CANNOT BE OCATED ON TE OWER RADIUS OR TE FOOT. MINIMUM SPACE BETWEEN PROTRUSIONS AND ADJACENT EAD TO BE 0.46 ( 0.018). MIIMETERS INCES DIM MIN MAX MIN MAX A A b c D E e 1.27 BSC BSC E E M Q Z ON Semiconductor and are registered trademarks of Semiconductor Components Industries, C (SCIC). SCIC reserves the right to make changes without further notice to any products herein. SCIC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCIC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. Typical parameters which may be provided in SCIC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including Typicals must be validated for each customer application by customer s technical experts. SCIC does not convey any license under its patent rights nor the rights of others. SCIC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCIC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCIC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCIC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCIC was negligent regarding the design or manufacture of the part. SCIC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBICATION ORDERING INFORMATION ITERATURE FUFIMENT: iterature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado USA Phone: or Toll Free USA/Canada Fax: or Toll Free USA/Canada orderlit@onsemi.com N. American Technical Support: Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: Japan Customer Focus Center Phone: ON Semiconductor Website: Order iterature: For additional information, please contact your local Sales Representative SN74S166/D