CS 152 Computer Architecture and Engineering. Lecture 11 VLSI

Transcription

1 CS 152 Computer Architecture and Engineering Lecture 11 VLSI John Lazzaro ( TAs: David Marquardt and Udam Saini www-inst.eecs.berkeley.edu/~cs152/

2 Today: State Storage Tools on Silicon ICs Capacitance: Holds state as charge Transistors: How to move charge Layout: How to fabricate your IC DRAM: 1 Transistor + 1 Capacitor VLSI == Very Large Scale Integration The tall thin designer, with feet on the ground and head in the sky. The ground: Physics and IC Fabrication The sky: Architecture and Applications Carver Mead

3 Capacitance

4 Recall: Building a capacitor Dielectric Top Plate Conducts electricity well. (metal, doped polysilicon) An insulator. Does not conducts electricity at all. (air, glass (silicon dioxide)) Bottom Plate Conducts electricity well (metal, doped polysilicon)

5 Recall: Capacitors in action Because the dielectric is an insulator, and does not conduct. I = After circuit settles... Q = C V = C * 1.5 Volts (D cell) Q: Charge stored on capacitor C: The capacitance of the device: function of device shape and type of dielectric. After battery is removed: Still, Q = C * 1.5 Volts Capacitor remembers charge 1.5V

6 Capacitors and current... Q = C V I V Differentiate with respect to time... if C!= C(t)... dq/dt = C dv/dt I is defined as dq/dt... I = C dv/dt Observation: If a voltage change dv occurs in zero time (dt = 0), the current I is infinite (impossible). The voltage across a capacitor cannot change instantaneously. And by Q = C V, the charge stored on a capacitor cannot change instantaneously.

7 Storing computational state as charge State is coded as the amount of energy stored by a device V State is read by sensing the amount of energy Problems: noise changes Q (up or down), parasitics leak or source Q. Fortunately, Q cannot change instantaneously, but that only gets us in the ballpark.

8 How do we fight noise and win? Store more energy than we expect from the noise. Q = CV. To store more charge, use a bigger V or make a bigger C. Cost: Power, chip size. Example: 1 bit per capacitor. Write 1.5 volts on C. To read C, measure V. V > 0.75 volts is a 1. V < 0.75 volts is a 0. Cost: Could have stored many bits on that capacitor. Represent state as charge in ways that are robust to noise. Correct small state errors that are introduced by noise. Cost: Complexity. Ex: read C every 1 ms Is V > 0.75 volts? Write back 1.5V (yes) or 0V (no).

9 MOS Transistors Two diodes and a capacitor in an interesting arrangement. So, we begin with a diode review...

10 Diodes in action... Resistor Light emitting diode (LED) Light on? Yes! Light on? No!

11 Diodes: Current vs Voltage Anode + Diode is off I - Io Diode is on I Io exp(v/vo) I V - Cathode I = Io [exp(v/vo) - 1] Io range: 1fA to 1nA Vo range: 25mV to 60 mv

12 Making a diode on a silicon wafer

13 A pure ( intrinsic ) silicon crystal... Conducts electricity better than an insulator, worse than a conductor. Why? Most electrons (dots) are in a full valence band. Moving in the band is difficult. Especially near 0 degrees K. Lots of room, but few electrons. Forbidden band gap Conduction band Valence band Many electrons, but packed too tight to move. e l e c t r o n e n e r g y

14 Intrinsic silicon crystal as T rises... Some valence band electrons diffuse into the conduction band. These electrons leave behind holes in the valence band, allowing remaining electrons to move easier. More electrons, better conduction Conduction band Valence band We think of holes as positive carriers... e l e c t r o n e n e r g y

15 We engineer crystal with impurities...

16 N-type silicon: add donor atoms Use diffusion or ion implantation to replace some of the Si atoms with As Arsensic has an extra electron that is donates to the conduction band. n+ : heavy doping. n- : light doping. Electrons from donor atoms. Improves conductivy. No change in the number of holes Conduction band Donor energy Valence band e l e c t r o n e n e r g y

17 P-type silicon: add acceptor atoms Use diffusion or ion implantation to replace some of the Si atoms with Boron Boron has one fewer electron than Si. It can accept valence band electrons, creating holes. p+ : heavy doping. p- : light doping. No change in conduction band electron count Conduction band Acceptor energy Valence band Number of holes increased, conductivity improves e l e c t r o n e n e r g y

18 How to make a silicon diode V Cathode: - Anode: + n+ p- Wafer cross-section Wafer doped p-type p- region depletion At V = 0, hill too high for region electrons to diffuse up. n+ region For holes, going downhill is hard. no carriers V controls hill. depletion region e l e c t r o n e n e r g y

19 Diodes: Current vs Voltage Anode + Diode is off I - Io Diode is on I Io exp(v/vo) I V - Cathode I = Io [exp(v/vo) - 1] Io range: 1fA to 1nA Vo range: 25mV to 60 mv

20 Note: IC Diodes are biased off! V1 V1 n+ V2 n+ V2 p- 0 V - ground V1, V2 > 0V. Diodes off, only current is Io leakage. I = Io [exp(v/vo) - 1] Anodes of all diodes on wafer connected to ground.

21 Administrivia: Xilinx checkoff, HW 2 Based on Spring 05 Mid-term II... Xilinx checkoff: Pipelining w/o the hard parts...

22 MOS Transistors Two diodes and a capacitor in an interesting arrangement...

23 What we want: the perfect switch. V1 n+ V1 Switch is off. V1 is not connected to V2. p- Switch is on. V1 is connected to V2. n+ p- V2 n+ V2 We want to turn a p-type region into an n-type region under voltage control. We need electrons to fill valence holes and add conduction band electrons

24 An n-channel MOS transistor (nfet) Vd = 1V Vd = 1V I na n+ I µa n+ Vg = 0V dielectric p- Vg = 1V dielectric p- n+ Vs = 0V n+ Vs = 0V Polysilicon gate, dielectric, and substrate form a capacitor. nfet is off (I is leakage ) Vg = 1V, small region near the surface turns from p-type to n-type. nfet is on.

25 Drawing an nfet Mask drawings sent to the fabrication facility to make the chips.

26 Mask set for an n-fet (circa 1986) Vg = 0V Vd = 1V I na n+ dielectric p- Vs = 0V Masks #1: n+ diffusion n+ #2: poly (gate) #3: diff contact #4: metal Top-down view: Layers to do p-fet not shown. Modern processes have more 6 to 10 metal layers (in 1986: 2)

27 Design rules for masks, Poly overhang. So that if masks are misaligned, we still get --- in channel. Minimum gate length. So that the source and drain depletion regions do not meet! length Metal rules:contact separation from channel, one fixed contact size, overlap rules with metal, etc... #1: n+ diffusion #3: diff contact #2: poly (gate) #4: metal

28 Fabrication

29 Mask set for an n-fet... Vd = 1V p- Top-down view: I µa n+ Vg = 1V Vs = 0V dielectric n+ Vg Masks Vd Ids Vs #1: n+ diffusion #2: poly (gate) #3: diff contact #4: metal How does a fab use a mask set to make an IC?

30 Start with an un-doped wafer... UV hardens exposed resist. A wafer wash leaves only hard resist. oxide p- Steps #1: dope wafer p- #2: grow gate oxide #3: grow undoped polysilicon #4: spin on photoresist #5: place positive poly mask and expose with UV.

31 Wet etch to remove unmasked... HF acid etches through poly and oxide, but not hardened resist. oxide p- oxide p- After etch and resist removal

32 Use diffusion mask to implant n-type accelerated donor atoms oxide n+ n+ p- Notice how donor atoms are blocked by gate and do not enter channel. Thus, the channel is selfaligned, precise mask alignment is not needed!

33 Metallization completes device oxide n+ n+ p- Grow a thick oxide on top of the wafer. oxide n+ n+ p- Mask and etch to make contact holes oxide n+ n+ p- Put a layer of metal on chip. Be sure to fill in the holes!

34 Final product... Vd Vs The planar process oxide n+ n+ p- Top-down view: Jean Hoerni, Fairchild Semiconductor 1958

35 p-channel Transistors

36 p-fet: Change polarity of everything V well = Vs = 1V I µa p+ Vg = 0V Vd = 0V dielectric n-well p- p+ Vg Vs Isd Vd New n-well mask Mobility of holes is slower than electrons. p-fets drive less current than n-fets, all else being equal

37 Device Equations

38 Recall: Our old switch model... We begin by modeling transistors that are off Vdd 1 A on p-fet fills up the capacitor with charge. Open Charge 0 Water level Time Vdd Vdd 1 A on n-fet empties the bucket. n Open Out Discharge 0 Water level Time

39 Recall: Why diode current is I = exp(v) V Cathode: - Anode: + n+ p- Wafer cross-section Wafer doped p-type p- region depletion At V = 0, hill too high for region electrons to diffuse up. n+ region For holes, going downhill is hard. no carriers V controls hill. depletion region e l e c t r o n e n e r g y

40 e l ec tr on en er gy A simple model for off transistor... Vd = 1V I na n+ Vg = 0.2V dielectric p- Vs = V sub = 0V n+ Ids = Io [exp((κvg - Vs)/Vo)] [1 - exp(-vds/vo)] Vg exponential dependence n+ region 1 if Vds > 70mV n+ region Io 100fA, Vo = kt/q = 25mV, κ = 0.7 Vg Vd Ids Vs Current flows when electrons diffuse to the gate wall top # electrons that reach top goes up as wall comes down, implies Ids exp(vg)

41 A simple model for on transistor... Vd = 2V I µa n+ Vg = 1V dielectric p- Vs = V sub = 0V n+ Vg Ids = (carriers in channel) / (transit time) Q = CV f(length, velocity) Vd Ids Vs Ids = [(µεw)/(ld)] [Vgs -Vth] [Vds] If Vds > Vgs - Vth, channel physics change : Ids = [(µεw)/(2ld)] [Vgs -Vth]^2 W = transistor width, L = length, D = capacitor plate distance µ is velocity, ε is C dilectric constant

42 Dynamic Memory (DRAM)

43 Recall: Capacitors in action Because the dielectric is an insulator, and does not conduct. I = After circuit settles... Q = C V = C * 1.5 Volts (D cell) Q: Charge stored on capacitor C: The capacitance of the device: function of device shape and type of dielectric. After battery is removed: Still, Q = C * 1.5 Volts Capacitor remembers charge 1.5V

44 DRAM cell: 1 transistor, 1 capacitor Bit Line Word Line Vdd Word Line Vdd Capacitor Bit Line Bit Line n+ n+ p- oxide oxide Word Line and Vdd run on z-axis Why Vcap values start out at ground. Vcap Vdd Diode leakage current.

45 A 4 x 4 DRAM array (16 bits)...

46 Invented after SRAM, by Robert Dennard

47 DRAM Circuit Challenge #1: Writing Vdd Vdd Vgs Vdd Vdd - Vth. Bad, we store less charge. Why do we not get Vdd? Ids = [(µεw)/(2ld)] [Vgs -Vth]^2, but turns off when Vgs <= Vth! Vgs = Vdd - Vc. When Vdd - Vc == Vth, charging effectively stops! Vc

48 DRAM Challenge #2: Destructive Reads Bit Line (initialized to a low voltage) (stored charge from cell) Word Line + 0 -> Vdd Vc -> 0 Vgs Vdd Raising the word line removes the charge from every cell it connects too! Must write back after each read.

49 DRAM Circuit Challenge #3a: Sensing Assume Ccell = 1 ff Word line may have 2000 nfet drains, assume word line C of 100 ff, or 100*Ccell. Ccell holds Q = Ccell*(Vdd-Vth) 100*Ccell Ccell When we dump this charge onto the word line, what voltage do we see? dv = [Ccell*(Vdd-Vth)] / [100*Ccell] dv = (Vdd-Vth) / 100 tens of millivolts! In practice, scale array to get a 60mV signal.

50 DRAM Circuit Challenge #3b: Sensing How do we reliably sense a 60mV signal? Compare the word line against the voltage on [...] a dummy world line. sense amp Word line to sense + Dummy word line.? - Cells hold no charge. Dummy word line

51 DRAM Challenge #4: Leakage... Bit Line Word Line Parasitic currents leak away charge. Solution: Refresh, by reading cells at regular intervals (tens of milliseconds) + Vdd n+ n+ p- oxide oxide Diode leakage...

52 DRAM Challenge #5: Cosmic Rays... Bit Line Word Line Cell capacitor holds 25,000 electrons (or less). Cosmic rays that constantly bombard us can release the charge! Solution: Store extra bits to detect and correct random bit flips (ECC). + Vdd n+ n+ p- oxide oxide Cosmic ray hit.

53 DRAM Challenge 6: Yield If one bit is bad, do we throw chip away? [...] Extra word lines. Used for sparing. Solution: add extra word lines (i.e. 80 when you only need 64). During testing, find the bad word lines, and use high current to burn away fuses put on chip to remove them.

54 DRAM Challenge 7: Scaling Each generation of IC technology, we shrink width and length of cell. If we keep the same cell layout, Ccell will shrink too! As will Q = Ccell*(Vdd-Vth) As will voltage to be sensed on word line. Recall: dv = [Ccell*(Vdd-Vth)] / [100*Ccell] Solution: Constant Innovation of Cell Capacitors!

55 Poly-diffusion Ccell is ancient history Bit Line Word Line Vdd Word Line Vdd Capacitor Bit Line Bit Line oxide n+ n+ p- oxide Word Line and Vdd run on z-axis

56 Modern cells: trench capacitors

57 Modern cells: stacked capacitors

58 Lessons learned Capacitors hold state Semiconductor physics Drawing transistors Transistor wrap-up: Fabrication, p-fets, device model equations. DRAM: 1 Transistor + 1 Capacitor

59 Lectures: Coming up next... Memory array structures and interfaces. The memory hierarchy