Investigation of the Dimension Effects of Sub-30nm Multiple-Gate SOI MOSFETs by TCAD Simulation

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1 Microelectronics and olid tate Electronics 212, 1(3): OI: /j.msse Investigation of the imension Effects of ub-3nm Multiple-ate OI MOFETs by TCA imulation Keng-Ming Liu *, Yung-Yu Hsieh epartment of Electrical Engineering, National ong Hwa University, Hualien, 974-1, Taiwan Abstract In this paper we use the commercial semiconductor device simulator, entaurus, to simulate the electrical characteristics of sub-3nm multiple-gate (M) silicon-on-insulator (OI) MOFETs. The gate configurations of the simulated M OI MOFETs include: single-gate (), two kinds of double-gate (), triple-gate (), and gate-all-around (). We examine the effects of the dimensions of the gate length, fin height, fin width, and the transport models for each gate configuration. The simulation results can serve as the guidelines of device design and they indicate that as the gate length scales down to 15 nm below, only,, and configurations with specific fin cross-section dimensions can meet the device requirements. Keywords evice imulation, Multiple-ate, MOFET, TCA, OI, imension 1. Introduction As the channel length of MOFETs keep scaling down within nanometer scale, the short channel effects (CEs) become so detrimental that the conventional planar bulk MOFET structure shows poor device performance. To improve the gate control over the channel region, the multiple-gate (M) MOFET structure has been proposed and studied by both fabrication[1-6] and simulation[7-13]. It is believed that there is a great possibility for the M MO- FET structure to be used in the 22-nm VLI technology node and the following nodes. Furthermore, silicon-oninsulator (OI) M MOFET structure has been considered as the ultimate device structure in the future. In this paper, we use the mainstream technology CA (TCA) tools in industry, entaurus (which is the product of ynopsys Inc.), to simulate various gate configurations and dimensions for the OI M MOFET structure. Most of the previous simulation studies on OI M MOFETs focused on the specific gate configurations[8-11]. In this paper, we simulate all the possible gate configurations for the OI M MOFETs: single-gate (), double-gate (), triple-gate (), and gate-all-around () configurations. The similar simulation study has been made before[7], however, the gate lengths of the simulated devices are above 3 nm therein. In this work, we investigate the device characteristics of the OI M MOFETs with the gate length less than 3 nm by 3 TCA simulation and also examine the * Corresponding author: kmliu@mail.ndhu.edu.tw (Keng-Ming Liu) Published online at Copyright 212 cientific & Academic Publishing. All Rights Reserved effects of the transport models on the device simulation results. 2. evice tructure and imulation Approach Figure 1 shows the simulated gate configurations for the OI M MOFET structure. The gate configurations include:,,, and configurations. Note that the configuration has two types: (1) the two gates are in parallel (-1) and (2) the two gates are connected (-2). All gate configurations have 1Å gate oxide (io 2 ) and 2 nm source and drain regions. For simplicity, we assume that the junctions are abrupt and there is no overlap or underlap between the gate and the source/drain. The doping concentration in the source and drain regions is n-type 1 2 cm -3 and that in the channel region is p-type cm -3. The work-function difference is adjusted to make each simulated device has a threshold voltage of.3 V. imply using the n + polysilicon gate without adjusting the work-function difference will result in a negative threshold voltage for the OI M MOFETs presented here. The supply voltage, V, is set to be 1 V. The values of the gate oxide thickness, channel doping, threshold voltage, and supply voltage are chosen according to the 9 International Technology Roadmap for emiconductors (ITR). The gate length, fin height, and fin width are varied from 15 to 3 nm, 1 to 2 nm, and 1 to 2 nm, respectively. In this work, we focus on examining the effects of the dimensions of the gate length, fin height, and fin width of the OI M MOFETs. evice simulation was performed by entaurus. Figure 2 shows the simulation flow. First, we use the entaurus

2 Microelectronics and olid tate Electronics 212, 1(3): tructure Editor (E) to define the desired device structures and the associated parameters. Then we put the outcome of E into the entaurus evice (evice) to simulate the device characteristics. There are at least two transport models which are available in evice: drift-diffusion () model and hydrodynamic (H) model. The simulation results of these two models will be shown in the following. The H model includes the carrier temperature effect and the energy current in addition to the electron and hole currents which are considered by the model. Therefore, we expect the simulation results from the H model should be more accurate. Besides the and H models, we also examine the effects of quantum confinement by including the density gradient () model into the evice simulation. To include quantization effects, evice uses a potential quantity n in the classical electron density formula [14]: EF, n EC n n N C F (1) 1/ 2 ktn where N C is the effective density of states in the conduction band and F 1/2 ( ) is the Fermi-irac integral. imilarly, there is a p for holes. For density gradient model, n is given by [14] 2 2 γ n n (2) 6m n n where is a fit factor. ince n is n -dependent, (2) needs to be solved numerically. (1) (2) (3) (4) (5) Buried oxide ilicon substrate Figure 1. ifferent gate configurations for the OI M MOFETs. The gate configurations include: (1), (2), (3) -1, (4) -2 and (5) configurations Figure 3. The I -V curves of the MOFETs with 3-nm or 15-nm gate length and 11 nm 2 fin cross section under different transport models (, H, and H+) Table 1. The Electrical Characteristics of the MOFETs with 15-nm ate Length and 11 nm 2 Fin Cross ection under ifferent Transport Models (, H, and H+) Model Characteristics H H+ (mv/dec) I on (A) I off (A) I on/i off Figure 2. imulation flow of entaurus TCA tools [14] Figure 3 shows the I -V curves of the MOFETs with 3-nm or 15-nm gate length and 11 nm 2 fin cross section under different transport models (, H, and H+). For the 3-nm gate length, the simulation results of different transport models are very close. However, as the gate length reduces to 15 nm, the difference caused by

3 66 Keng-Ming Liu et al.: Investigation of the imension Effects of ub-3nm Multiple-ate OI MOFETs by TCA imulation using different transport model is obvious. Table 1 shows the electrical characteristics of the 15-nm MOFET under different transport models which are derived from Figure 3. For 15-nm gate length, using either or H model only may overestimate the subthreshold swing () and adopting model only may underestimate the current drive. The degradation of caused by including the model is due to the increase of the effective oxide thickness (EOT) as quantum confinement is considered. We believe that using H model combined with model should be more realistic for the nanoscale devices. Therefore, all the following simulation results are based on H model combined with model. 3. imulation Results and iscussion There are actually four fin cross sections for the simulated OI M MOFETs as shown in Figure 4: (1) 22 nm 2, (2) 21 nm 2 (fin height fin width), (3) 12 nm 2, and (4) 11 nm 2. Figures 5, 6, 7, and 8 show the drain-induced barrier lowering (IBL) and the subthreshold swing () of the OI M MOFETs with these four cross sections (Figure 4) as the gate length decreases from 3 nm to 15 nm under different gate configurations. The IBL is defined as the difference in threshold voltage when the drain voltage is increased from.5 V to 1 V. As shown in Figure 5, there is no gate configuration can have a IBL value below 6 mv or a value below 3 mv/dec for the 15-nm gate-length OI M MOFETs with the 22 nm 2 fin cross section. The smaller fin cross section shows the better IBL and as shown in Figure 8. The configuration has the best IBL and for any fin cross section. However, for the 21 nm 2 and 12 nm 2 fin cross sections, the device characteristics of the and -1 configurations, respectively, are comparable to those of the configuration as shown in Figures 6 and 7. The -1 configuration has better performance than the -2 configuration except for the 21 nm 2 fin cross section since the gate width of the -1 configuration is small (1 nm per gate) in this case. In general, more gate coverage results in better immunity against CEs. Table 2 is the summary for the device characteristics of the 15-nm gate-length MOFETs under different fin cross sections. The device with the 11 nm 2 fin cross section has the best device performance and the and on-off current ratio are 86.6 mv/dec and , respectively. (1) (2) (3) (4) Figure 4. Four fin cross sections for the simulated OI M MOFETs: (1) 22 nm 2, (2) 21 nm 2 (fin height fin width), (3) 12 nm 2, and (4) 11 nm 2. Here the configuration is used as an illustration. A W fin =H fin =2nm Figure 5. IBL and of the OI M MOFETs with the fin cross section 22 nm 2 as the gate length decreases from 3 nm to 15 nm under different gate configurations W fin =H fin =2nm H fin =2nm,W fin =1nm Figure 6. IBL and of the OI M MOFETs with the fin cross section 21 nm 2 (fin height fin width) as the gate length decreases from 3 nm to 15 nm under different gate configurations H fin =2nm,W fin =1nm H fi

4 Microelectronics and olid tate Electronics 212, 1(3): m ) Figure 7. IBL and of the OI M MOFETs with the fin cross section 12 nm 2 (fin height fin width) as the gate length decreases from 3 nm to 15 nm under different gate configurations H fin =1nm,W fin =2nm H fin =1nm,W fin =2nm W fin =H fin =1nm W fin =H fin =1nm Figure 8. IBL and of the OI M MOFETs with the fin cross section 11 nm 2 as the gate length decreases from 3 nm to 15 nm under different gate configurations Table 2. ummary for the evice Characteristics of the 15-nm ate-length MOFETs under ifferent Fin Cross ections (Fin Height Fin Width) Characteristics Height Width (mv/ dec) IBL (mv) I on (A) I off (A) I on/ I off 2 2 nm NA nm nm nm Conclusions In this work, we have investigated the effects of various fin dimensions on the device characteristics of the OI M MOFETs with the, -1, -2,, and configurations. The simulation results indicate that the smaller fin cross section and higher gate-coverage ratio will result in the better CE immunity. The configuration has the best device performance for any fin cross section. For some rectangular fin cross sections, the device characteristics of the and -1 configurations are comparable to those of the configuration. For the 15 nm gate length, only,, and -1 configurations with particular fin cross-section dimensions can fulfill the device requirements. ACKNOWLEEMENT This work is supported by Taiwan National cience Council (NC) under Contract NC E We are also grateful to the Taiwan National Center for High-performance Computing for computing facilities. REFERENCE [1] F. L. Yang et al., 5nm-gate nanowire FinFET, in Proc. VLI ymp. Tech. ig., 4, pp [2].. uk et al., High-performance twin silicon nanowire MOFET(TNWFET) on bulk i wafer, IEEE Transactions on Nanotechnology, vol. 7, no. 2, pp , 8. [3]. Hisamoto et al., FinFET-A self-aligned double-gate MOFET scalable to 2 nm, IEEE Transactions on Electron evices, vol. 47, no. 12, pp ,. [4] B. Yu et al., FinFET scaling to 1 nm gate length," in Tech. igest, IEM, 2, pp [5] C. Y. Chang et al., A 25-nm gate-length FinFET transistor module for 32nm node, in Tech. igest, IEM, 9, pp [6] X. Huang et al., ub-5nm p-channel FinFET, IEEE Transactions on Electron evices, vol. 48, no. 5, pp , 1. [7] J. T. Park and J. P. Colinge, Multiple-gate OI MOFETs: device design guidelines, IEEE Transactions on Electron evices, vol. 49, no. 12, pp , 2.

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