A Bottom-gate Depletion-mode Nanowire Field Effect Transistor (NWFET) Model Including a Schottky Diode Model

Transcription

1 Journal of the Korean Physical Society, Vol. 55, No. 3, September 2009, pp A Bottom-gate Depletion-mode Nanowire Field Effect Transistor (NWFET) Model Including a Schottky Diode Model Y. S. Yu Department of Information & Control Engineering and Electronic Technology Institute, Hankyong National University, Anseong S. H. Lee, D. S. Kim, Y. C. Jung and S. W. Hwang Department of Computer & Electronics Engineering and Research Center for Time Domain Nano-Functional Devices, Korea University, Seoul D. Ahn Institute of Quantum Information Processing & Systems, University of Seoul, Seoul (Received 26 August 2008) We present a compact model for a bottom-gate depletion-mode nanowire field-effect transistor (NWFET) including a Schottky diode model for efficient circuit simulation. The NWFET model is based on an equivalent circuit corresponding to two back-to-back Schottky diodes for the metalsemiconductor (MS) contacts separated by a depletion-mode NWFET for the intrinsic NWFET. The previously developed depletion-mode NWFET model is used for the intrinsic part of the NWFET. The Schottky diode model for the M-S contacts includes the thermionic field emission (TFE) and the thermionic emission (TE) mechanisms for reverse bias and forward bias, respectively. Our newly developed model is integrated into Advanced Design System (ADS), in which the extrinsic part (Schottky diode model) and the intrinsic part of the NWFET are developed by utilizing the symbolically defined device (SDD) for an equation-based nonlinear model. The results simulated from the newly developed NWFET model reproduce the experimental results within 10% errors. The mobilities extracted from the newly developed NWFET model are compared with those extracted from the previously reported NWFET model which replaced the Schottky diodes with series resistances. PACS numbers: V, T, H, S, Keywords: Nanowire field-effect transistor, Schottky diode, Thermionic emission, Thermionic field emission, Equivalent circuit I. INTRODUCTION Semiconducting nanowires offer many opportunities for the assembly of nanoscale devices and arrays by using the bottom-up paradigm [1,2]. Semiconducting nanowire field-effect transistor (NWFETs) fabricated by using the bottom-up paradigm have demonstrated promising fieldeffect transistor (FET) characteristics in top-gate [3], back-gate [4 7], and surround-gate [8] FET geometries. The nanowire circuits defined by assembly of nanowire components, such as the NWFETs, have already been demonstrated [9 11]. Many NWFETs had bottom-gate structures [1,2,4 7], and most NWFETS have operated in the accumulation or the depletion mode [1 4,8,12,13]. The NWFETs using a semiconducting nanowire generally have a metal-semiconductor-metal (MSM) structure ysyu@hknu.ac.kr; Fax: [1 13]. The metal-semiconductor (MS) contacts can be classified as Schottky and Ohmic contacts [14]. Most NWFETs are composed of two Schottky contacts connected back to back in series with a semiconducting nanowire operating as an intrinsic NWFET [14]. A few compact models of depletion-mode NWFETs with bottom-gate structure have been reported so far to design and simulate the nanowire circuits [12, 13, 15]. Yim et al. [12] used an equivalent circuit model of a depletion-mode ZnO NWFET with a back-gate structure by using PSPICE. It consisted of back-to-back diodes for the metal-nanowire contacts and a MOSFET for the nanowire channel. Because it used the built-in diode model and MOSFET LEVEL 1 model provided by PSPICE, the physical characteristics of the depletionmode NWFET could not be explained exactly. Cha et al. [13] proposed a capacitance and current-voltage model of a depletion-mode GaN NWFET with a bottom-gate

2 A Bottom-gate Depletion-mode Nanowire Field Effect Transistor (NWFET) Model Y. S. Yu et al Fig. 1. 3D schematic diagram of an n-type NWFET with a bottom-gate structure. structure by using a simplified electrostatic analysis. The model included the surface depletion effects. The model did not include current conduction due to accumulated charges in the nanowire when charges were accumulated by the applied gate voltage. Recently, we developed a depletion-mode NWFET model, including the surface depletion effect and the accumulated charges [15]. However, because the NWFET model does not yet consider the nonlinear characteristics for the MS Schottky contacts, a new NWFET model including the nonlinear contact model is required. In this paper, for efficient circuit simulation, we will present a new compact model of depletion-mode n-type NWFET. The NWFET model will be based on an equivalent circuit corresponding to two back-to-back Schottky diodes for the MS contacts separated by one depletionmode NWFET for the intrinsic NWFET. The intrinsic NWFET model will include the current conduction of bulk charges through the center neutral region and of accumulation charges through the surface accumulation region; thus, it will include all current conduction mechanisms of an NWFET operating at various bias conditions. The Schottky diode model for the MS contacts will include the thermionic field emission (TFE) and the thermionic emission (TE) mechanisms for reverse bias and forward bias, respectively. To verify the validity of our model, we compare the results from our model with the experimental results for two types of NWFETs. II. NWFET MODELING Figure 1 shows the 3-dimensional (3D) schematic diagram of a n-type NWFET with a bottom-gate structure used in this work. The NWFET channel doped with n-type doping concentration, Nd, is contacted by two metal electrodes (source and drain), and the bottom silicon gate is used to control the potential of the semiconducting nanowire. Here, W nw, L nw, t nw, and ε nw are the width, the length, the thickness, and the dielectric permittivity of the nanowire, respectively, t i and ε i are the thickness and the dielectric permittivity of the insulator, respectively, and x ds is the surface depletion depth. The surface depletion depth is given by x ds = (2ε nw V bi /qn d ) 1/2, where q is the electron charge and V bi is the surface Fermi level pinning potential by surface states [13]. The source in the device is grounded, and the voltages V ds and V gs are applied to the drain and the gate, respectively. The NWFET has an MSM structure. An equivalent circuit of the NWFET consists of two Schottky diodes (for MS contacts) connected backto-back in series with an intrinsic bottom-gate depletionmode NWFET, as shown in Fig. 2. Here, V is is the voltage of the intrinsic source node, and V id is that of the intrinsic drain node. The intrinsic NWFET model has been derived with the following procedure [15]. Solving the Poisson s equation in the vertical direction of the channel, the depletion width in the nanowire, x d, is expressed as [16] x d (y) = W { eff ε nw C i 1 } 2C i qn d ε nw Weff 2 [V G V F B V (y)], (1) where W eff = W nw 2x ds and C i is the gate insulator capacitance per unit length [13]. Under this condition, the conducting channel is in the center neutral portion (non-depleted region) of the nanowire, and the total number of mobile carriers per unit length in the center neutral channel (Q n) is given by Q n = qn d W eff (t eff x d ), (2) where t eff = t nw x ds. The depletion region at the bottom side in the nanowire disappears, and electrons are accumulated at the bottom surface. Under this situation, the total number of mobile carriers per unit length in the channel, which includes the total number of electrons per unit length in the center neutral region and in the accumulated region (Q acc), is given by Q n = qn d W eff t eff, Q acc = C i[v G V F B V (y)], (3) where V (y) is the channel potential at location y in the channel and V F B is the flat-band voltage of the gate. Depending on the bias-conditions, the mechanism of current conduction in a depletion-mode NWFET can be complicated. A depletion-mode NWFET has two current components. One is the body current, I body, occurring in the center neutral region of the device when the carriers in the nanowire are not fully depleted: I body = Q n µ n0 1 µn0 ν sat V y dv dy. (4)

3 Journal of the Korean Physical Society, Vol. 55, No. 3, September 2009 Fig. 2. Equivalent circuit of the NWFET. where µ no is the low-field bulk mobility and v sat is the electron saturated velocity. The other is the accumulation current, I acc, due to the electrons accumulated when the carriers at the bottom surface are accumulated: I acc = Q acc µ s0 1 µs0 ν sat V y dv dy. (5) where µ so (= k 1 µ no ) is the low-field bulk mobility for the mobile carriers in the accumulated region. Here, k 1 is a fitting parameter to account for the surface scattering effect. Depending on the bias-conditions, there are six cases of current conduction in depletion-mode NWFET, as shown in Ref. 15. The Schottky diode model for the MS contacts has been derived with the following procedure [17, 18]: the electron transport mechanisms for the MS barrier in NWFETs at forward bias and reverse bias hve been reported to be TE and TFE, respectively [14, 17]. The current for the forward bias region of the Schottky diode can be modeled by using the classic TE equation [19]. The current for the reverse bias region of the Schottky diode can be modeled by using the TFE equation for reverse bias voltage and intermediate temperature [20]. The current I of the TFE model can be expressed as [14, 17,18,20] I = SJ s exp( qv/ε ), (6) J s = A T 2 (πe 00 ) 1/2 φ B [ ev + kt cosh(e 00 /kt) ]1/2 exp( φ B E 0 ), (7) where V is the voltage applied to the Schottky diode, S is the diode area, A is the Richardson constant, φ B is the Schottky-barrier height (SBH), k is the Boltzmann constant, and T is the temperature. Other constants, such as ε, E o, and E oo, are given in Ref. 17 and 18. For the high current of the forward bias region, a series resistance due to the contact resistance is included in the Schottky diode model [17]. Barrier lowering of the SBH Fig. 3. I ds V ds characteristics of an n-type GaN NWFET with a bottom-gate structure for various values of V gs. in our model is represented by the following parameterbased equation [21], which is made to simply be put into the circuit simulator ADS [22]: φ B = φ B0 AV DS + BV GS + C. (8) Here, φ B0 is the ideal SBH without any SBH lowering effects [23], and A, B, and C are the fitting parameters for the V ds dependence, the V gs dependence, and the surface state effects [21], respectively. To implement the intrinsic part and the extrinsic part (two Schottky diodes) in the NWFET into ADS, each part utilizes a symbolically defined device (SDD) of the equation-based nonlinear model in ADS, based on the above equations for the drain current and the Schottky diode current. III. MODEL VERIFICATION Figure 3 shows the drain current-drain voltage (I ds V ds ) characteristics of an n-type GaN NWFET with a bottom-gate structure for various values of the gate voltage (V gs ). Symbols and lines denote the experimental data [13] and the data fitted by the newly developed model, respectively. Parameters for the intrinsic NWFET, fitted by the newly developed model, are t i = 40 nm, t nw = W nw = 33 nm, L nw = 4 µm, N d = cm 3, V F B = 0.2 V, µ n0 = 13.8 cm 2 /Vs, ν sat = cm/s, k 1 = 0.5, θ = 0.1, V bi = 1.0 V, n = 1.5, and I 0 = A. Parameters for the MS contacts, fitted by the newly developed model, are φ B0 = 2.0 ev, A = 0.5, B = 0.12, and C = 0.1. Fitting data simulated with the newly developed model reproduce the experimental data within a 5% error. Compared with the previously reported model of the NWFET [15] consisting of an intrinsic NWET and the source/drain series resistances, the mobility extracted by using the newly developed model is similar to that extracted by the previously reported model. The contact characteristics of the GaN NWFET show that its MS contacts do

4 A Bottom-gate Depletion-mode Nanowire Field Effect Transistor (NWFET) Model Y. S. Yu et al less than that extracted by using the newly developed model including the Schottky diode models. This mobility extraction shows that the newly developed model can explain more exactly the nonlinear characteristics of the MS contacts than the previously reported model which replaces the Schottky diodes with series resistances. IV. CONCLUSIONS Fig. 4. (a) I ds V ds characteristics of an n-type Si NWFET with a bottom-gate structure for various values of V gs and (b) I ds V gs characteristics of the Si NWFET for various values of V ds. not have Schottky barriers, but rather barriers that are nearly Ohmic. Figures 4(a) and (b) show the I ds V ds characteristics of an n-type Si NWFET with a bottom-gate structure for various values of V gs and the drain-current-gate voltage (I ds V gs ) characteristics of the Si NWFET for various values of V ds, respectively. Symbols and lines denote the experimental data [24] and the data fitted by the newly developed model, respectively. Parameters for the intrinsic NWFET [25,26], fitted by the newly developed model, are t i = 50 nm, t nw = W nw = 100 nm, L nw = 2 µm, N d = cm 3, V F B = 0.5 V, µ n0 = 100 cm 2 /Vs, ν sat = cm/s, k 1 = 1.0, θ = 0.001, V bi = 1.0 V, n = 1.5, and I 0 = A. Parameters for the MS contacts, fitted by the newly developed model, are φ B0 = ev, A = 0.02, B = , and C = Fitting data simulated with the newly developed model reproduce the experimental data within a 10% error. The value of the mobility (= (di ds /dv gs )Lln[(2t i + t nw /2)/(t nw /2)]/(2πε i V ds )) extracted from the previously reported model [15] which replaces the Schottky diodes with series resistances (R s = R d = 300 kω) is 38 cm 2 /Vs at V ds = 1 V, which is In summary, a compact model of a bottom-gate depletion-mode NWFET including a Schottky diode model for efficient circuit simulation was presented. The NWFET model was based on an equivalent circuit corresponding to two back-to-back Schottky diodes for the MS contacts separated by a depletion-mode NWFET for the intrinsic NWFET. The previously developed depletionmode NWFET model was used for the intrinsic part of the NWFET. The Schottky diode model for the MS contacts included the TFE and the TE mechanisms for reverse bias and forward bias, respectively. Our newly developed model was integrated into ADS, in which the extrinsic part (Schottky diode model) and intrinsic part of the NWFET were developed by utilizing the SDD for an equation-based nonlinear model. The results simulated with the newly developed NWFET model reproduced the experimental results within 10% errors. The mobilities extracted from the newly developed NWFET model were compared with those extracted from the previously reported NWFET model which replaced the Schottky diodes with series resistances. REFERENCES [1] L. Wei and C. M. Lieber, J. Phys. D: Appl. Phys. 39, R387 (2006). [2] C. M. Lieber and Z. L. Wang, MRS Bull. 32, 99 (2007). [3] J. Xiang, W. Lu, Y. Hu, Y. Wu, H. Yan and C. M. Lieber, Nature 441, 489 (2006). [4] S. Han, W. Jin, D. Zhang, T. Tang, C. Li, X. Liu, Z. Liu, B. Lei and C. Zhou, Chem. Phys. Lett. 389, 176 (204). [5] W. I. Park, J. S. Kim, G.-C. Yi, M. H. Bae and H.-J. Lee, Appl. Phys. Lett. 85, 5052 (2004). [6] D. Wang, Q. Wang, A. Javey, R. Tu, H. Dai, H. Kim, P. C. Mclntyre, T. Krishnamohan and K. C. Saraswat, Appl. Phys. Lett. 83, 2432 (2003). [7] S. M. Koo, M. D. Edelstein, Q. Li, C. A. Richter and E. M. Vogel, Nanotechnology 16, 1482 (2006). [8] T. L. Wade, X. Hoffer, A. D. Mohammed, J.-F. Dayen, D. Pribat and J.-E. Wegrowe, Nanotechnology 18, (2007). [9] R. S. Friedman, M. C. McAlpine, D. S. Ricketts, D. Ham and C. M. Lieber, Nature 434, 1085 (2005). [10] Y. Huang, X. Duan, Y. Cui, L. J. Lauhon, K. H. Kim and C. M. Lieber, Science 294, 1313 (2001). [11] Z. Zhong, D. Wang, Y. Cui, M. W. Bockrath and C. M. Lieber, Science 302, 1377 (2003).

5 Journal of the Korean Physical Society, Vol. 55, No. 3, September 2009 [12] C. Y. Yim, D. Y. Jeon, K. H. Kim, G. T. Kim, Y. S. Woo, S. Roth, J. S. Lee and S. Kim, J. Korean Phys. Soc. 48, 1565 (2006). [13] H.-Y. Cha, H. Wu, M. Chandrashekhar, Y. C. Choi, S. Chae, G. Koley and M. G. Spencer, Nanotechnology 17, 1264 (2006). [14] Z. Y. Zhang, C. H. Jin, X. L. Liang, Q. Chen and L.-M. Peng, Appl. Phys. Lett. 88, (2006). [15] Y. S. Yu, S. H. Lee, J. H. Oh, H. J. Kim, S. W. Hwang and D. Ahn, Semicond. Sci. Technol. 23, (2008). [16] J.-P. Colinge, IEEE Trans. Electron Devices 37, 718 (1990). [17] S. H. Lee, Y. S. Yu, S. W. Hwang and D. Ahn, J. Nanosci. Nanotechnol. 7, 4089 (2007). [18] S. H. Lee, Y. S. Yu, H. J. Kim, S. W. Hwang and D. Ahn, J. Korean Phys. Soc. 51, S298 (2007). [19] S. M. Sze, Physics of Semiconductor Devices, 2nd ed (Wiley, New York, 1981). [20] F. A. Padovani and R. Stratton, Solid State Electron. 9, 695 (1966). [21] S. H. Lee, Y. S. Yu, S. W. Hwang and D. Ahn, published to IEEE Trans. Nanotechnol. 8 (2009). [22] Agilent Technologies 2003 Advanced Design System. [23] S. Adachi, Properties of Group-IV, III-V and II-VI Semiconductors (John Wiley & Sons Ltd, West Sussex, England, 2005). [24] D. S. Kim, Y. C. Jung, M. Y. Park, B. S. Kim, S. H. Hong, M. S. Choi, M. G. Kang, Y. S. Yu, D. Whang and S. W. Hwang, IEEE Trans. Nanotechnol. 7, 683 (2008). [25] W. I. Park, J. Korean Phys. Soc. 53, L1759 (2008). [26] S.-H. Woo and D. Hwang, J. Korean Phys. Soc. 54, 152 (2009).