Modelling of capacitance and threshold voltage for ultrathin normally-off AlGaN/GaN MOSHEMT

Size: px
Start display at page:

Download "Modelling of capacitance and threshold voltage for ultrathin normally-off AlGaN/GaN MOSHEMT"

Transcription

1 Pramana J. Phys. (07) 88: 3 DOI 0.007/s y c Indian Academy of Sciences Modelling of capacitance and threshold voltage for ultrathin normally-off AlGaN/GaN MOSHEMT R SWAIN, K JENA and T R LENKA Microelectronics and VLSI Design Group, Department of Electronics & Communication Engineering, National Institute of Technology Silchar, Silchar , India Corresponding author. t.r.lenka@ieee.org; trlenka@ece.nits.ac.in MS received January 05; revised 6 February 06; accepted 6 May 06; published online December 06 Abstract. A compact quantitative model based on oxide semiconductor interface density of states (DOS) is proposed for Al 0.5 Ga 0.75 N/GaN metal oxide semiconductor high electron mobility transistor (MOSHEMT). Mathematical expressions for surface potential, sheet charge concentration, gate capacitance and threshold voltage have been derived. The gate capacitance behaviour is studied in terms of capacitance voltage (CV) characteristics. Similarly, the predicted threshold voltage (V T ) is analysed by varying barrier thickness and oxide thickness. The positive V T obtained for a very thin 3 nm AlGaN barrier layer enables the enhancement mode operation of the MOSHEMT. These devices, along with depletion mode devices, are basic constituents of cascode configuration in power electronic circuits. The expressions developed are used in conventional long-channel HEMT drain current equation and evaluated to obtain different DC characteristics. The obtained results are compared with experimental data taken from literature which show good agreement and hence endorse the proposed model. Keywords. Two-dimensional electron gas; density of state; high electron mobility transistor; metal oxide semiconductor high electron mobility transistor; normally-off; quantum capacitance. PACS Nos 60; 70. Introduction AlGaN/GaN devices are promising candidates for microwave and power electronic applications because of their unique properties such as high two-dimensional electron gas (DEG) density of 0 3 cm,maximum oscillation frequency (f max )of9ghzandoutput power density of 3.65 W mm at 8 GHz []. The DEG concentration in the conventional AlGaN/GaN high electron mobility transistor (HEMT) device plays a vital role [,3] and it has a strong dependence on the Al-content of the AlGaN layer [4]. Scaling of the barrier layer has a risk of increase in gate leakage current, current collapse and hot electron effect [5]. The metal oxide semiconductor high electron mobility transistors (MOSHEMTs) have thin dielectric layers such as Al O 3 [6] under the gate to minimize the leakage current. Very low gate leakage current of 0 Amm is achieved in AlGaN/GaN MOSHEMTs [7]. Charges occupying oxide/algan interface traps, depending upon the position of Fermi energy level, help to deplete the DEG density in the quantum well at AlGaN/GaN interface and hence shift V T towards positive values [8]. MOSHEMT with atomic layer deposition (ALD) of SiO as gate dielectric on 7.5 nm thick Al 0.6 Ga 0.74 N barrier possesses a V T of.5 V with fixed oxide/algan interface charge concentration of.6 0 cm [9]. For Al-mole fraction of 0.5 the critical barrier thickness is around 6 nm for the formation of DEG in the well [0]. Ultrathin subcritical AlGaN barrier layer is ideal for the realization of normally-off (E-mode) devices because thin barrier forms negligible DEG density at zero gate bias (V gs ). With only 3 nm thick Al 0.5 Ga 0.75 N barrier and 0 nm thick SiO layer, V T of 4 V is obtained []. Compact charge-based model for current voltage and capacitance voltage characteristics in AlGaN/GaN HEMTs is presented by considering all the nonideal factors as in refs [,3]. However,

2 3 Page of 7 Pramana J. Phys. (07) 88: 3 there is no suitable model which illustrates the effect of charge trapping at oxide/barrier interface in case of MOSHEMTs. Therefore, our present work focusses on a proper model for MOSHEMTs by considering oxide/ barrier interface DOS to achieve normally-off operation. The organization of this paper is as follows. The model is developed by considering necessary energy band diagrams and HEMT physics in. The MATLABbased simulation results of the developed model are compared graphically with the experimental results from the literature presented in 3. Finally the conclusion has been drawn in 4.. Model development The basic expression for sheet charge concentration in HEMT device is given by [4] n s = σ pol ε AlGaN [φ s + E F (n s ) E C ], () qd AlGaN where σ pol is the total spontaneous and piezoelectric polarization induced charge concentration, ε AlGaN and d AlGaN are permittivity and thickness of AlGaN, q is the charge of the electron, E F (n s ) is the difference between the Fermi level and the bottom of conduction band in GaN layer which is again a function of sheet charge density, φ s is the surface potential and E C is the discontinuity in the conduction band at AlGaN/GaN interface. For enhancement mode device the surface potential φ s can be represented as φ s = φ s0 V gs where φ s0 is the surface potential at zero gate bias. So eq. () becomes n s0 = σ pol ε AlGaN [φ s0 + E F (n s0 ) E C ]. () qd AlGaN. Dependence of n s on oxide/algan interface DOS The oxide/barrier interface energy states are continuous having a charge neutral state (E NL )towardsthe centre. All the levels above this state are acceptor states and levels below it are donor states [5]. As per the definition of Fermi level (E F ) all the levels above it are empty while those below it are filled with electrons. This results in the ionized donor states between E NL and E F while the acceptor states are neutral. Assuming all the states between E NL and E F are ionized, the interface charge is given by Charge concentration = DOS electronic charge energy Q it = D it q(e NL E F ). (3) Here D it represents the interface DOS and Q it represents the interface charge. The barrier depletion charge along with the oxideinterface charge results in a potential drop V ox which can be given by V ox = Q D + Q it, (4) where Q D is the depletion charge and is the oxide capacitance. The depletion charge is formed in the barrier due to the polarization-driven movement of free electrons from the barrier to the triangular quantum well and can be formulated as Q D = qn D d AlGaN, (5) where N D is the unintentional doping concentration in AlGaN barrier. Making use of eqs (3 5) we get V ox = qn Dd AlGaN + D it q(e NL E F ). (6) From figure it can be written as φ s0 = φ M + V ox χ AlGaN and E NL E F = q(φ s0 φ 0 ), where φ M is the work function of the metal, χ AlGaN is the electron affinity for AlGaN and φ 0 is the potential difference between the neutral level and the conduction band edge. Introducing these relations in eq. (6) we get the dependence of surface potential on DOS as in eq. (7). φ s0 = γ(φ M χ AlGaN ) + ( γ)φ 0 γqn Dd AlGaN, (7) where γ = + D it q. / Substituting eq. (7) in eq. () we shall get the DEG sheet charge density at zero gate potential as in eq. (8). n s0 = σ pol ε [ AlGaN γ (φ M χ AlGaN ) + ( γ )φ 0 qd AIGaN γqn ] Dd AlGaN + E F (n s0 ) E C. (8) However, the Fermi level can be expressed as a secondorder expression [6 8], which gives a good fitting to the numerical solution of eq. (8), where E F (n s0 ) is given by E F (n s0 ) = k + k n / s0 + k 3n s0, (9) where k, k and k 3 are constants defined in [6]. Making use of eqs (8) and (9) and solving for n s0 we get [9] n s0 = [ A + A (B + Cφ s0 F)], (0)

3 Pramana J. Phys. (07) 88: 3 Page 3 of 7 3 qv OX Vacuum level qv OX Vacuum level q AlGaN q AlGaN q M q S0 q 0 q M E F E NL C E F (n S) E F q S q 0 E NL C E F (n S ) Metal SiO d AlGaN GaN Metal SiO d AlGaN GaN (a) (b) Figure. Conduction band profile for metal/oxide/algan/gan interface for (a) V g = 0and(b) V g >V T. where ε AlGaN k A = (ε AlGaN k 3 + qd AlGaN ), () B = ε AlGaN(k E C ) (ε AlGaN k 3 + qd AlGaN ), () ε AlGaN C = (ε AlGaN k 3 + qd AlGaN ), (3) d AlGaN qσ pol D = (ε AlGaN k 3 + qd AlGaN ). (4) The DEG charge density at any gate voltage is denoted as n s and can be obtained by replacing φ s0 with φ s + V gs in eq. (0) and can be written as in eq. (5). [ n s = A + A (B + C(φ s + V gs ) D)].. Electric field (5) The near-surface electric field across the barrier can be predicted by [0] E s = q(σ pol n s ), (6) ε AlGaN where n s is a function of the gate voltage..3 Quantum capacitance The total capacitance across the MOSHEMT junction is given by [] as follows: [ ] C eq = + C it + ( ), (7) /C b + /C q where C it is the capacitance due to interface traps, C b is the capacitance due to barrier layer and C q represents the quantum capacitance formed in DEG. If we neglect the variation in interface states and assume that C b is much greater than C q, the total capacitance becomes C eq = C q + C q, (8) where = ε oxide /t oxide and C q = (qn s )/ φ s. Quantum capacitance is formed at the DEG region due to the penetration of Fermi level into the conduction band. It can be obtained by differentiating the sheet charge density with respect to the surface potential as in eq. (9) []. C C q = q.4 Threshold voltage [ A + ] A (B + Cφ s D) A (B + Cφ s D). (9) To make the device off, DEG must be completely depleted (n s = 0). As can be seen in figure, under this condition, E F (n s ) reduces to zero. Putting these conditions in eq. () and replacing φ s with φ s0 + V T where φ s0 is given by eq. (7), the expression for V T can be obtained as in eq. (0). V T = γ(φ M χ AlGaN )+( γ)φ 0 γqn Dd AlGaN E C σ polqd AlGaN ε AlGaN. (0)

4 3 Page 4 of 7 Pramana J. Phys. (07) 88: 3 3. Simulation results and discussion E F S E NL Metal SiO dalgan C GaN Figure. Conduction band at pinch-off. Now C eq and V T from eqs (8) and (0) respectively can be used in drain current equation for HEMT in linear mode [3]. I d,linear = μ GaN C eq ( ) Z [(V gs V T )V ds Vds L ], SD () where μ GaN is the electron mobility in GaN, L SD is the source to drain distance, V ds is the voltage applied between the drain and the source and Z is the width of the channel. Similarly, the saturation mode current equation is given by I d,sat = μ GaN C eq ( ) Z (V gs V T ). () L SD The parameters for AlGaN/GaN heterostructure used for solving the model equations in MATLAB are taken from the existing literatures and indicated in table. Equation (0) is plotted in MATLAB to realize the variation of sheet charge density with respect to barrier thickness at zero gate bias as shown in figure 3. The figure confirms that the minimum barrier thickness beyond which DEG is formed is 6 nm as per ref. [0] and therefore taking 3 nm barrier is subcritical in accordance with ref. []. Further, it can be observed from the figure that for a DEG density of 0 7 m,30 nm thick barrier is required. Similarly, the electric field across AlGaN barrier obtained from eq. (6) is plotted against gate voltage as shown in figure 4. Until threshold voltage is reached, the electric field remains constant at.5 MV cm due to negligible DEG density as compared to polarization charges. Increasing gate voltage beyond threshold voltage increases DEG density at AlGaN/GaN interface, and so there is a linear decay in the electric field and at 3.5 V it becomes zero. Further increase in V g makes the electric field negative due to the accumulation of more negative charges inside the quantum well. In figure 5 the graph of gate capacitance vs. gate voltage is shown. The model results obtained from eqs (8) and (9) are correlated with the experimental results taken from ref. [7] for a device having a gate length of 6 μm. It shows a maximum capacitance of.5 pf across the gate beyond V T. For gate voltage Table. List of model parameters. Parameter Value Unit References ε AlGaN 8.8ε 0 Fm ε oxide 3.9ε 0 Fm k [6] k [6] k [6] σ pol m [4] t oxide 0, 0, 30 nm φ M (Ni) 5. ev χ AlGaN.5 ev φ 0 ev [4] N D 0 m 3 D it.5 0 cm ev [5] E C.4 ev [6] Z/L SD 00 μm/6 μm [] μ GaN 0. m V s Sheet charge Density (x0 m ) AlGaN Barrier Thickness (nm) Figure 3. DEG sheet charge density (n s ) with the variation of AlGaN barrier thickness.

5 Pramana J. Phys. (07) 88: 3 Page 5 of Electric Field (MV/cm) Gate Voltage (V) Figure 4. Electric field across AlGaN/GaN interface with the variation of gate voltage. below V T the capacitance is very small, i.e. 0.9 pf due to negligible sheet charge density. Figure 6 demonstrates the variation of V T with barrier thickness as per eq. (0). It shows a linearly decaying V T with increase in barrier thickness similar to the behaviour obtained in ref. [6]. Due to the unavailability of sufficient experimental data in literature demonstrating the above behaviour for AlGaN/GaN MOSHEMT, comparison with TCAD [8] results is preferred as illustrated in figure 6 showing good agreement. It is observed here that to attain positive V T,very thin barrier below 0 nm is required. This is in good agreement with the argument presented in ref. [0] Figure 6. Variation of threshold voltage with barrier thickness. for a device with barrier having 5% Al content. Barrier thickness of 3 nm and oxide thickness of 0 nm are considered to achieve a V T of.6 V. Figure 7 shows a plot between threshold voltage and oxide thickness. The modelled threshold voltage values are compared with the experimental values taken from ref. [9]. As per the model, V T decreases linearly with increase in oxide thickness which is also evident from experimental results. Finally, the drain current in eqs () and () are plotted with respect to V gs and V ds to obtain I d V gs and I d V ds characteristics respectively. The oxide thickness considered to obtain I d V gs characteristics is 0 nm Figure 5. Gate capacitance with the variation of gate voltage. Figure 7. Threshold voltage variation with oxide thickness.

6 3 Page 6 of 7 Pramana J. Phys. (07) 88: 3 values obtained from the model presented in are appropriate. 4. Conclusion Figure 8. Drain current characteristics with respect to gate voltage for t ox = 0 nm. In this paper, the authors have attempted to establish an analytical model for predicting capacitance and threshold voltage characteristics of ultrathin Al 0.5 Ga 0.75 N/GaN MOSHEMT by developing suitable models for surface potential and sheet charge concentration in the DEG formed at AlGaN/GaN heterointerface. It is evident that a positive V T of.6 V is obtained by decreasing the barrier thickness below the critical value, i.e., 3 nm which leads to normally-off operation of MOSHEMT. The predicted C g V g, I d V gs,andi d V ds characteristics consistently agree with the experimental results available in the literature. and for I d V ds the thickness is 0 nm. The characteristics obtained from the developed models are compared with the respective experimental results taken from ref. [] and are shown in figures 8 and 9. In figure 8 we obtained a threshold voltage of.6 V and drain current of 90 ma mm at V gs = 6Vfor V ds = V. In figure 9 the saturation drain currents of 460 ma mm at V gs = 6 V, 300 ma mm at V gs = 5V,80mAmm at V gs = 4 V are obtained. This also proves that the capacitance and threshold voltage Figure 9. Drain current characteristics with respect to drain voltage for t ox = 0 nm. Acknowledgements The authors acknowledge the Microelectronics Computational Lab in the Department of Electronics & Communication Engineering of National Institute of Technology Silchar, India for providing all necessary facilities to carry out the research work. References [] Z H Feng et al, Electron Device Lett. 3(), 386 (00) [] T R Lenka and A K Panda, Semiconductors 45(9), (0) [3] T R Lenka and A K Panda, Semiconductors 45(5), 660 (0) [4] M Miyoshi, M Sakai, S Arulkumaran, H Ishikawa, T Egawa, M Tanaka and O Oda, Jpn J. Appl. Phys. 43(), 7939 (004) [5] M Higashiwaki, R Chu and U K Mishra, IEEE Trans. Electron Device 58(), 68 (0) [6] P Ye, B Yang, K Ng, J Bude, G Wilk, S Halder and J Hwang, Int. J. High Speed Electron. Systems 4(3), 79 (004) [7] A Colon and J Shi, Solid State Electron. 99, 5 (04) [8] R Swain, J Panda, K Jena and T R Lenka, J. Comput. Electron. 4(03), 754 (05) [9] C J Kirkpatrick et al, Electron Device Lett. 33, 40 (0) [0] A Endoh et al, Jpn J. Appl. Phys. 43(4B), 55 (004) [] R Brown et al, Electron Device Lett. 35(9), 906 (04) [] S Khandelwal and T A Fjeldly, Solid State Electron. 76, 60 (0) [3] F M Yigletu and S Khandelwal, IEEETrans.ElectronDevices 60(), 3746 (03) [4] O Ambacher et al, Appl. Phys. Lett. 85(6), 3 (999) [5] M Tapajna and J Kuzmík, Jpn. J. Appl. Phys. 5, o8jn08-5 (03) [6] S Kola, J M Golio and G N Maracas, IEEE Electron Device Lett. 9(30), 36 (988)

7 Pramana J. Phys. (07) 88: 3 Page 7 of 7 3 [7] M Li and Y Wang, IEEE Trans. Electron Devices 55(), 6 (008) [8] X Cheng, M Li and Y Wang, IEEE Trans. Electron Devices 56(), 88 (009) [9] K Jena, R Swain and T R Lenka, Pramana J. Phys. DOI:0.007/s (05) [0] D Yan, H Lu, D Cao, D Chen, R Zhang and Y Zheng, Appl. Phys. Lett. 97(5), (00) [] D A Deen and J G Champlain, Appl. Phys. Lett. 99, 5350 (0) [] K Jena, R Swain and T R Lenka, J. Semiconductors 36(3), (05) [3] S M Sze, Physics of semiconductor devices, 3rd edn (John Wiley & Sons, 007) [4] J Robertson and B Falabretti, J. Appl. Phys. 00, 04-8 (006) [5] S Arulkumaran, T Egawa and H Ishikawa, Jpn J. Appl. Phys. 44, 8 (005) [6] Z Wang, B Zhang, W Chen and Z Li, IEEE Trans. Electron Devices 60(5), 607 (03) [7] J H Bae, I Hwang, J M Shin, H-I Kwon, C H Park, J Ha, J Lee, H Choi, J Kim, J B Park, J Oh, J Shin, U I Chung and J H Lee, Proceedings of IEEE IEDM, 303 (0) [8] SILVACO, International Incorporated, ATLAS User s Manual, Version 5..0.R. USA, Silvaco inc. (00) [9] R Brown, A Al-Khalidi, D Macfarlane, S Taking, G Ternent, I Thayne and E Wasige, Phys. Status Solidi C, 844 (04)

Impact of oxide thickness on gate capacitance Modelling and comparative analysis of GaN-based MOSHEMTs

Impact of oxide thickness on gate capacitance Modelling and comparative analysis of GaN-based MOSHEMTs PRAMANA c Indian Academy of Sciences Vol. 85, No. 6 journal of December 2015 physics pp. 1221 1232 Impact of oxide thickness on gate capacitance Modelling and comparative analysis of GaN-based MOSHEMTs

More information

AlGaN/GaN-based HEMT on SiC substrate for microwave characteristics using different passivation layers

AlGaN/GaN-based HEMT on SiC substrate for microwave characteristics using different passivation layers PRAMANA c Indian Academy of Sciences Vol. 79, No. 1 journal of July 2012 physics pp. 151 163 AlGaN/GaN-based HEMT on SiC substrate for microwave characteristics using different passivation layers T R LENKA

More information

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS

CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS 98 CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS In this chapter, the effect of gate electrode work function variation on DC

More information

Performance Analysis of. doped and undoped AlGaN/GaN HEMTs

Performance Analysis of. doped and undoped AlGaN/GaN HEMTs Performance Analysis of doped and undoped AlGaN/GaN HEMTs Smitha G S 1, Meghana V 2, Narayan T. Deshpande 3 1 M. Tech Student, ECE, BMS College of Engineering, Bengaluru, Karnataka, India 2B.E. Student,

More information

The physical process analysis of the capacitance voltage characteristics of AlGaN/AlN/GaN high electron mobility transistors

The physical process analysis of the capacitance voltage characteristics of AlGaN/AlN/GaN high electron mobility transistors Chin. Phys. B Vol. 9, No. 9 200 097302 The physical process analysis of the capacitance voltage characteristics of AlGaN/AlN/GaN high electron mobility transistors Wang Xin-Hua, Zhao Miao, Liu Xin-Yu,

More information

Lecture 6: 2D FET Electrostatics

Lecture 6: 2D FET Electrostatics Lecture 6: 2D FET Electrostatics 2016-02-01 Lecture 6, High Speed Devices 2014 1 Lecture 6: III-V FET DC I - MESFETs Reading Guide: Liu: 323-337 (he mainly focuses on the single heterostructure FET) Jena:

More information

MOS CAPACITOR AND MOSFET

MOS CAPACITOR AND MOSFET EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure

More information

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 130 Professor Ali Javey Fall 2006

UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences. EECS 130 Professor Ali Javey Fall 2006 UNIVERSITY OF CALIFORNIA College of Engineering Department of Electrical Engineering and Computer Sciences EECS 130 Professor Ali Javey Fall 2006 Midterm 2 Name: SID: Closed book. Two sheets of notes are

More information

Typical example of the FET: MEtal Semiconductor FET (MESFET)

Typical example of the FET: MEtal Semiconductor FET (MESFET) Typical example of the FET: MEtal Semiconductor FET (MESFET) Conducting channel (RED) is made of highly doped material. The electron concentration in the channel n = the donor impurity concentration N

More information

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor

CMPEN 411 VLSI Digital Circuits. Lecture 03: MOS Transistor CMPEN 411 VLSI Digital Circuits Lecture 03: MOS Transistor Kyusun Choi [Adapted from Rabaey s Digital Integrated Circuits, Second Edition, 2003 J. Rabaey, A. Chandrakasan, B. Nikolic] CMPEN 411 L03 S.1

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 23, 2018 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2018 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes

Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2

More information

Normally-Off GaN Field Effect Power Transistors: Device Design and Process Technology Development

Normally-Off GaN Field Effect Power Transistors: Device Design and Process Technology Development Center for High Performance Power Electronics Normally-Off GaN Field Effect Power Transistors: Device Design and Process Technology Development Dr. Wu Lu (614-292-3462, lu.173@osu.edu) Dr. Siddharth Rajan

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals Bond Model of Electrons and Holes Si Si Si Si Si Si Si Si Si Silicon

More information

Dual-metal-gate Structure of AlGaN/GaN MIS HEMTs Analysis and Design

Dual-metal-gate Structure of AlGaN/GaN MIS HEMTs Analysis and Design Dual-metal-gate Structure of AlGaN/GaN MIS HEMTs Analysis and Design Mr. Gaurav Phulwari 1, Mr. Manish Kumar 2 Electronics & Communication Engineering 1, 2, Bhagwant University, Ajmer 1,2 M.Tech Scholar

More information

Section 12: Intro to Devices

Section 12: Intro to Devices Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

A Bottom-gate Depletion-mode Nanowire Field Effect Transistor (NWFET) Model Including a Schottky Diode Model

A Bottom-gate Depletion-mode Nanowire Field Effect Transistor (NWFET) Model Including a Schottky Diode Model Journal of the Korean Physical Society, Vol. 55, No. 3, September 2009, pp. 1162 1166 A Bottom-gate Depletion-mode Nanowire Field Effect Transistor (NWFET) Model Including a Schottky Diode Model Y. S.

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 2017 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2017 Khanna Lecture Outline! Semiconductor Physics " Band gaps "

More information

Semiconductor Physics Problems 2015

Semiconductor Physics Problems 2015 Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible

More information

Modeling of the Substrate Current and Characterization of Traps in MOSFETs under Sub-Bandgap Photonic Excitation

Modeling of the Substrate Current and Characterization of Traps in MOSFETs under Sub-Bandgap Photonic Excitation Journal of the Korean Physical Society, Vol. 45, No. 5, November 2004, pp. 1283 1287 Modeling of the Substrate Current and Characterization of Traps in MOSFETs under Sub-Bandgap Photonic Excitation I.

More information

EE 560 MOS TRANSISTOR THEORY

EE 560 MOS TRANSISTOR THEORY 1 EE 560 MOS TRANSISTOR THEORY PART 1 TWO TERMINAL MOS STRUCTURE V G (GATE VOLTAGE) 2 GATE OXIDE SiO 2 SUBSTRATE p-type doped Si (N A = 10 15 to 10 16 cm -3 ) t ox V B (SUBSTRATE VOLTAGE) EQUILIBRIUM:

More information

MOS Transistor I-V Characteristics and Parasitics

MOS Transistor I-V Characteristics and Parasitics ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 3, 018 MOS Transistor Theory, MOS Model Lecture Outline! CMOS Process Enhancements! Semiconductor Physics " Band gaps " Field Effects!

More information

ESE 570: Digital Integrated Circuits and VLSI Fundamentals

ESE 570: Digital Integrated Circuits and VLSI Fundamentals ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 29, 2019 MOS Transistor Theory, MOS Model Penn ESE 570 Spring 2019 Khanna Lecture Outline! CMOS Process Enhancements! Semiconductor

More information

MOS Capacitor MOSFET Devices. MOSFET s. INEL Solid State Electronics. Manuel Toledo Quiñones. ECE Dept. UPRM.

MOS Capacitor MOSFET Devices. MOSFET s. INEL Solid State Electronics. Manuel Toledo Quiñones. ECE Dept. UPRM. INEL 6055 - Solid State Electronics ECE Dept. UPRM 20th March 2006 Definitions MOS Capacitor Isolated Metal, SiO 2, Si Threshold Voltage qφ m metal d vacuum level SiO qχ 2 E g /2 qφ F E C E i E F E v qφ

More information

Surfaces, Interfaces, and Layered Devices

Surfaces, Interfaces, and Layered Devices Surfaces, Interfaces, and Layered Devices Building blocks for nanodevices! W. Pauli: God made solids, but surfaces were the work of Devil. Surfaces and Interfaces 1 Interface between a crystal and vacuum

More information

an introduction to Semiconductor Devices

an introduction to Semiconductor Devices an introduction to Semiconductor Devices Donald A. Neamen Chapter 6 Fundamentals of the Metal-Oxide-Semiconductor Field-Effect Transistor Introduction: Chapter 6 1. MOSFET Structure 2. MOS Capacitor -

More information

Analytical Evaluation of Energy and Electron Concentrations in Quantum Wells of the High Electron Mobility Transistors.

Analytical Evaluation of Energy and Electron Concentrations in Quantum Wells of the High Electron Mobility Transistors. Analytical Evaluation of Energy Electron Concentrations in Quantum Wells of the High Electron Mobility Transistors Salih SAYGI Department of Physics, Faculty of Arts Sciences, Gaziosmanpasa University,

More information

Lecture 04 Review of MOSFET

Lecture 04 Review of MOSFET ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D

More information

Influence of structural and doping parameter variations on Si and Si 1 x Ge x double gate tunnel FETs: An analysis for RF performance enhancement

Influence of structural and doping parameter variations on Si and Si 1 x Ge x double gate tunnel FETs: An analysis for RF performance enhancement Pramana J. Phys. (2018) 91:2 https://doi.org/10.1007/s12043-018-1577-2 Indian Academy of Sciences Influence of structural and doping parameter variations on Si and Si 1 x Ge x double gate tunnel FETs:

More information

Quantum Mechanical Simulation for Ultra-thin High-k Gate Dielectrics Metal Oxide Semiconductor Field Effect Transistors

Quantum Mechanical Simulation for Ultra-thin High-k Gate Dielectrics Metal Oxide Semiconductor Field Effect Transistors Mechanical Simulation for Ultra-thin High-k Gate Dielectrics Metal Oxide Semiconductor Field Effect Transistors Shih-Ching Lo 1, Yiming Li 2,3, and Jyun-Hwei Tsai 1 1 National Center for High-Performance

More information

FIELD-EFFECT TRANSISTORS

FIELD-EFFECT TRANSISTORS FIEL-EFFECT TRANSISTORS 1 Semiconductor review 2 The MOS capacitor 2 The enhancement-type N-MOS transistor 3 I-V characteristics of enhancement MOSFETS 4 The output characteristic of the MOSFET in saturation

More information

Appendix 1: List of symbols

Appendix 1: List of symbols Appendix 1: List of symbols Symbol Description MKS Units a Acceleration m/s 2 a 0 Bohr radius m A Area m 2 A* Richardson constant m/s A C Collector area m 2 A E Emitter area m 2 b Bimolecular recombination

More information

M R S Internet Journal of Nitride Semiconductor Research

M R S Internet Journal of Nitride Semiconductor Research Page 1 of 6 M R S Internet Journal of Nitride Semiconductor Research Volume 9, Article 7 The Ambient Temperature Effect on Current-Voltage Characteristics of Surface-Passivated GaN-Based Field-Effect Transistors

More information

MOSFET: Introduction

MOSFET: Introduction E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major

More information

Spring Semester 2012 Final Exam

Spring Semester 2012 Final Exam Spring Semester 2012 Final Exam Note: Show your work, underline results, and always show units. Official exam time: 2.0 hours; an extension of at least 1.0 hour will be granted to anyone. Materials parameters

More information

Semiconductor Physics fall 2012 problems

Semiconductor Physics fall 2012 problems Semiconductor Physics fall 2012 problems 1. An n-type sample of silicon has a uniform density N D = 10 16 atoms cm -3 of arsenic, and a p-type silicon sample has N A = 10 15 atoms cm -3 of boron. For each

More information

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor

Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor Triode Working FET Fundamentals of the Metal Oxide Semiconductor Field-Effect Transistor The characteristics of energy bands as a function of applied voltage. Surface inversion. The expression for the

More information

Self-heating simulation of GaN-based metal-oxide-semiconductor high-electron-mobility transistors including hot electron and quantum effects

Self-heating simulation of GaN-based metal-oxide-semiconductor high-electron-mobility transistors including hot electron and quantum effects JOURNAL OF APPLIED PHYSICS 100, 074501 2006 Self-heating simulation of GaN-based metal-oxide-semiconductor high-electron-mobility transistors including hot electron and quantum effects W. D. Hu, X. S.

More information

Extensive reading materials on reserve, including

Extensive reading materials on reserve, including Section 12: Intro to Devices Extensive reading materials on reserve, including Robert F. Pierret, Semiconductor Device Fundamentals EE143 Ali Javey Bond Model of Electrons and Holes Si Si Si Si Si Si Si

More information

Understanding the effect of n-type and p-type doping in the channel of graphene nanoribbon transistor

Understanding the effect of n-type and p-type doping in the channel of graphene nanoribbon transistor Bull. Mater. Sci., Vol. 39, No. 5, September 2016, pp. 1303 1309. DOI 10.1007/s12034-016-1277-9 c Indian Academy of Sciences. Understanding the effect of n-type and p-type doping in the channel of graphene

More information

! CMOS Process Enhancements. ! Semiconductor Physics. " Band gaps. " Field Effects. ! MOS Physics. " Cut-off. " Depletion.

! CMOS Process Enhancements. ! Semiconductor Physics.  Band gaps.  Field Effects. ! MOS Physics.  Cut-off.  Depletion. ESE 570: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 9, 019 MOS Transistor Theory, MOS Model Lecture Outline CMOS Process Enhancements Semiconductor Physics Band gaps Field Effects

More information

Study of Interface Traps in AlGaN/GaN MISHEMTs Using LPCVD SiN x as Gate Dielectric

Study of Interface Traps in AlGaN/GaN MISHEMTs Using LPCVD SiN x as Gate Dielectric 824 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 64, NO. 3, MARCH 2017 Study of Interface Traps in AlGaN/GaN MISHEMTs Using LPCVD SiN x as Gate Dielectric Xing Lu, Kun Yu, Huaxing Jiang, Anping Zhang, Senior

More information

Lecture 5: CMOS Transistor Theory

Lecture 5: CMOS Transistor Theory Lecture 5: CMOS Transistor Theory Slides courtesy of Deming Chen Slides based on the initial set from David Harris CMOS VLSI Design Outline q q q q q q q Introduction MOS Capacitor nmos I-V Characteristics

More information

Part 4: Heterojunctions - MOS Devices. MOSFET Current Voltage Characteristics

Part 4: Heterojunctions - MOS Devices. MOSFET Current Voltage Characteristics MOS Device Uses: Part 4: Heterojunctions - MOS Devices MOSCAP capacitor: storing charge, charge-coupled device (CCD), etc. MOSFET transistor: switch, current amplifier, dynamic random access memory (DRAM-volatile),

More information

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOSFET N-Type, P-Type. Semiconductor Physics.

Lecture Outline. ESE 570: Digital Integrated Circuits and VLSI Fundamentals. Review: MOSFET N-Type, P-Type. Semiconductor Physics. ESE 57: Digital Integrated Circuits and VLSI Fundamentals Lec 4: January 24, 217 MOS Transistor Theory, MOS Model Lecture Outline! Semiconductor Physics " Band gaps " Field Effects! MOS Physics " Cutoff

More information

Energy position of the active near-interface traps in metal oxide semiconductor field-effect transistors on 4H SiC

Energy position of the active near-interface traps in metal oxide semiconductor field-effect transistors on 4H SiC Energy position of the active near-interface traps in metal oxide semiconductor field-effect transistors on 4H SiC Author Haasmann, Daniel, Dimitrijev, Sima Published 2013 Journal Title Applied Physics

More information

This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented.

This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. References IEICE Electronics Express, Vol.* No.*,*-* Effects of Gamma-ray radiation on

More information

Electrical Characteristics of Multilayer MoS 2 FET s

Electrical Characteristics of Multilayer MoS 2 FET s Electrical Characteristics of Multilayer MoS 2 FET s with MoS 2 /Graphene Hetero-Junction Contacts Joon Young Kwak,* Jeonghyun Hwang, Brian Calderon, Hussain Alsalman, Nini Munoz, Brian Schutter, and Michael

More information

Electrical measurements of voltage stressed Al 2 O 3 /GaAs MOSFET

Electrical measurements of voltage stressed Al 2 O 3 /GaAs MOSFET Microelectronics Reliability xxx (2007) xxx xxx www.elsevier.com/locate/microrel Electrical measurements of voltage stressed Al 2 O 3 /GaAs MOSFET Z. Tang a, P.D. Ye b, D. Lee a, C.R. Wie a, * a Department

More information

Analytic Model for Photo-Response of p-channel MODFET S

Analytic Model for Photo-Response of p-channel MODFET S Journal of the Korean Physical Society, Vol. 42, February 2003, pp. S642 S646 Analytic Model for Photo-Response of p-channel MODFET S Hwe-Jong Kim, Ilki Han, Won-Jun Choi, Young-Ju Park, Woon-Jo Cho and

More information

Lecture #27. The Short Channel Effect (SCE)

Lecture #27. The Short Channel Effect (SCE) Lecture #27 ANNOUNCEMENTS Design Project: Your BJT design should meet the performance specifications to within 10% at both 300K and 360K. ( β dc > 45, f T > 18 GHz, V A > 9 V and V punchthrough > 9 V )

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

Dynamic On-resistance and Tunneling Based De-trapping in GaN HEMT

Dynamic On-resistance and Tunneling Based De-trapping in GaN HEMT MITSUBISHI ELECTRIC RESEARCH LABORATORIES http://www.merl.com Dynamic On-resistance and Tunneling Based De-trapping in GaN HEMT Zhu, L.; Teo, K.H.; Gao, Q. TR2015-047 June 2015 Abstract GaN HEMT dynamic

More information

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions

P. R. Nelson 1 ECE418 - VLSI. Midterm Exam. Solutions P. R. Nelson 1 ECE418 - VLSI Midterm Exam Solutions 1. (8 points) Draw the cross-section view for A-A. The cross-section view is as shown below.. ( points) Can you tell which of the metal1 regions is the

More information

Characteristics and parameter extraction for NiGe/n-type Ge Schottky diode with variable annealing temperatures

Characteristics and parameter extraction for NiGe/n-type Ge Schottky diode with variable annealing temperatures 034 Chin. Phys. B Vol. 19, No. 5 2010) 057303 Characteristics and parameter extraction for NiGe/n-type Ge Schottky diode with variable annealing temperatures Liu Hong-Xia ), Wu Xiao-Feng ), Hu Shi-Gang

More information

Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007

Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007 6.720J/3.43J - Integrated Microelectronic Devices - Spring 2007 Lecture 29-1 Lecture 29 - The Long Metal-Oxide-Semiconductor Field-Effect Transistor (cont.) April 20, 2007 Contents: 1. Non-ideal and second-order

More information

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.

Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices. Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

Investigation of Buffer Traps in AlGaN/GaN Heterostructure Field-Effect Transistors Using a Simple Test Structure

Investigation of Buffer Traps in AlGaN/GaN Heterostructure Field-Effect Transistors Using a Simple Test Structure http://dx.doi.org/10.5573/jsts.2014.14.4.478 JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, VOL.14, NO.4, AUGUST, 2014 Investigation of Buffer Traps in AlGaN/GaN Heterostructure Field-Effect Transistors

More information

POLARIZATION INDUCED EFFECTS IN AlGaN/GaN HETEROSTRUCTURES

POLARIZATION INDUCED EFFECTS IN AlGaN/GaN HETEROSTRUCTURES Vol. 98 (2000) ACTA PHYSICA POLONICA A No. 3 Proceedings of the XXIX International School of Semiconducting Compounds, Jaszowiec 2000 POLARIZATION INDUCED EFFECTS IN AlGaN/GaN HETEROSTRUCTURES O. AMBACHER

More information

ECE-305: Fall 2017 MOS Capacitors and Transistors

ECE-305: Fall 2017 MOS Capacitors and Transistors ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue

More information

Strain and Temperature Dependence of Defect Formation at AlGaN/GaN High Electron Mobility Transistors on a Nanometer Scale

Strain and Temperature Dependence of Defect Formation at AlGaN/GaN High Electron Mobility Transistors on a Nanometer Scale Strain and Temperature Dependence of Defect Formation at AlGaN/GaN High Electron Mobility Transistors on a Nanometer Scale Chung-Han Lin Department of Electrical & Computer Engineering, The Ohio State

More information

EECS130 Integrated Circuit Devices

EECS130 Integrated Circuit Devices EECS130 Integrated Circuit Devices Professor Ali Javey 10/02/2007 MS Junctions, Lecture 2 MOS Cap, Lecture 1 Reading: finish chapter14, start chapter16 Announcements Professor Javey will hold his OH at

More information

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region

EE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel

More information

Threshold voltage shift of heteronanocrystal floating gate flash memory

Threshold voltage shift of heteronanocrystal floating gate flash memory JOURNAL OF APPLIED PHYSICS 97, 034309 2005 Threshold voltage shift of heteronanocrystal floating gate flash memory Yan Zhu, Dengtao Zhao, Ruigang Li, and Jianlin Liu a Quantum Structures Laboratory, Department

More information

Device Models (PN Diode, MOSFET )

Device Models (PN Diode, MOSFET ) Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed

More information

Role of Electrochemical Reactions in the Degradation Mechanisms of AlGaN/GaN HEMTs

Role of Electrochemical Reactions in the Degradation Mechanisms of AlGaN/GaN HEMTs Role of Electrochemical Reactions in the Degradation Mechanisms of AlGaN/GaN HEMTs Feng Gao 1,2, Bin Lu 2, Carl V. Thompson 1, Jesús del Alamo 2, Tomás Palacios 2 1. Department of Materials Science and

More information

MOS Transistor Theory

MOS Transistor Theory MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors

More information

Switching characteristics of lateral-type and vertical-type SiC JFETs depending on their internal parasitic capacitances

Switching characteristics of lateral-type and vertical-type SiC JFETs depending on their internal parasitic capacitances Switching characteristics of lateral-type and vertical-type SiC JFETs depending on their internal parasitic capacitances Nathabhat Phankong 1a), Tsuyoshi Funaki 2, and Takashi Hikihara 1 1 Kyoto University,

More information

JFET/MESFET. JFET: small gate current (reverse leakage of the gate-to-channel junction) More gate leakage than MOSFET, less than bipolar.

JFET/MESFET. JFET: small gate current (reverse leakage of the gate-to-channel junction) More gate leakage than MOSFET, less than bipolar. JFET/MESFET JFET: small gate current (reverse leakage of the gate-to-channel junction) More gate leakage than MOSFET, less than bipolar. JFET has higher transconductance than the MOSFET. Used in low-noise,

More information

Long Channel MOS Transistors

Long Channel MOS Transistors Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended to Metal-Oxide-Semiconductor Field-Effect transistors (MOSFET) by considering the following structure:

More information

Practice 3: Semiconductors

Practice 3: Semiconductors Practice 3: Semiconductors Digital Electronic Circuits Semester A 2012 VLSI Fabrication Process VLSI Very Large Scale Integration The ability to fabricate many devices on a single substrate within a given

More information

MOS Transistor Theory

MOS Transistor Theory CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS

More information

(a) (b) Supplementary Figure 1. (a) (b) (a) Supplementary Figure 2. (a) (b) (c) (d) (e)

(a) (b) Supplementary Figure 1. (a) (b) (a) Supplementary Figure 2. (a) (b) (c) (d) (e) (a) (b) Supplementary Figure 1. (a) An AFM image of the device after the formation of the contact electrodes and the top gate dielectric Al 2 O 3. (b) A line scan performed along the white dashed line

More information

Lecture 4: CMOS Transistor Theory

Lecture 4: CMOS Transistor Theory Introduction to CMOS VLSI Design Lecture 4: CMOS Transistor Theory David Harris, Harvey Mudd College Kartik Mohanram and Steven Levitan University of Pittsburgh Outline q Introduction q MOS Capacitor q

More information

Electrical Characteristics of MOS Devices

Electrical Characteristics of MOS Devices Electrical Characteristics of MOS Devices The MOS Capacitor Voltage components Accumulation, Depletion, Inversion Modes Effect of channel bias and substrate bias Effect of gate oide charges Threshold-voltage

More information

GaN based transistors

GaN based transistors GaN based transistors S FP FP dielectric G SiO 2 Al x Ga 1-x N barrier i-gan Buffer i-sic D Transistors "The Transistor was probably the most important invention of the 20th Century The American Institute

More information

MOS Capacitors ECE 2204

MOS Capacitors ECE 2204 MOS apacitors EE 2204 Some lasses of Field Effect Transistors Metal-Oxide-Semiconductor Field Effect Transistor MOSFET, which will be the type that we will study in this course. Metal-Semiconductor Field

More information

Schottky Rectifiers Zheng Yang (ERF 3017,

Schottky Rectifiers Zheng Yang (ERF 3017, ECE442 Power Semiconductor Devices and Integrated Circuits Schottky Rectifiers Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Power Schottky Rectifier Structure 2 Metal-Semiconductor Contact The work function

More information

1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00

1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00 1 Name: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND Final Exam Physics 3000 December 11, 2012 Fall 2012 9:00-11:00 INSTRUCTIONS: 1. Answer all seven (7) questions.

More information

Traps in MOCVD n-gan Studied by Deep Level Transient Spectroscopy and Minority Carrier Transient Spectroscopy

Traps in MOCVD n-gan Studied by Deep Level Transient Spectroscopy and Minority Carrier Transient Spectroscopy Traps in MOCVD n-gan Studied by Deep Level Transient Spectroscopy and Minority Carrier Transient Spectroscopy Yutaka Tokuda Department of Electrical and Electronics Engineering, Aichi Institute of Technology,

More information

EE5311- Digital IC Design

EE5311- Digital IC Design EE5311- Digital IC Design Module 1 - The Transistor Janakiraman V Assistant Professor Department of Electrical Engineering Indian Institute of Technology Madras Chennai October 28, 2017 Janakiraman, IITM

More information

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA

MOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing

More information

AS MOSFETS reach nanometer dimensions, power consumption

AS MOSFETS reach nanometer dimensions, power consumption 1 Analytical Model for a Tunnel Field-Effect Transistor Abstract The tunnel field-effect transistor (TFET) is a promising candidate for the succession of the MOSFET at nanometer dimensions. Due to the

More information

EE105 - Fall 2006 Microelectronic Devices and Circuits

EE105 - Fall 2006 Microelectronic Devices and Circuits EE105 - Fall 2006 Microelectronic Devices and Circuits Prof. Jan M. Rabaey (jan@eecs) Lecture 7: MOS Transistor Some Administrative Issues Lab 2 this week Hw 2 due on We Hw 3 will be posted same day MIDTERM

More information

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002

The Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002 Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction

More information

Supporting information

Supporting information Supporting information Design, Modeling and Fabrication of CVD Grown MoS 2 Circuits with E-Mode FETs for Large-Area Electronics Lili Yu 1*, Dina El-Damak 1*, Ujwal Radhakrishna 1, Xi Ling 1, Ahmad Zubair

More information

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model

Today s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model - Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next

More information

Subthreshold and scaling of PtSi Schottky barrier MOSFETs

Subthreshold and scaling of PtSi Schottky barrier MOSFETs Superlattices and Microstructures, Vol. 28, No. 5/6, 2000 doi:10.1006/spmi.2000.0954 Available online at http://www.idealibrary.com on Subthreshold and scaling of PtSi Schottky barrier MOSFETs L. E. CALVET,

More information

V t vs. N A at Various T ox

V t vs. N A at Various T ox V t vs. N A at Various T ox Threshold Voltage, V t 0.9 0.8 0.7 0.6 0.5 0.4 T ox = 5.5 nm T ox = 5 nm T ox = 6 nm m = 4.35 ev, Q ox = 0; V sb = 0 V 0.3 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 Body Doping, N

More information

Frequency dispersion effect and parameters. extraction method for novel HfO 2 as gate dielectric

Frequency dispersion effect and parameters. extraction method for novel HfO 2 as gate dielectric 048 SCIENCE CHINA Information Sciences April 2010 Vol. 53 No. 4: 878 884 doi: 10.1007/s11432-010-0079-8 Frequency dispersion effect and parameters extraction method for novel HfO 2 as gate dielectric LIU

More information

Department of Electronic Engineering, Chienkuo Technology University, No. 1, Chieh Shou N. Rd., Changhua City, 500 Taiwan, R.O.C.

Department of Electronic Engineering, Chienkuo Technology University, No. 1, Chieh Shou N. Rd., Changhua City, 500 Taiwan, R.O.C. Typeset using jjap.cls Compact Hot-Electron Induced Oxide Trapping Charge and Post- Stress Drain Current Modeling for Buried-Channel p-type Metal- Oxide-Semiconductor-Field-Effect-Transistors

More information

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University

SECTION: Circle one: Alam Lundstrom. ECE 305 Exam 5 SOLUTIONS: Spring 2016 April 18, 2016 M. A. Alam and M.S. Lundstrom Purdue University NAME: PUID: SECTION: Circle one: Alam Lundstrom ECE 305 Exam 5 SOLUTIONS: April 18, 2016 M A Alam and MS Lundstrom Purdue University This is a closed book exam You may use a calculator and the formula

More information

Semiconductor Devices. C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5

Semiconductor Devices. C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5 Semiconductor Devices C. Hu: Modern Semiconductor Devices for Integrated Circuits Chapter 5 Global leader in environmental and industrial measurement Wednesday 3.2. afternoon Tour around facilities & lecture

More information

Figure 3.1 (p. 141) Figure 3.2 (p. 142)

Figure 3.1 (p. 141) Figure 3.2 (p. 142) Figure 3.1 (p. 141) Allowed electronic-energy-state systems for two isolated materials. States marked with an X are filled; those unmarked are empty. System 1 is a qualitative representation of a metal;

More information

Lecture 12: MOSFET Devices

Lecture 12: MOSFET Devices Lecture 12: MOSFET Devices Gu-Yeon Wei Division of Engineering and Applied Sciences Harvard University guyeon@eecs.harvard.edu Wei 1 Overview Reading S&S: Chapter 5.1~5.4 Supplemental Reading Background

More information

Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.)

Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.) Lecture 7 PN Junction and MOS Electrostatics(IV) Metal Oxide Semiconductor Structure (contd.) Outline 1. Overview of MOS electrostatics under bias 2. Depletion regime 3. Flatband 4. Accumulation regime

More information

ECE 305: Fall MOSFET Energy Bands

ECE 305: Fall MOSFET Energy Bands ECE 305: Fall 2016 MOSFET Energy Bands Professor Peter Bermel Electrical and Computer Engineering Purdue University, West Lafayette, IN USA pbermel@purdue.edu Pierret, Semiconductor Device Fundamentals

More information

META-STABILITY EFFECTS IN ORGANIC BASED TRANSISTORS

META-STABILITY EFFECTS IN ORGANIC BASED TRANSISTORS META-STABILITY EFFECTS IN ORGANIC BASED TRANSISTORS H. L. Gomes 1*, P. Stallinga 1, F. Dinelli 2, M. Murgia 2, F. Biscarini 2, D. M. de Leeuw 3 1 University of Algarve, Faculty of Sciences and Technology

More information

Electrostatics of Nanowire Transistors

Electrostatics of Nanowire Transistors Electrostatics of Nanowire Transistors Jing Guo, Jing Wang, Eric Polizzi, Supriyo Datta and Mark Lundstrom School of Electrical and Computer Engineering Purdue University, West Lafayette, IN, 47907 ABSTRACTS

More information