Influence of structural and doping parameter variations on Si and Si 1 x Ge x double gate tunnel FETs: An analysis for RF performance enhancement

Transcription

1 Pramana J. Phys. (2018) 91:2 Indian Academy of Sciences Influence of structural and doping parameter variations on Si and Si 1 x Ge x double gate tunnel FETs: An analysis for RF performance enhancement S POORVASHA and B LAKSHMI School of Electronics Engineering, VIT University, Chennai , India Corresponding author. lakshmi.b@vit.ac.in MS received 9 August 2017; revised 16 November 2017; accepted 2 January 2018; published online 25 May 2018 Abstract. This paper deals with the effect of structural and doping parameter variations on RF parameters for Si and Si 1 x Ge x -based double gate (DG) tunnel FETs (TFETs). For the first time, asymmetric gate oxide is introduced in the gate-drain overlap and compared with that of DG TFETs. The DC parameter subthreshold swing (SS) and RF parameter metrics, unity gain cut-off frequency ( f t ) and maximum oscillation frequency ( f max ) are extracted by varying structural parameters, gate length (L g ), gate oxide thickness (t ox ), channel thickness (t ch ), doping parameters, channel doping (N ch ), drain doping (N d ) and source doping (N s ) in and around their nominal value. For a channel thickness of 15 nm, a very less SS of 8 mv/dec is achieved in Si 1 x Ge x -based DG TFETs with gate-drain overlap. Variations of gate oxide thickness offer better RF performance enhancement for Si-based asymmetric gate oxide devices. This could be achieved because of the higher tunnelling rate of electrons occurring at the source side of asymmetric gate oxide devices. Keywords. Double gate tunnel FETs; gate-drain overlap; subthreshold swing; unity gain cut-off frequency; maximum oscillation frequency; TCAD. PACS No Introduction Many novel devices have been reported from the aspect of eradicating the major issues of CMOS technology involving high leakage current (I OFF ), high power consumption and non-scalability of subthreshold swing (SS). Tunnel field effect transistor (TFET), being one such novel device, involves band band tunnelling as their principal mechanism which offers low SS, I OFF and threshold voltage (V t )[1 3]. In terms of improved on-current (I ON ), low threshold voltage and RF characteristics, double gate TFETs (DG TFETs) are found to be superior to single gate TFETs (SG TFETs) [4 7]. But still the practical usage of TFETs is delayed due to low I ON and ambipolar behaviour [8]. TFETs with lower band-gap materials such as silicon germanium (SiGe) are used to enhance I ON [9 12]. It has been reported that the ambipolar behaviour affecting the TFET performance can be reduced by using gatedrain overlap in DG TFET device structure [13]. In this paper, Si- and SiGe-based TFETs are compared with their structural and doping parameter variations. The study is carried out by extracting the DC parameter, subthreshold swing (SS) and RF parameters, unity gain cut-off frequency ( f t ) and maximum oscillation frequency ( f max ) for both the devices. Section 2 presents the Si- and SiGe-based DG TFET device structures and the simulation methodology. The results and discussions are given in 3 and finally 4 provides the conclusion. 2. Device structure and simulation methodology All the simulations are carried out using technology CAD (TCAD) simulator from Synopsys [14]. Figures 1a and 1b depict the two-dimensional structure of Si-based DG TFET and DG TFET with gate-drain overlap respectively. Figures 2aand2b show the structure of Si 1 x Ge x with the mole fraction of (x) based DG TFET devices. The schematic of DG TFET with gate-drain overlap is shown in figure 3.Table1 provides the parameter space for DG TFETs. In this study, 1 V is the supply voltage and 1.8 V is the gate voltage.

2 2 Page 2 of 8 Pramana J. Phys. (2018) 91:2 Figure 1. Structure of Si-based DG TFET and DG TFET with gate-drain overlap. Figure 3. Schematic of DG TFET with gate-drain overlap. simulator. Proper tuning of the gate and gate-drain overlap work function are performed to obtain optimised I ON with matched I OFF for DG TFETs with gate-drain overlap. The device is calibrated against the published results [4]. From our previous work, the mole fraction (x) of Si 1 x Ge x is optimised to 0.4 which offers more I ON and least I OFF [15]. Figure 4 depicts the I d V g characteristics of Si- and Si 1 x Ge x -based DG TFETs and DG TFETs with gate-drain overlap. As mentioned earlier, for all the devices described in this study, I OFF matching is done by proper work function tuning. It is evident from the plot that Si 1 x Ge x -based DG TFETs with gatedrain overlap offers higher I ON and lower SS compared to Si-based devices. The subthreshold swing of the device is expressed as Figure 2. Structure of Si 1 x Ge x -based DG TFET and DG TFET with gate-drain overlap. In addition to doping-dependent mobility, effects of high and normal electric fields on mobility and velocity saturation model, non-local Hurkx band-to-band tunnelling, Fermi Dirac statistics and Shockley Read Hall recombination model are also included in the device SS = dv g (mv/dec). (1) d(log I d ) Figure 5 shows SS for varying gate voltage for all the nominal devices whose I OFF values are matched. SS is extracted for the gate voltages ranging from 0.6 V because gate-induced drain leakage (GIDL) is observed below 0.6 V. It can be observed from figure 5 that SS for DG TFET with gate-drain overlap performs better with respect to DG TFET without gate-drain overlap for both Si and Si 1 x Ge x.

3 Pramana J. Phys. (2018) 91:2 Page 3 of 8 2 Table 1. Parameter space for DG TFETs. Parameters Nominal value Range of values Gate length (L g ) 50 nm nm Gate oxide thickness (t ox ) 3 nm 1 5 nm Channel thickness (t ch ) 10 nm 5 15 nm Channel doping concentration (N ch ) 1e17cm 3 1e15 1e19 cm 3 Drain doping concentration (N d ) 5e18cm 3 5e17 1e20 cm 3 Source doping concentration (N s ) 1e20 cm 3 5e19 8e20 cm 3 Figure 4. I d V g characteristics of Si- and Si 1 x Ge x -based DG TFETs without gate-drain overlap and DG TFETs with gate-drain overlap with I OFF matched to 14.5 fa/μm. From (1), SS of TFET can be written as [ 1 dv eff SS = ln 10 + E + b ] de 1 V eff dv g E 2, (2) dv g where E is the electric field and b is the coefficient determined by the material properties of the junction and cross-sectional area of the device. It can be seen that the gate bias (V g ) is controlling over the tunnelling junction bias (V eff ) which results in lower values of SS for decreased values of V g. This result is in line with those of the results reported earlier [4,16,17]. The two important RF metrics, unity gain cut-off frequency ( f t ) and maximum oscillation frequency ( f max ), are extracted for the above-mentioned devices. f t is defined as the frequency at which current gain equals to one and in terms of device parameters, it is expressed as f t = g m, (3) 2πC gg where g m is the transconductance, C gg is given as the sum of C gs and C gd (C gd is the gate-to-drain intrinsic capacitance, C gs is the gate-to-source intrinsic capacitance). Figure 5. SS vs. V g. f max is defined as the frequency at which power gain drops to unity and can be expressed as f max = f t 4Rg (g ds + 2π f t C gd ), (4) where R g is the gate resistance and g ds is the output conductance. The structural and doping parameters of DG TFET without gate-drain overlap and DG TFET with gatedrain overlap for the nominal device is taken into consideration as per table 1 with I OFF matched to 14.5 fa/μm. All the four devices are compared with respect to I ON, SS, f t and f max and the results are given in table 2. Aspertable2, Si 1 x Ge x -based DG TFET with gate-drain overlap performs better than that of DG TFET without gate-drain overlap in terms of I ON,SS and f t. 3. Results and discussion The structural parameters (gate length (L g ), gate oxide thickness (t ox ), channel thickness (t ch )) and doping parameters (channel doping (N ch ), drain doping (N d )

4 2 Page 4 of 8 Pramana J. Phys. (2018) 91:2 Table 2. Comparison between DG TFET with gate-drain overlap and DG TFET. Parameters DG TFET with gate-drain overlap DG TFET without gate-drain overlap Si 1 x Ge x Si Si 1 x Ge x Si I OFF (fa/μm) I ON (μa/μm) SS (mv/dec) f t (GHz) f max (GHz) Figure 6. SS vs. L g. and source doping (N s )) are varied as shown in table 1 to extract SS, f t and f max. 3.1 Variation in gate length (L g ) The variation of SS against gate length (L g )isshown in figure 6. It can be observed from the plot that SS decreases with increasing L g. This can be attributed to the reduction in short channel effects (SCEs) for larger gate lengths [18,19]. Figure 7 gives the plot of the variation of f t and f max against gate length (L g ). It can be seen from the graph that f t decreases with increasing L g. f t is decided by both g m and C gg.asl g is scaled down, g m increases whereas C gg remains almost constant resulting in increased f t. [20]. It has been observed that Si-based DG TFETs with gate-drain overlap offers better f t compared to DG TFETs without gate-drain overlap due to the drastic increase of g m found in DG TFETs with gatedrain overlap. This result is valid for Si 1 x Ge x based devices also due to the reasons discussed earlier. It can also be observed from the plot that f max decreases with increasing L g. The increase in f max is due to the reduced channel resistance and parasitic capacitance C gd for smaller gate lengths [21]. Both Si and Si 1 x Ge x -based Figure 7. f t and f max vs. L g. DG TFETs with gate-drain overlap have comparatively lesser values of f max due to larger values of g ds [22]. 3.2 Variation in gate oxide thickness (t ox ) Figure 8 shows the variation of SS against t ox. It can be noticed from the graph that SS increases for values below 4 nm. For very lesser values of t ox, gate leakage occurs due to gate tunnelling and hence SS is increased. Figure 9 shows the variation of f t and f max against t ox. It can be seen that f t increases for lower values of t ox. g m increases with decreasing t ox because of the increase in vertical gate electric field which ultimately enhances f t [23]. This result is observed for both Si and Si 1 x Ge x - based devices. It is observed from the graph that f max decreases with increasing t ox. Higher values of f max are achieved due to degradation of channel resistance and output conductance as discussed earlier. 3.3 Variation in channel thickness (t ch ) Figure 10 shows the SS variation for the values of t ch as mentioned in table 1. It can be observed that SS decreases upto t ch = 12 nm for both Si and Si 1 x Ge x - based DG TFET devices. This result is on par with the

5 Pramana J. Phys. (2018) 91:2 Page 5 of 8 2 Figure 8. SS vs. t ox. Figure 10. SS vs. t ch. Figure 9. f t and f max vs. t ox. Figure 11. f t and f max vs. t ch. already published results [24,25]. For Si 1 x Ge x -based DG TFET with gate-drain overlap, SS still decreases upto t ch = 15 nm giving a least SS of 8 mv/dec. Figure 11 shows the f t and f max variation with respect to t ch variation. It can be observed that f t increases with the downscaling of t ch. For lower values of t ch, I ON increases, thereby g m increases which ultimately improves f t. Comparatively, the gate capacitance values are lower and hence the values of f t are more with the decrease in t ch and this may be reasoned out due to the screening of gate fringing fields [26]. As discussed earlier, f max follows the same trend of f t for all the devices. 3.4 Variation in channel doping (N ch ) Figure 12 shows the variation of SS against channel doping (N ch ). It can be noticed from the plot that SS remains Figure 12. SS vs. N ch. more or less constant up to N ch = 1e18/cm 3 and thereafter it increases. This is due to the better gate control over the channel for lesser doping concentration [18].

6 2 Page 6 of 8 Pramana J. Phys. (2018) 91:2 Comparatively, it can be found that DG TFETs with gate-drain overlap shows less values of SS. Figure 13 shows the variation of f t and f max against channel doping (N ch ). The graph shows that both f t and f max are almost insensitive for lesser concentration of channel doping and start to decrease after N ch = 1e18/cm 3. This can be reasoned out because of g m degradation f t decreases for higher doping levels [27]. 3.5 Variation in drain doping (N d ) Figure 13. f t and f max vs. N ch. Figure 14 showsthe variationof SS withrespectto drain doping (N d ). The graph shows an increase in SS after a doping concentration of N d = 1e19/cm 3. This may be attributed to the increase in electron density for higher doping levels which ultimately decreases the threshold voltage (V t ). This is evident from figure 15. Due to this reduction in threshold voltage, SS increases because gate loses control over the channel. Figure 16 shows f t and f max variations for various values of drain doping (N d ). For all the devices mentioned, f t increases because of the increase in g m for higher doping levels. For DG TFETs with gate-drain overlap, f max shows an increasing trend for all values of N d whereas DG TFETs without gate-drain overlap exhibit an increase in f max after the doping concentration of N d = 1e19/cm Variation in source doping (N s ) Figure 14. SS vs. N d. Figure 17 depicts the variation of SS with respect to source doping (N s ). It can be noted that SS gives a least value for N s = 1e20/cm 3 for all the devices. Since source is of p-type material, electron density gets Figure 15. Density for the two drain doping concentrations of Si-based DG TFET.

7 Pramana J. Phys. (2018) 91:2 Page 7 of 8 2 N s = 5e20/cm 3 and thereafter decrease due to the increase in transconductance. 4. Conclusion Figure 16. f t and f max vs. N d. In this work, four different devices of DG TFETs are studied using TCAD simulations. An asymmetric gate oxide is introduced on gate-drain overlap of Si and Si 1 x Ge x -based DG TFETs and its RF performance is compared with that of DG TFETs without gatedrain overlap. The structural parameters, L g, t ox, t ch and doping parameters, N ch, N d, N s are varied for all the devices. It can be found that the variation in the structural parameters, t ox and t ch,offersmorerfperformance enhancement rather than the variation of doping parameters. This enhancement in RF performance is particularly observed in DG TFETs with gate-drain overlap devices. Hence, DG TFETs with gate-drain overlap is considered to be superior to that of DG TFETs without gate-drain overlap and it seems to be a promising candidate for future RF/analog or mixed signal circuit applications. Acknowledgements This work is supported by the Department of Science and Technology, Government of India under SERB scheme Grant No. SERB/F/2660. Figure 17. SS vs. N s. Figure 18. f t and f max vs. N s. decreased for a higher doping source concentration and hence V t decreases resulting in higher SS. Figure 18 shows the variation of f t and f max for different values of source doping (N s ). It can be observed that for all the devices, both f t and f max increase upto References [1] Y Khatami and K Banerjee, IEEE Trans. Electron Devices 56, 2752 (2009) [2] P S Gupta, S Kanungo, H Rahaman, K Sinha and P S Dasgupta, Int. J. Appl. Phys. Math. 2, 240 (2012) [3] A C Seabaugh and Q Zhang, Proc. IEEE 98, 2095 (2010) [4] K Boucart and A M Ionescu, IEEE Trans. Electron Devices 54, 1725 (2007) [5] K-F Lee et al, NSTI Nanotechnol. 2, 65 (2010) [6] L Zhang, M Chan and F He, IEEE International Conference on Electron Devices and Solid-State Circuits (Hong Kong, 2010) p. 1 [7] S M Razavi, S H Zahiri and S E Hosseini, Pramana J. Phys. 88, 58 (2017) [8] A Hraziia, C Andrei, A Vladimirescu, A Amara and C Anghel, Solid State Electron. 70, 67 (2012) [9] E-H Toh, G H Wang, L Chan, D Sylvester, C-H Heng, G S Samudra and Y-C Leo, Jpn. J. Appl. Phys. 47, 2593 (2008) [10] Q T Zhao, J M Hartmann and S Mantl, IEEE Electron. Device Lett. 32, 1480 (2011)

8 2 Page 8 of 8 Pramana J. Phys. (2018) 91:2 [11] H W Kim, J H Kim, S W Kim, M-C Sun, E Park and B-G Park, Jpn. J. Appl. Phys. 53, Article ID 06JE12-1 (2014) [12] S Richter et al, Solid State Electron. 98, 75 (2014) [13] D B Abdi and M J Kumar, J. Electron Device Soc. 2, 187 (2014) [14] Synopsys Sentaurus Device User Guide version J [15] S Poorvasha and B Lakshmi, International Conference on VLSI Systems, Architectures, Technology and Applications (2016) [16] Y Zhu and M K Hudait, Nanotechnol. Rev. 2, 637 (2013) [17] P Chaturvedi and M J Kumar, Jpn. J. Appl. Phys. 53, Article No (2014) [18] G Rawat, S Kumar, E Goel, M Kumar1, S Dubey and S Jit, J. Semicond. 35, (2014) [19] N B Balamurugan, K Sankaranarayanan, P Amutha and M F John, J. Semicond. Technol. Sci. 8, 221(2008) [20] S Cho, J S Lee, K R Kim, B-G Park, J S Harris and I M Kang, IEEE Trans. Electron Devices 58, 4164 (2011) [21] V Vijayvargiya and S K Vishvakarma, IEEE Trans. Nanotechnol. 13, 974 (2014) [22] J Mo, E Lind and L E Wernersson, IEEE Electron Device Lett. 35, 515 (2014) [23] Sushant S Suryagandh, Mayank Garg, M Gupta, Jason C S Woo, International Conference on Solid-state and Integrated Circuits Technology, Vol. 1, p. 153 (2004). [24] J Y Song, W Y Choi, J H Park, J D Lee and B-G Park, IEEE Trans. Nanotechnol. 5, 186 (2006) [25] T A Bhat, M Mustafa and M R Beigh, J. Nano Electron. Phys. 7, Article No (2015) [26] A Nandi, A K Saxena and S Dasgupta, IEEE Trans. Electron Devices 60, 1529 (2013) [27] B Lakshmi and R Srinivasan, Int. J. VLSI Design Commun. Syst. 1, 36 (2010)