CHAPTER 2 AN OVERVIEW OF TCAD SIMULATOR AND SIMULATION METHODOLOGY
|
|
- Leona Cobb
- 6 years ago
- Views:
Transcription
1 15 CHAPTER 2 AN OVERVIEW OF TCAD SIMULATOR AND SIMULATION METHODOLOGY In this chapter TCAD and the various modules available in the TCAD simulator have been discussed. The simulation methodologies to extract DC parameters, V T, I ON, I OFF and R o and AC parameters, f t, NQS delay, intrinsic gain and NF have also been discussed. Sensitivity analysis and screening experiment method which are used to rank the parameters are discussed in detail. 2.1 INTRODUCTION Technology CAD (TCAD) refers to using computer simulations to develop and optimize semiconductor processing technologies and devices. TCAD simulation tools solve fundamental, physical partial differential equations, such as diffusion and transport equations for discretized geometries, representing the silicon wafer or the layer system in a semiconductor device. This deep physical approach gives TCAD simulation predictive accuracy. It is therefore, possible to substitute TCAD simulations for costly and time-consuming test wafer runs when developing and characterizing a new semiconductor device or technology. TCAD simulations are widely used throughout the semiconductor industry. As technologies become more complex, the semiconductor industry relies increasingly more on TCAD to cut costs and speeds up the research and development process. In addition, semiconductor manufacturers use TCAD
2 16 for yield analysis, which is, monitoring, analyzing, and optimizing their IC process flows, as well as analyzing the impact of IC process variation. 2.2 SENTAURUS TCAD Sentaurus TCAD from (Synopsys ) is used in this study. There are various modules in Sentaurus TCAD and we have used the following modules. Sentaurus Structure Editor (SDE) Sentaurus Device (SDEVICE) Inspect Tecplot Sentaurus Workbench These modules are discussed as follows Sentaurus Structure Editor Sentaurus Structure Editor is a structure editor, which can be used to build 2D and 3D device structures. The contact sets are defined and the contact placement is done in SDE. It has built-in, analytical profiles allowing user to define doping and algorithms for meshing the device. The grid and doping file (TDR format) contains two kinds of information: One is the device geometry, including the regions and materials of the device, the locations of the contacts, and the mesh points, including the location of all the discrete points, also called nodes or vertices. The other is the field values in the device, for example, the doping profiles. The structure file can be 1D, 2D, or 3D. They are typically generated by the mesh engine Mesh.
3 17 In addition, it can emulate semiconductor process steps. It has three distinct operational modes: 2D structure editing, 3D structure editing, and 3D process emulation. From the graphical user interface, 2D and 3D device models are created geometrically, using 2D or 3D primitives, such as rectangles, polygons, cuboids, cylinders, and spheres. Apart from these, there are some options like filleting, 3D edge blending, and chamfering are also available. The main types of input and output file supported by Sentaurus Structure Editor are explained. Input file - This is a user-defined script file that contains scheme script commands describing the steps to be executed by Sentaurus Structure Editor in creating a device structure. This file can be edited to change its content. Output file - This is an output file to view the structure of the device and it is given as input to the SDEVICE file. The other file formats that are supported by SDE are *.sab, *.sat. *.bnd, *.tdr,*.cmd,*.lyt,*.grd,*.scm and *.tcl Sentaurus Device Sentaurus Device is a comprehensive, semiconductor, device simulator framework capable of simulating the electrical, thermal, and optical characteristics of silicon-based and compound semiconductor devices. It simulates 1D, 2D, and 3D geometries over a wide range of operating conditions, including mixed-mode circuit simulation, combining numeric devices with compact models. It incorporates advanced physical models and robust numeric methods for the simulation of most types of semiconductor device ranging from very deep submicron silicon MOSFETs to large bipolar power structures.
4 18 and SDEVICE. Figure 2.1 shows the flow diagram of input and output files in SDE Figure 2.1: Flow of input and output files in SDE and SDEVICE Input Command File A typical input command file of Sentaurus Device consists of several command sections (or statement blocks) with each section executing a relatively independent function. The input command file typically contains the following sections: File The File section defines the input and output files of the simulation. Sentaurus Device expects one essential file of input to define the device structure. A Sentaurus Device simulation produces several output files: The Current file contains the electrical output data, such as currents, voltages, and charges at each of the contacts. The Output file contains all the informative texts that Sentaurus Device has downloaded during a run, including the physical models that have been activated and the parameter values that have been used.
5 19 Electrode The electrical (or thermal) contacts of the device, together with their initial bias conditions, are defined in the Electrode section. If there is a special boundary condition for a contact, it can be defined here. Each electrode defined here must match exactly (case sensitive) an existing contact name in the structure file and only the contacts that are named in the Electrode block are included in the simulation. If the ideal gate contact is used, then Barrier is the parameter to be used. Physics In the Physics section, physical models to be used in the simulation are declared. Example models include the carrier mobility model, the bandgap narrowing model, the carrier generation and recombination model, the impact ionization model, and the gate leakage model. Options are available to specify a particular region in a device using Material= material name or Region= region name. In the Physics section, the models are only declared or activated. The models for velocity saturation and mobility degradation are also available. Depending on the device under investigation and the level of modeling accuracy required, Drift-Diffusion simulation mode is chosen in this study. This is an isothermal simulation, described by basic semiconductor equations and is suitable for low power density devices with long active regions. Math Sentaurus Device solves the device equations (which are essentially a set of partial differential equations) self-consistently, on the discrete mesh, in an iterative fashion. For each iteration, an error is calculated and Sentaurus Device attempts to converge on a solution that has an acceptably small error.
6 20 The Math section is used to control the numeric solver in the simulation. The Math parameters to the solution algorithms are device independent and must only appear in the base Math section. These can be grouped by solver type. The control parameters for the linear solvers are Method and SubMethod. The keyword Method selects the linear solver to be used, and the keyword SubMethod selects the inner method for blockdecomposition methods. The two linear solvers PARDISO and ILS support the option MultipleRHS to solve linear systems with multiple right-hand sides. This option is only appropriate for AC analysis. Solve To get an initial solution, equilibrium condition is first reached with the Poisson equation. The initial bias conditions are taken from those specified in the Electrode section. The Poisson equation and carrier continuity equations are solved self consistently in a single Newton solver. Plot The Plot section is used to specify the solution variables that are to be saved in the Plot file (named in the File section), which is performed at the end of the simulation or saved in a file using the Plot command within the Solve section, which can be performed at any specified bias point. The variables like doping and carrier concentrations, current densities and electric field distributions can be viewed in plot section using Tecplot Tecplot Tecplot SV is a part of Sentaurus Workbench Visualization. It is a plotting software with extensive 2D and 3D capabilities for visualizing data from simulations and experiments. The.tdr file is used to describe a device structure, its meshing and the values of field quantities existing in the corresponding device.
7 Inspect Inspect is a plotting and analysis tool for xy data, such as doping profiles and electrical characteristics of semiconductor devices. Inspect is a tool that is used to display and analyze curves. It features a convenient graphical user interface, a script language and an interactive language for computations with curves Sentaurus Workbench Sentaurus Workbench is the framework designed to make the use of TCAD tools easier. It frees from typing system commands for the handling of data files or starting applications. Sentaurus Workbench is the primary graphical front end that integrates Sentaurus simulation programs into one environment. Sentaurus Workbench automatically manages the information flow from one tool to another. This includes preprocessing user input files, parameterizing projects, setting up and executing tool instances, and visualizing the results. Its intuitive graphical user interface (GUI) is used to design, organize, and run simulations for semiconductor research and manufacturing. Simulations are comprehensively organized into projects. A simulation flow typically consists of several tools, such as the process simulator Sentaurus Process, the meshing tool Mesh, the device simulator Sentaurus Device and the plotting and analysis tool Inspect. Sentaurus Workbench allows defining parameters and variables to run comprehensive parametric analyses. The use of mathematical and logical expressions serves to preprocess the simulation input dynamically. The resulting data can be used with statistical and spreadsheet software.
8 SIMULATION METHODOLOGY In this work, we have used the tools, structure editor, sdevice, tecplot and inspect to investigate the performance of FinFETs, Junctionless FETs and GAA devices. The transistor at different technology nodes are generated using SDE. From the output structure of the SDE structure editor, suitable mesh for device simulation is generated. SDEVICE device simulator is used to extract the device related parameters. The physics section of SDEVICE includes the appropriate models for band to band tunneling, quantization of inversion layer charge, doping dependency of mobility, effect of high and normal electric fields on mobility, and velocity saturation Extraction of V T, I ON, I OFF and R o From the saturation I D -V G characteristics, I ON, I OFF and V T are extracted. I OFF is extracted when drain voltage is maximum and the gate voltage is zero. I ON is extracted when both the gate and drain voltages are maximum. V T is extracted by constant current method with value of 10-7 A. This is the method wherein the gate voltage is extracted at which the drain current exceeds a given current level. From the I D -V D characteristics, R o is extracted at different gate bias Extraction of f t In a small-signal analysis simulation, Sentaurus Device computes the Y-matrix. The Y-matrix describes how the currents in a circuit would react if the applied voltages at different contact nodes of the circuit change. For any two-port network, the current and voltage can be represented in matrix form as follows
9 23 i Y Y V i Y Y V (2.1) The output of the SDEVICE has the following form ( a, c ) ( a, c ) ( a, c ) ( a, c ) (2.2) This can be interpreted in the following way i ( a j c ) ( a j c ) V i ( a j c ) ( a j c ) V (2.3) The complex Y-matrix can be split into two parts: The real part a is called conductance matrix, which measures the in-phase response of the current with the voltage, the imaginary part c is called the capacitance matrix, which measures the out-phase response. The symbol j = -1 specify the imaginary part of a complex variable and denotes the frequency of the small-signal change. Standard AC simulations are done in SDEVICE and AC Y simulations yield Y parameter matrix. f t is the frequency at which Y ( f ) ( f ) equals one, and it strongly depends on the gate bias. At various gate biases f t is calculated and the maximum of them is taken as f t. Figure 2.2 depicts the graph of the variation of f t with respect to gate bias.
10 24 Figure 2.2: Typical graph of f t versus gate bias Non-Quasi Static Delay When a small time varying ac signal (V g ) is applied to a gate of the transistor, kept in strong inversion and saturation, the inversion charge takes some time to respond to the gate signal i.e. there is a phase difference( ) between the signal (gate voltage V G ) and the inversion charge response (drain current I D ). When the signal frequency increases, also increases. According to the accuracy needed, may be fixed, and the delay corresponding to this is known as Non-Quasi Static delay ( ). Figure 2.3 shows a typical circuit to study NQS delay. To calculate NQS delay, a transient simulation is performed by plotting V g and I d. i.e. a small time varying AC signal along with a DC bias (0.5V) is applied to the gate. The delay ( ) between the applied gate signal and the drain current is measured to get the NQS delay.
11 25 Figure 2.3: A typical circuit to study NQS delay Figure 2.4 shows a waveform of NQS delay. Here one complete cycle of the wave is associated with an angular displacement of 2 radians. A (t) = A. sin (2 ft + ) = A. sin ( t+ ) (2.4) where f is the frequency and is the angular frequency, A is the amplitude of the signal. Here A=1. The phase is the angle of a signal portion; it is specified in angular degrees and provides a reference to the reference value of the entire signal. It can be calculated as Phase angle (deg) = 360.f. (2.5)
12 26 Figure 2.4: A waveform showing NQS delay Intrinsic Gain The intrinsic gain can be defined as the product of transconductance (g m ) and output resistance (R o ). It is given by Intrinsic gain= g m.r o (2.6) From the saturation I D -V G characteristics, g m is extracted by taking the derivative of the I D -V G curve. From the I D -V D characteristics, R o is extracted. The bias points at which both g m and R o are extracted are taken as V DD /2.
13 Noise Figure The noise figure (NF) is a figure of merit for the high frequency noise of two port devices. Considering the two port model of the MOSFET, the spectrum of the noise power P =v O. i O at the output of the device can be measured and the noise figure is then defined as follows (Schmitusen et al 2000; Schenk et al 2003) NF O, noisy P O, noiseless P (2.7) Figure 2.5: Equivalent network showing noise measurement circuitry Figure 2.5 shows an equivalent network representing the principal noise measurement circuitry neglecting the dc biasing circuit and other parasitic parts. NF depends on the frequency and the admittance of the input noise source Y S. Here P O,noisy is the output noise power if the device under test (DUT) is noisy while P O,noiseless is the output noise power for noiseless DUT. In the noise measurement circuit of Fig. 2.5 the noisy two-port is represented by its Y-parameters and equivalent voltage noise sources e 1 and e 2 at the input and output of the device. These voltage noise sources e 1 and e 2 with the noise voltage auto-correlation spectra S 1 V and S 2 V are correlated through the noise voltage cross-correlation spectrum S 21 V. The voltage noise sources e1 and e2
14 28 could be replaced by current noise sources i 1 =Y 11 e 1 and i 2 =Y 22 e 2 inserted in parallel to the admittances Y 11 and Y 22 respectively. Noise simulation in SDEVICE is a standard AC simulation with noise models included in the physics section. The results from the noise simulation are used to extract the noise figure which is given by NF 1 gg 2 dd gd 1 + SI S I 2 Re ( SI ) s (2.8) S I with Where Y s (2.9) Y11 Y21 admittance and is given by S S I is the current noise spectrum of the noisy source S S k T Re( Y ) (2.10) I 4 B S gg S I and terminals respectively, dd S I are the noise current spectrums, at the gate and drain dg S I is the cross-correlation noise spectra between the drain and gate terminals, Y 11 (i.e. Y gg ) and Y 21 (i.e. Y dg )are the respective admittance parameters. 2.4 SENSITIVITY ANALYSIS Sensitivity analysis is done by varying one parameter at a time, keeping all other parameters as a constant quantity and observing the output quantity of interest (Wong et al 1989). Considering a generalized model with a set of independent variables, X={X 1, X 2, X 3...X n } and a dependent variable (also known as response) Y=f(X), the simplest method of sensitivity analysis
15 29 is to vary one parameter at a time by a given percentage while holding the other parameters fixed (Hamby 1994). Sensitivity coefficient ( i) is defined as i % % Y X i (2.11) where Y is the change in the output parameter and X i is the change in the input parameter considered. A sensitivity ranking can be obtained by looking at the various sensitivity coefficients. For more than one dependent variable response vector (Y) is obtained. The independent vector X, in this study, consists of the structural and doping parameters. The dependent vector, Y consists of f t, NQS delay, intrinsic gain and noise figure. The sensitivity of Y with respect to X can be calculated as YX Y S (2.12) X 2.5 PLACKETT-BURMAN SCREENING METHODOLOGY The statistical design of experiments is an efficient procedure for planning experiments so that the data obtained can be analyzed to yield valid and objective conclusions. DOE is useful at the start of a response surface study where screening experiments should be performed to identify the important system or process parameters. Response Surface Methodology (RSM) involves exploration of a large parameters space, for studying the statistical significance of each one of them through 2 nd order response surface modeling. However performing RSM for a large set of input variables becomes computationally inefficient. Hence it is typically preceded by a step wherein, the relatively insignificant input variables are eliminated from RSM study (screening experiment). This procedure can be visualized as a block
16 30 diagram with multiple, inputs and multiple outputs, as depicted in Fig. 2.6, with the box indicating the system or a process for k process parameters and m responses. Each response is a function of all the input variables. Figure 2.6: Block diagram with input and output variables The successful use of fractional factorial designs are based on a key idea called sparsity of effects (Myers and Montgomery 2002). According to this, if there are several variables, the system or process is likely to be driven by some of the main effects and low order interactions. According to two level Plackett-Burman (PB) DOE, k = N-1 factors can be studied in just N runs of experiments, for N divisible by 4. Through suitable DOE, it can be shown that the j th observation of an actual experiment, y j for j = 1, 2 N, in terms of x i s which vary from -1 to +1, can be expressed as, y j 0 x j1 1 x j x jk k j (2.13) where the constant 0, and the coefficients 1, 2,... k, can be calculated from experimental data, and j is the total effect of all the higher order interactions, which is assumed to be small for most of the practical purposes.
17 31 The purpose of the experiment is to estimate s in Equation 2.13, from a set of measurements m 1, m 2... m N. For this we must solve a set of N linear equations. These equations always involve 0, and therefore to estimate k number of s it is necessary to make at least N = k + 1 measurements. Normally the value of N, the number of runs in an experiment is much less than the complete factorial 2k designs, for k factors. The greater the N, greater will be the precision with which factor effects may be estimated. The estimation of error variance of is minimized when N = 4I, where I is an integer as in a 2 level PB DOE. In the PB designs with factors at 2 levels, all the main effects may be estimated with maximum precision. The parameters that are listed in Fig. 2.6 are assigned to each column of a standard PB, Design Matrix (DM) of Fig. 2.7 (transposed) with 12 runs for 11 factors (NIST 2006). This DM contains vectors of +/- sign, corresponding to ±1 which in turn corresponds to ±10% (=3 ) deviation from the nominal values. Factors Exp. No X1 X2 X3 X4 X5 X6 X7 X8 X9 X10 X Figure 2.7: Plackett-Burman (transposed) design matrix
18 32 Four experiments have been performed, each time arbitrarily assigning parameters to the columns of DM. First order models were built for f t, NQS delay, intrinsic gain and NF which are also called as responses, in a single regression from the results that are obtained from all the 4 experiments. This was done for better estimation of model coefficients and hence effective screening. The first order model building involves the estimation of the model coefficient vector for each of the responses from 48(12 X4) runs, using least square error (LSE) technique to compute the model coefficients as, T 1 T X X X Y (2.14) where = [ ft, NQS delay, intrinsic gain, NF ] is a 13x4 coefficient matrix, corresponding to 4 responses, X is the 48x13 matrix (of -1s and +1s for 2 level designs, implying the involved process variable x i s are normalized), which is the DM resulting from 4 experiments, augmented with a first column of +1s, and Y = [y ft, y NQS delay, y intrinsic gain, y NF ] is the 48x4, response matrix, with each column corresponding to their subscripted response parameter, extracted from all the 4 experiments (48 runs). The functional form of each response is in the form of Equation As each variable have the same range from -1 to +1 in a regression model for a particular response, the magnitude of the model coefficients will indicate the significance of the corresponding variable for that response. The model coefficients are generated with the help of SPSS, a statistical tool (SPSS 2011). For the elements of each column of the percentage scale. matrix, a rank can be assigned on a
19 CONCLUSION Since this thesis work is based on TCAD simulation, usage of various modules in this study and their capabilities have been discussed in this chapter. Various parameters, both DC (V T, I ON, I OFF and R o ) and AC (f t, NQS delay, intrinsic gain and noise figure) are used throughout all the chapters. The extraction strategies of these parameters are also discussed. Throughout the chapters the sensitivity analysis is used to rank the parameters and a general procedure to do the sensitivity analysis is also discussed in this chapter.
CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS
98 CHAPTER 5 EFFECT OF GATE ELECTRODE WORK FUNCTION VARIATION ON DC AND AC PARAMETERS IN CONVENTIONAL AND JUNCTIONLESS FINFETS In this chapter, the effect of gate electrode work function variation on DC
More informationTechnology Computer Aided Design (TCAD) Laboratory. Lecture 2, A simulation primer
Technology Computer Aided Design (TCAD) Laboratory Lecture 2, A simulation primer [Source: Synopsys] Giovanni Betti Beneventi E-mail: gbbeneventi@arces.unibo.it ; giobettibeneventi@gmail.com Office: Engineering
More informationOperation and Modeling of. The MOS Transistor. Second Edition. Yannis Tsividis Columbia University. New York Oxford OXFORD UNIVERSITY PRESS
Operation and Modeling of The MOS Transistor Second Edition Yannis Tsividis Columbia University New York Oxford OXFORD UNIVERSITY PRESS CONTENTS Chapter 1 l.l 1.2 1.3 1.4 1.5 1.6 1.7 Chapter 2 2.1 2.2
More informationSemiconductor Physics fall 2012 problems
Semiconductor Physics fall 2012 problems 1. An n-type sample of silicon has a uniform density N D = 10 16 atoms cm -3 of arsenic, and a p-type silicon sample has N A = 10 15 atoms cm -3 of boron. For each
More informationRole of Computer Experiment
Role of Computer Experiment Experimental World Computer Experiment Theoretical World Accumulation of factual information Checks and stimuli Ordering of factual information into logically coherent patterns
More informationSimple and accurate modeling of the 3D structural variations in FinFETs
Simple and accurate modeling of the 3D structural variations in FinFETs Donghu Kim Electrical Engineering Program Graduate school of UNIST 2013 Simple and accurate modeling of the 3D structural variations
More informationSTATISTICAL MODELLING OF f t TO PROCESS PARAMETERS IN 30 NM GATE LENGTH FINFETS B. Lakshmi and R. Srinivasan
STATISTICAL MODELLING OF f t TO PROCESS PARAMETERS IN 30 NM GATE LENGTH FINFETS B. Lakshmi and R. Srinivasan Department of Information Technology SSN College of Engineering, Kalavakkam 603 110, Chennai,
More informationSOI/SOTB Compact Models
MOS-AK 2017 An Overview of the HiSIM SOI/SOTB Compact Models Marek Mierzwinski*, Dondee Navarro**, and Mitiko Miura-Mattausch** *Keysight Technologies **Hiroshima University Agenda Introduction Model overview
More informationReduction of Self-heating effect in LDMOS devices
Reduction of Self-heating effect in LDMOS devices T.K.Maiti * and C. K. Maiti ** Department of Electronics and Electrical Communication Engineering, Indian Institute of Technology, Kharagpur-721302, India
More informationCHAPTER 3. EFFECT OF STRUCTURAL AND DOPING PARAMETER VARIATIONS ON f t, NQS DELAY, INTRINSIC GAIN AND NF IN N-TYPE FINFETS
34 CHAPTER 3 EFFECT OF STRUCTURAL AND DOPING PARAMETER VARIATIONS ON f t, NQS DELAY, INTRINSIC GAIN AND NF IN N-TYPE FINFETS In this chapter, the effect of structural and doping parameter variations on
More informationMOS Transistors. Prof. Krishna Saraswat. Department of Electrical Engineering Stanford University Stanford, CA
MOS Transistors Prof. Krishna Saraswat Department of Electrical Engineering S Stanford, CA 94305 saraswat@stanford.edu 1 1930: Patent on the Field-Effect Transistor! Julius Lilienfeld filed a patent describing
More information1 Name: Student number: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND. Fall :00-11:00
1 Name: DEPARTMENT OF PHYSICS AND PHYSICAL OCEANOGRAPHY MEMORIAL UNIVERSITY OF NEWFOUNDLAND Final Exam Physics 3000 December 11, 2012 Fall 2012 9:00-11:00 INSTRUCTIONS: 1. Answer all seven (7) questions.
More informationLong Channel MOS Transistors
Long Channel MOS Transistors The theory developed for MOS capacitor (HO #2) can be directly extended to Metal-Oxide-Semiconductor Field-Effect transistors (MOSFET) by considering the following structure:
More informationAppendix 1: List of symbols
Appendix 1: List of symbols Symbol Description MKS Units a Acceleration m/s 2 a 0 Bohr radius m A Area m 2 A* Richardson constant m/s A C Collector area m 2 A E Emitter area m 2 b Bimolecular recombination
More informationBSIM-CMG Model. Berkeley Common-Gate Multi-Gate MOSFET Model
BSIM-CMG Model Why BSIM-CMG Model When we reach the end of the technology roadmap for the classical CMOS, multigate (MG) CMOS structures will likely take up the baton. Numerous efforts are underway to
More informationMOS CAPACITOR AND MOSFET
EE336 Semiconductor Devices 1 MOS CAPACITOR AND MOSFET Dr. Mohammed M. Farag Ideal MOS Capacitor Semiconductor Devices Physics and Technology Chapter 5 EE336 Semiconductor Devices 2 MOS Capacitor Structure
More informationCurrent mechanisms Exam January 27, 2012
Current mechanisms Exam January 27, 2012 There are four mechanisms that typically cause currents to flow: thermionic emission, diffusion, drift, and tunneling. Explain briefly which kind of current mechanisms
More informationChapter 4 Field-Effect Transistors
Chapter 4 Field-Effect Transistors Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 5/5/11 Chap 4-1 Chapter Goals Describe operation of MOSFETs. Define FET characteristics in operation
More informationSemiconductor Module
Semiconductor Module Optics Seminar July 18, 2018 Yosuke Mizuyama, Ph.D. COMSOL, Inc. The COMSOL Product Suite Governing Equations Semiconductor Schrödinger Equation Semiconductor Optoelectronics, FD Semiconductor
More informationModelling of Diamond Devices with TCAD Tools
RADFAC Day - 26 March 2015 Modelling of Diamond Devices with TCAD Tools A. Morozzi (1,2), D. Passeri (1,2), L. Servoli (2), K. Kanxheri (2), S. Lagomarsino (3), S. Sciortino (3) (1) Engineering Department
More informationOverview of Modeling and Simulation TCAD - FLOOPS / FLOODS
Overview of Modeling and Simulation TCAD - FLOOPS / FLOODS Modeling Overview Strain Effects Thermal Modeling TCAD Modeling Outline FLOOPS / FLOODS Introduction Progress on GaN Devices Prospects for Reliability
More informationSemiconductor Physics Problems 2015
Semiconductor Physics Problems 2015 Page and figure numbers refer to Semiconductor Devices Physics and Technology, 3rd edition, by SM Sze and M-K Lee 1. The purest semiconductor crystals it is possible
More informationMOS Transistor Theory
CHAPTER 3 MOS Transistor Theory Outline 2 1. Introduction 2. Ideal I-V Characteristics 3. Nonideal I-V Effects 4. C-V Characteristics 5. DC Transfer Characteristics 6. Switch-level RC Delay Models MOS
More informationMOSFET: Introduction
E&CE 437 Integrated VLSI Systems MOS Transistor 1 of 30 MOSFET: Introduction Metal oxide semiconductor field effect transistor (MOSFET) or MOS is widely used for implementing digital designs Its major
More informationSpring Semester 2012 Final Exam
Spring Semester 2012 Final Exam Note: Show your work, underline results, and always show units. Official exam time: 2.0 hours; an extension of at least 1.0 hour will be granted to anyone. Materials parameters
More informationFinal Examination EE 130 December 16, 1997 Time allotted: 180 minutes
Final Examination EE 130 December 16, 1997 Time allotted: 180 minutes Problem 1: Semiconductor Fundamentals [30 points] A uniformly doped silicon sample of length 100µm and cross-sectional area 100µm 2
More informationBipolar Transistor WS 2011
Institut für Integrierte Systeme Integrated Systems Laboratory Bipolar Transistor WS 2011 1 Introduction In this exercise we want to simulate the IV characteristics of a bipolar transistor and draw the
More informationMOS Transistor Properties Review
MOS Transistor Properties Review 1 VLSI Chip Manufacturing Process Photolithography: transfer of mask patterns to the chip Diffusion or ion implantation: selective doping of Si substrate Oxidation: SiO
More informationFigure 1: MOSFET symbols.
c Copyright 2008. W. Marshall Leach, Jr., Professor, Georgia Institute of Technology, School of Electrical and Computer Engineering. The MOSFET Device Symbols Whereas the JFET has a diode junction between
More informationSemiconductor Physics fall 2012 problems
Semiconductor Physics fall 2012 problems 1. An n-type sample of silicon has a uniform density N D = 10 16 atoms cm -3 of arsenic, and a p-type silicon sample has N A = 10 15 atoms cm -3 of boron. For each
More informationLecture 04 Review of MOSFET
ECE 541/ME 541 Microelectronic Fabrication Techniques Lecture 04 Review of MOSFET Zheng Yang (ERF 3017, email: yangzhen@uic.edu) What is a Transistor? A Switch! An MOS Transistor V GS V T V GS S Ron D
More informationAtlas III-V Advanced Material Device Modeling
Atlas III-V Advanced Material Device Modeling Requirements for III-V Device Simulation Blaze as Part of a Complete Simulation Toolset III-V Device Simulation maturity has conventionally lagged behind silicon
More informationIntroduction to Power Semiconductor Devices
ECE442 Power Semiconductor Devices and Integrated Circuits Introduction to Power Semiconductor Devices Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Power Semiconductor Devices Applications System Ratings
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The Devices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationECE-305: Fall 2017 MOS Capacitors and Transistors
ECE-305: Fall 2017 MOS Capacitors and Transistors Pierret, Semiconductor Device Fundamentals (SDF) Chapters 15+16 (pp. 525-530, 563-599) Professor Peter Bermel Electrical and Computer Engineering Purdue
More informationSolid State Electronics. Final Examination
The University of Toledo EECS:4400/5400/7400 Solid State Electronic Section elssf08fs.fm - 1 Solid State Electronics Final Examination Problems Points 1. 1. 14 3. 14 Total 40 Was the exam fair? yes no
More informationECE 342 Electronic Circuits. Lecture 6 MOS Transistors
ECE 342 Electronic Circuits Lecture 6 MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2
More informationTrench IGBT failure mechanisms evolution with temperature and gate resistance under various short-circuit conditions
Author manuscript, published in "Microelectronics Reliability vol.47 (7) pp.173-1734" Trench IGBT failure mechanisms evolution with temperature and gate resistance under various short-circuit conditions
More informationThis is the 15th lecture of this course in which we begin a new topic, Excess Carriers. This topic will be covered in two lectures.
Solid State Devices Dr. S. Karmalkar Department of Electronics and Communication Engineering Indian Institute of Technology, Madras Lecture - 15 Excess Carriers This is the 15th lecture of this course
More informationDesign/Technology Co-Optimisation (DTCO) in the Presence of Acute Variability
Design/Technology Co-Optimisation (DTCO) in the Presence of Acute Variability A. Asenov 1,2, E. A. Towie 1!! 1 Gold Standard Simulations Ltd 2 Glasgow University! Summary!! Introduction!! FinFET complexity
More informationECE 546 Lecture 10 MOS Transistors
ECE 546 Lecture 10 MOS Transistors Spring 2018 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jesa@illinois.edu NMOS Transistor NMOS Transistor N-Channel MOSFET Built on p-type
More informationSchottky diodes. JFETs - MESFETs - MODFETs
Technische Universität Graz Institute of Solid State Physics Schottky diodes JFETs - MESFETs - MODFETs Quasi Fermi level When the charge carriers are not in equilibrium the Fermi energy can be different
More informationIndex. buried oxide 35, 44 51, 89, 238 buried channel 56
Index A acceptor 275 accumulation layer 35, 45, 57 activation energy 157 Auger electron spectroscopy (AES) 90 anode 44, 46, 55 9, 64, 182 anode current 45, 49, 65, 77, 106, 128 anode voltage 45, 52, 65,
More informationELECTRONICS IA 2017 SCHEME
ELECTRONICS IA 2017 SCHEME CONTENTS 1 [ 5 marks ]...4 2...5 a. [ 2 marks ]...5 b. [ 2 marks ]...5 c. [ 5 marks ]...5 d. [ 2 marks ]...5 3...6 a. [ 3 marks ]...6 b. [ 3 marks ]...6 4 [ 7 marks ]...7 5...8
More informationECE 342 Electronic Circuits. 3. MOS Transistors
ECE 342 Electronic Circuits 3. MOS Transistors Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jschutt@emlab.uiuc.edu 1 NMOS Transistor Typically L = 0.1 to 3 m, W = 0.2 to
More informationMSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University
MSE 310/ECE 340: Electrical Properties of Materials Fall 2014 Department of Materials Science and Engineering Boise State University Practice Final Exam 1 Read the questions carefully Label all figures
More informationSession 6: Solid State Physics. Diode
Session 6: Solid State Physics Diode 1 Outline A B C D E F G H I J 2 Definitions / Assumptions Homojunction: the junction is between two regions of the same material Heterojunction: the junction is between
More informationScaling Issues in Planar FET: Dual Gate FET and FinFETs
Scaling Issues in Planar FET: Dual Gate FET and FinFETs Lecture 12 Dr. Amr Bayoumi Fall 2014 Advanced Devices (EC760) Arab Academy for Science and Technology - Cairo 1 Outline Scaling Issues for Planar
More informationDigital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. The Devices. July 30, Devices.
Digital Integrated Circuits A Design Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The July 30, 2002 1 Goal of this chapter Present intuitive understanding of device operation Introduction
More information16EC401 BASIC ELECTRONIC DEVICES UNIT I PN JUNCTION DIODE. Energy Band Diagram of Conductor, Insulator and Semiconductor:
16EC401 BASIC ELECTRONIC DEVICES UNIT I PN JUNCTION DIODE Energy bands in Intrinsic and Extrinsic silicon: Energy Band Diagram of Conductor, Insulator and Semiconductor: 1 2 Carrier transport: Any motion
More informationMetal-oxide-semiconductor field effect transistors (2 lectures)
Metal-ide-semiconductor field effect transistors ( lectures) MOS physics (brief in book) Current-voltage characteristics - pinch-off / channel length modulation - weak inversion - velocity saturation -
More informationEE105 Fall 2014 Microelectronic Devices and Circuits. NMOS Transistor Capacitances: Saturation Region
EE105 Fall 014 Microelectronic Devices and Circuits Prof. Ming C. Wu wu@eecs.berkeley.edu 511 Sutardja Dai Hall (SDH) 1 NMOS Transistor Capacitances: Saturation Region Drain no longer connected to channel
More informationModeling and Analysis of Full-Chip Parasitic Substrate Currents
Modeling and Analysis of Full-Chip Parasitic Substrate Currents R. Gillon, W. Schoenmaker September 11, 2017 Rev. 2.0 1 Outline Objectives Challenges SPX solver Solutions l Compact Modeling (ONSEMI) l
More informationMOSFET Capacitance Model
MOSFET Capacitance Model So far we discussed the MOSFET DC models. In real circuit operation, the device operates under time varying terminal voltages and the device operation can be described by: 1 small
More informationnmos IC Design Report Module: EEE 112
nmos IC Design Report Author: 1302509 Zhao Ruimin Module: EEE 112 Lecturer: Date: Dr.Zhao Ce Zhou June/5/2015 Abstract This lab intended to train the experimental skills of the layout designing of the
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationDevice 3D. 3D Device Simulator. Nano Scale Devices. Fin FET
Device 3D 3D Device Simulator Device 3D is a physics based 3D device simulator for any device type and includes material properties for the commonly used semiconductor materials in use today. The physical
More informationLecture 2. Introduction to semiconductors Structures and characteristics in semiconductors
Lecture 2 Introduction to semiconductors Structures and characteristics in semiconductors Semiconductor p-n junction Metal Oxide Silicon structure Semiconductor contact Literature Glen F. Knoll, Radiation
More informationTransistors - a primer
ransistors - a primer What is a transistor? Solid-state triode - three-terminal device, with voltage (or current) at third terminal used to control current between other two terminals. wo types: bipolar
More informationIntrinsic Small-Signal Equivalent Circuit of GaAs MESFET s
Intrinsic Small-Signal Equivalent Circuit o GaAs MESFET s M KAMECHE *, M FEHAM M MELIANI, N BENAHMED, S DALI * National Centre o Space Techniques, Algeria Telecom Laboratory, University o Tlemcen, Algeria
More informationComparative Analysis of Practical Threshold Voltage Extraction Techniques for CMOS. Yu-Hsing Cheng ON Semiconductor October 15, 2018
Comparative Analysis of Practical Threshold Voltage Extraction Techniques for CMOS and LDMOS Devices in 180 nm Technology Yu-Hsing Cheng ON Semiconductor October 15, 2018 Outline Overview and Background
More informationDC and AC modeling of minority carriers currents in ICs substrate
DC and AC modeling of minority carriers currents in ICs substrate Camillo Stefanucci, Pietro Buccella, Maher Kayal and Jean-Michel Sallese Swiss Federal Institute of Technology Lausanne, Switzerland MOS-AK
More informationQuantum and Non-local Transport Models in Crosslight Device Simulators. Copyright 2008 Crosslight Software Inc.
Quantum and Non-local Transport Models in Crosslight Device Simulators Copyright 2008 Crosslight Software Inc. 1 Introduction Quantization effects Content Self-consistent charge-potential profile. Space
More informationSupertex inc. TN0104. N-Channel Enhancement-Mode Vertical DMOS FET. Features. General Description. Applications. Ordering Information.
TN1 N-Channel Enhancement-Mode Vertical DMOS FET Features Low threshold (1.6V max.) High input impedance Low input capacitance Fast switching speeds Low on-resistance Free from secondary breakdown Low
More informationECE 497 JS Lecture - 12 Device Technologies
ECE 497 JS Lecture - 12 Device Technologies Spring 2004 Jose E. Schutt-Aine Electrical & Computer Engineering University of Illinois jose@emlab.uiuc.edu 1 NMOS Transistor 2 ρ Source channel charge density
More informationField effect = Induction of an electronic charge due to an electric field Example: Planar capacitor
JFETs AND MESFETs Introduction Field effect = Induction of an electronic charge due to an electric field Example: Planar capacitor Why would an FET made of a planar capacitor with two metal plates, as
More informationN Channel MOSFET level 3
N Channel MOSFET level 3 mosn3 NSource NBulk NSource NBulk NSource NBulk NSource (a) (b) (c) (d) NBulk Figure 1: MOSFET Types Form: mosn3: instance name n 1 n n 3 n n 1 is the drain node, n is the gate
More informationElectronic Circuits for Mechatronics ELCT 609 Lecture 2: PN Junctions (1)
Electronic Circuits for Mechatronics ELCT 609 Lecture 2: PN Junctions (1) Assistant Professor Office: C3.315 E-mail: eman.azab@guc.edu.eg 1 Electronic (Semiconductor) Devices P-N Junctions (Diodes): Physical
More informationTheory of Electrical Characterization of Semiconductors
Theory of Electrical Characterization of Semiconductors P. Stallinga Universidade do Algarve U.C.E.H. A.D.E.E.C. OptoElectronics SELOA Summer School May 2000, Bologna (It) Overview Devices: bulk Schottky
More informationFor the following statements, mark ( ) for true statement and (X) for wrong statement and correct it.
Benha University Faculty of Engineering Shoubra Electrical Engineering Department First Year communications. Answer all the following questions Illustrate your answers with sketches when necessary. The
More informationErik Lind
High-Speed Devices, 2011 Erik Lind (Erik.Lind@ftf.lth.se) Course consists of: 30 h Lectures (H322, and Fys B check schedule) 8h Excercises 2x2h+4h Lab Excercises (2 Computer simulations, 4 RF measurment
More informationLAYOUT TECHNIQUES. Dr. Ivan Grech
LAYOUT TECHNIQUES OUTLINE Transistor Layout Resistor Layout Capacitor Layout Floor planning Mixed A/D Layout Automatic Analog Layout Layout Techniques Main Layers in a typical Double-Poly, Double-Metal
More informationThe Devices. Jan M. Rabaey
The Devices Jan M. Rabaey Goal of this chapter Present intuitive understanding of device operation Introduction of basic device equations Introduction of models for manual analysis Introduction of models
More informationIntroduction and Background
Analog CMOS Integrated Circuit Design Introduction and Background Dr. Jawdat Abu-Taha Department of Electrical and Computer Engineering Islamic University of Gaza jtaha@iugaza.edu.ps 1 Marking Assignments
More informationSchottky Rectifiers Zheng Yang (ERF 3017,
ECE442 Power Semiconductor Devices and Integrated Circuits Schottky Rectifiers Zheng Yang (ERF 3017, email: yangzhen@uic.edu) Power Schottky Rectifier Structure 2 Metal-Semiconductor Contact The work function
More informationThe Devices. Digital Integrated Circuits A Design Perspective. Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic. July 30, 2002
igital Integrated Circuits A esign Perspective Jan M. Rabaey Anantha Chandrakasan Borivoje Nikolic The evices July 30, 2002 Goal of this chapter Present intuitive understanding of device operation Introduction
More informationAt point G V = = = = = = RB B B. IN RB f
Common Emitter At point G CE RC 0. 4 12 0. 4 116. I C RC 116. R 1k C 116. ma I IC 116. ma β 100 F 116µ A I R ( 116µ A)( 20kΩ) 2. 3 R + 2. 3 + 0. 7 30. IN R f Gain in Constant Current Region I I I C F
More informationLecture 3: Transistor as an thermonic switch
Lecture 3: Transistor as an thermonic switch 2016-01-21 Lecture 3, High Speed Devices 2016 1 Lecture 3: Transistors as an thermionic switch Reading Guide: 54-57 in Jena Transistor metrics Reservoir equilibrium
More informationThis is the author s final accepted version.
Al-Ameri, T., Georgiev, V.P., Adamu-Lema, F. and Asenov, A. (2017) Does a Nanowire Transistor Follow the Golden Ratio? A 2D Poisson- Schrödinger/3D Monte Carlo Simulation Study. In: 2017 International
More informationTestability. Shaahin Hessabi. Sharif University of Technology. Adapted from the presentation prepared by book authors.
Testability Lecture 6: Logic Simulation Shaahin Hessabi Department of Computer Engineering Sharif University of Technology Adapted from the presentation prepared by book authors Slide 1 of 27 Outline What
More informationEKV MOS Transistor Modelling & RF Application
HP-RF MOS Modelling Workshop, Munich, February 15-16, 1999 EKV MOS Transistor Modelling & RF Application Matthias Bucher, Wladek Grabinski Electronics Laboratory (LEG) Swiss Federal Institute of Technology,
More informationSwitching circuits: basics and switching speed
ECE137B notes; copyright 2018 Switching circuits: basics and switching speed Mark Rodwell, University of California, Santa Barbara Amplifiers vs. switching circuits Some transistor circuit might have V
More informationMOS Transistor I-V Characteristics and Parasitics
ECEN454 Digital Integrated Circuit Design MOS Transistor I-V Characteristics and Parasitics ECEN 454 Facts about Transistors So far, we have treated transistors as ideal switches An ON transistor passes
More informationECE-343 Test 1: Feb 10, :00-8:00pm, Closed Book. Name : SOLUTION
ECE-343 Test : Feb 0, 00 6:00-8:00pm, Closed Book Name : SOLUTION C Depl = C J0 + V R /V o ) m C Diff = τ F g m ω T = g m C µ + C π ω T = g m I / D C GD + C or V OV GS b = τ i τ i = R i C i ω H b Z = Z
More informationScaling of MOS Circuits. 4. International Technology Roadmap for Semiconductors (ITRS) 6. Scaling factors for device parameters
1 Scaling of MOS Circuits CONTENTS 1. What is scaling?. Why scaling? 3. Figure(s) of Merit (FoM) for scaling 4. International Technology Roadmap for Semiconductors (ITRS) 5. Scaling models 6. Scaling factors
More informationSolid State Device Fundamentals
Solid State Device Fundamentals ENS 345 Lecture Course by Alexander M. Zaitsev alexander.zaitsev@csi.cuny.edu Tel: 718 982 2812 Office 4N101b 1 Outline - Goals of the course. What is electronic device?
More informationThis article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented.
This article has been accepted and published on J-STAGE in advance of copyediting. Content is final as presented. References IEICE Electronics Express, Vol.* No.*,*-* Effects of Gamma-ray radiation on
More informationGaN based transistors
GaN based transistors S FP FP dielectric G SiO 2 Al x Ga 1-x N barrier i-gan Buffer i-sic D Transistors "The Transistor was probably the most important invention of the 20th Century The American Institute
More information8. Schottky contacts / JFETs
Technische Universität Graz Institute of Solid State Physics 8. Schottky contacts / JFETs Nov. 21, 2018 Technische Universität Graz Institute of Solid State Physics metal - semiconductor contacts Photoelectric
More informationMOS Transistor Theory
MOS Transistor Theory So far, we have viewed a MOS transistor as an ideal switch (digital operation) Reality: less than ideal EE 261 Krish Chakrabarty 1 Introduction So far, we have treated transistors
More informationDevice Models (PN Diode, MOSFET )
Device Models (PN Diode, MOSFET ) Instructor: Steven P. Levitan steve@ece.pitt.edu TA: Gayatri Mehta, José Martínez Book: Digital Integrated Circuits: A Design Perspective; Jan Rabaey Lab Notes: Handed
More informationOrganic Device Simulation Using Silvaco Software. Silvaco Taiwan September 2005
Organic Device Simulation Using Silvaco Software Silvaco Taiwan September 2005 Organic Devices Simulation: Contents Introduction Silvaco TCAD Simulator Theory Models OTFT Simulation v.s Measurement OLED
More informationPSEUDORANDOM BINARY SEQUENCES GENERATOR
PSEUDORANDOM BINARY SEQUENCES GENERATOR 1. Theoretical considerations White noise is defined as a random process with power spectral density that is constant in an infinite frequency band. Quasi-white
More informationReview of Semiconductor Physics. Lecture 3 4 Dr. Tayab Din Memon
Review of Semiconductor Physics Lecture 3 4 Dr. Tayab Din Memon 1 Electronic Materials The goal of electronic materials is to generate and control the flow of an electrical current. Electronic materials
More informationDecemb er 20, Final Exam
Fall 2002 6.720J/3.43J Integrated Microelectronic Devices Prof. J. A. del Alamo Decemb er 20, 2002 - Final Exam Name: General guidelines (please read carefully b efore starting): Make sure to write your
More informationToday s lecture. EE141- Spring 2003 Lecture 4. Design Rules CMOS Inverter MOS Transistor Model
- Spring 003 Lecture 4 Design Rules CMOS Inverter MOS Transistor Model Today s lecture Design Rules The CMOS inverter at a glance An MOS transistor model for manual analysis Important! Labs start next
More informationLecture 2. Introduction to semiconductors Structures and characteristics in semiconductors
Lecture 2 Introduction to semiconductors Structures and characteristics in semiconductors Semiconductor p-n junction Metal Oxide Silicon structure Semiconductor contact Literature Glen F. Knoll, Radiation
More informationSemiconductor Integrated Process Design (MS 635)
Semiconductor Integrated Process Design (MS 635) Instructor: Prof. Keon Jae Lee - Office: 응용공학동 #4306, Tel: #3343 - Email: keonlee@kaist.ac.kr Lecture: (Tu, Th), 1:00-2:15 #2425 Office hour: Tues & Thur
More informationChapter 13 Small-Signal Modeling and Linear Amplification
Chapter 13 Small-Signal Modeling and Linear Amplification Microelectronic Circuit Design Richard C. Jaeger Travis N. Blalock 1/4/12 Chap 13-1 Chapter Goals Understanding of concepts related to: Transistors
More informationStretching the Barriers An analysis of MOSFET Scaling. Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa
Stretching the Barriers An analysis of MOSFET Scaling Presenters (in order) Zeinab Mousavi Stephanie Teich-McGoldrick Aseem Jain Jaspreet Wadhwa Why Small? Higher Current Lower Gate Capacitance Higher
More information