Supertex inc. TN0104. N-Channel Enhancement-Mode Vertical DMOS FET. Features. General Description. Applications. Ordering Information.

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1 TN1 N-Channel Enhancement-Mode Vertical DMOS FET Features Low threshold (1.6V max.) High input impedance Low input capacitance Fast switching speeds Low on-resistance Free from secondary breakdown Low input and output leakage Applications Logic level interfaces ideal for TTL and CMOS Solid state relays Battery operated systems Photo voltaic drives Analog switches General purpose line drivers Telecom switches General Description This low threshold, enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Ordering Information Part Number Package Option Packing TN1N3-G 1/Bag TN1N3-G P TN1N3-G P3 TN1N3-G P5 TN1N3-G P13 TN1N3-G P1 TN1N8-G TO-3AA (SOT-89) /Reel /Reel -G denotes a lead (Pb)-free / RoHS compliant package. Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant. Absolute Maximum Ratings Parameter Value Drain-to-source voltage BS Drain-to-gate voltage BV DGS Gate-to-source voltage ±V Operating and storage temperature -55 O C to +15 O C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Typical Thermal Resistance Package TO-3AA (SOT-89) Doc.# DSFP-TN1 θ ja 13 O C/W 133 O C/W Product Summary BX /BV DGX Pin Configuration SOURCE Product Marking SiTN 1 YYWW DRAIN GATE (max) DRAIN TO-3AA (SOT-89) YY = Year Sealed WW = Week Sealed = Green Packaging Package may or may not include the following marks: Si or SS (min) V 1.8Ω.A SOURCE DRAIN GATE TN1LW W = Code for Week Sealed = Green Packaging Package may or may not include the following marks: Si or TO-3AA (SOT-89)

2 Thermal Characteristics Package (continuous) (pulsed) Power C = 5 O C TN1 5mA.A 1.W 5mA.A TO-3AA (SOT-89) 63mA.9A 1.6W 63mA.9A Notes: (continuous) is limited by max rated T j. = 5 C. Mounted on FR5 Board, 5mm x 5mm x 1.57mm. Significant P D increase possible on ceramic substrate. R RM Electrical Characteristics ( = 5 O C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BS Drain-to-source breakdown voltage - - V = V, = 1.mA (th) Gate threshold voltage V =, = 5µA Δ(th) Change in (th) with temperature mv/ O C =, = 1.mA I GSS Gate body leakage na = ± V, = V SS (ON) Zero gate voltage drain current On-state drain current Static drain-to-source on-state resistance µa = V, = Max Rating =.8 Max Rating, = V, = 15 C = 3.V, = V A = 5.V, = V..6 - = 1V, = V = 3.V, = 5mA Both packages = 5.V, = 5mA Ω = 1V, = 1.A TO-3AA - -. Δ Change in with temperature %/ O C = 1V, = 1.A G FS Forward transductance mmho = V, = 5mA C ISS Input capacitance C OSS Common source output capacitance C RSS Reverse transfer capacitance t d(on) Turn-on delay time t r Rise time t d(off) Turn-off delay time t f Fall time V SD Diode forward voltage drop pf ns = V, = V, f = 1.MHz V DD = V, = 1.A, R GEN = 5Ω = V, I SD = 1.A V TO-3AA - -. = V, I SD =.5A t rr Reverse recovery time ns = V, I SD = 1.A Notes: 1. All D.C. parameters 1% tested at 5 O C unless otherwise stated. (Pulse test: 3µs pulse, % duty cycle.). All A.C. parameters sample tested. Doc.# DSFP-TN1

3 Switching Waveforms and Test Circuit TN1 INPUT 1V V 1% 9% Pulse Generator VDD R L OUTPUT t (ON) t (OFF) R GEN t d(on) t r t d(off) t f OUTPUT VDD 1% 1% INPUT D.U.T. V 9% 9% Doc.# DSFP-TN1 3

4 Typical Performance Curves TN Output Characteristics 3.75 Saturation Characteristics 3. = 1V V 6V = 1V 8V 6V.75 V.75 V V 1 3 Transconductance vs. Drain Current.75 = 5V V Power Dissipation vs. Case Temperature 5 ( = 5 O C).6 = -55 O C G FS (siemens).5.3 = 5 O C = 15 O C P D (watts) 3 TO-3AA T C ( O C) 1 Maximum Rated Safe Operating Area 1. Thermal Response Characteristics. (DC) TO-3AA (DC).1 ( = 5 O C) Thermal Resistance (normalized) TO-3AA P D = 1.6W = 5 O C t P (seconds) P D = 1.W T C = 5 O C Doc.# DSFP-TN1

5 TN1 Typical Performance Curves (cont.) 1.3 BS Variation with Temperature 1 On-Resistance vs. Drain Current = 5.V 1. 8 BS (normalized) (Ω) 6 = 1V T j ( O C) 1 3. Transfer Characteristics = 5V = -55 O C V (th) and R DS Variation with Temperature O C O C (th) (normalized) V,.5A 1..8 (normalized) Capacitance vs. Drain-to-Source Voltage 1 f = 1MHz T j ( O C) Gate Drive Dynamic Characteristics 1 = 1V pF C (picofarads) 5 C ISS 6 V 5 C OSS C RSS 1 3 5pF Q G (nanocoulombs) Doc.# DSFP-TN1 5

6 3-Lead Package Outline (N3) D TN1 Seating Plane 1 3 A L e1 e Front View b c Side View E1 1 3 E Bottom View Dimensions (inches) Symbol A b c D E E1 e e1 L MIN NOM MAX * JEDEC Registration. * This dimension is not specified in the JEDEC drawing. This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-3TO9N3, Version E19. Doc.# DSFP-TN1 6

7 3-Lead TO-3AA (SOT-89) Package Outline (N8) TN1 D D1 C E H E1 L 1 3 b e e1 b1 A Top View Side View Dimensions (mm) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the (website: http//) 13 All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-TN1 Symbol A b b1 C D D1 E E1 e e1 H L MIN NOM BSC BSC - - MAX JEDEC Registration TO-3, Variation AA, Issue C, July This dimension differs from the JEDEC drawing Drawings not to scale. Supertex Doc. #: DSPD-3TO3AAN8, Version F Bordeaux Drive, Sunnyvale, CA 989 Tel:

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