Normally-Off GaN Field Effect Power Transistors: Device Design and Process Technology Development

Transcription

1 Center for High Performance Power Electronics Normally-Off GaN Field Effect Power Transistors: Device Design and Process Technology Development Dr. Wu Lu ( , Dr. Siddharth Rajan ( , Department of Electrical and Computer Engineering Sept 19 th, 2014

2 Leading Faculties Dr. Wu Lu Professor Semiconductor device physics and design Advanced semiconductor processing technologies Device characterization and modeling Energy storage devices Dr. Siddharth Rajan Associate Professor Nano-scale semiconductor devices Molecular beam epitaxy III-nitride semiconductors. 2

3 Research Programs on Nitride Semiconductor Materials and Devices Crystal growth and epitaxy (Rajan, Myers) Process science and advanced device fabrication technologies (Lu, Rajan) Metal contacts Process-induced defects Nanoscale,e-beam lithography; deep UV; ICP RIE plasma etching High frequency, high power, low noise GaN HEMTs Material characterization (Ringel, Brillson, Arehart) Structural, electronic, optical, chemical, in-situ & ex-situ measurements Development of new techniques at nanometer resolution Interface physics (metal-ceramic, dielectric-semiconductor) Device modeling, testing and circuit design (Lu, Roblin, Wang) Small and large signal RF testing/modeling Pulsed IV, RF measurements; nonlinear mwave; thermal modeling 3

4 Normally-off GaN-based Power FETs Key requirements of solid-state power devices - Higher breakdown voltage - Lower on-resistance - Higher operation current - Normally-off channel - Higher switching speed Therefore, normally-off GaN-based FETs Two strategies for normally-off GaN-FETs 1 Design of new Ga-faced or N-faced heterostructures for normally-off channel 2 Development of key process technologies for GaN power transistors 4

5 Frontend Processing Technologies 5

6 Manufacturable Ohmic Contacts for GaN Power Transistors Plasma processing to generate a thin layer of n+ region to promote carrier tunneling 6

7 Requirements for Gate Recess 1. Controllability Slow etch rate High selectivity (some applications) 2. Minimal damage 3. Smooth surface morphology 4. Uniformity 7

8 Excellent Etch Rate Control, Selectivity, Smoothness 12 Etch depth (nm) GaN cap thickness 4-5 nm/min Etch time (min) [6] M. Schuette et al., J. Vac. Sci. Technol. B. 25 p (2010). 8

9 Diode C-V Electron density (cm -3 ) nm recessed non-recessed Schottky interface V max = +3 V Depletion width (nm) 2DEG shifted 11 nm toward surface Cap layer precisely removed after 70% overetch n + -GaN cap fully depleted 9

10 -Pinchoff voltage (V) Diode C-V, I-V 2DEG density (10 12 cm -2 ) C-V extractions Plasma exposure time (min) Threshold voltage control Current density (A/cm 2 ) 10 3 reference 6 min 18 min Not etched Etched Applied bias (V) Reduced leakage current 10

11 V T & G m,max distribution vs R at 0 V and I D at 10 V Note that R at 0V and I D at 10 V were measured between source & drain after gate recess & before gate metallization Threshold voltage & G m,max vs Resistance at V DS = 0 V Threshold voltage & G m,max vs I D at V DS = 10 V V T (V) I D (ma/mm) R ( ) at V DS = 0 V Gm (ms/mm) I D (ma/mm) Gm,max (ms/mm) V T (V) I D (A) at V DS 10 V Gm (ms/mm) I D (ma/mm) Gm,max (ms/mm) Gm (ms/mm) V GS (V) V GS (V) V GS (V) 0 11

12 Why Gate dielectric is necessary in GaN Power FETs? Why MIS structures? - To reduce gate leakage current (various oxides, SiNx) - To increase a gate voltage swing - To improve thermal stability - To reduce trap density (~10 11 ev 1 cm 2 with Al 2 O 3 ) * Why Al oxides? - Large dielectric constant (8.6~ 10), large bandgap (~9 ev) - high breakdown field (5 ~ 60 MV/cm) - thermal & chemical stability ** * P. Kordos et al., Appl. Phys. Lett. (2009) Ref 1 ) Y. Q. Wu et al., App.. Phys. Lett. 90, (2007) 12

13 Al 2 O 3 /GaN Energy band line-up metal Al 2 O 3 GaN Flat band voltage Linear fit: V FB = x10 6 t ox (cm) Flat band in GaN is not flat-band in oxide φ b = 3 ev φ s = ev Conduction band offset ΔE c = 2.12 ev (matches theory and other measurements) Oxide field F ox = 0.51 MV/cm Esposto et al., Appl. Phys. Lett. 99, ,

14 Al 2 O 3 /GaN interface charges σ fix = σ metal + σ sp_gan metal Al 2 O 3 GaN Total fixed charge = x10 13 cm -2 Total fixed charges (σ fix ) induce electrical field in the dielectric Increase leakage current Interface fixed charge is greater than just the polarization charge! Positive charge prevents normally off FETs by shifting threshold in the negative direction σ metal σ fix σ sp_gan 14

15 Remote Ionized Impurity Scattering Fixed charges S G Dielectric AlGaN D d GaN Fixed charges (~ cm -2 ) cause remote ionized impurity scattering Polarization charges do not act as scattering centers When charges are close to the 2DEG the effect is more severe 15

16 Remote Ionized Impurity Scattering Fixed charges S G Dielectric AlGaN D d GaN Remote impurity scattering: Fixed charges (~ cm -2 ) cause remote ionized impurity scattering Polarization charges do not act as scattering centers When charges are close to the 2DEG the effect is more severe Proportional to fixed charge density Increases exponentially as distance is decreased 16

17 Remote impurity scattering n 2D = 1 x cm -2 n 2D = 5 x cm -2 n 2D = 1 x cm -2 n fix = 4 x cm -2 The regime of the interface charge density we expect Interfacial charge scattering reduces electron mobility significantly Remote impurity scattering becomes dominant as 2DEG density < 5x10 12 cm -2 Fixed charge density > 5x10 12 cm -2 Distance is lower than 10 nm Hung et al., Appl. Phys. Lett. 99,

18 Interface charge effects on devices n fix = 4 x cm -2 Interfacial charge scattering reduces electron mobility significantly Interface charge increases reverse gate leakage Interface charge prevents normally off operation It is important to reduce the positive charge density in oxide/iii-nitride interfaces Hung et al., Appl. Phys. Lett. 99,

19 Oxygen Plasma Treatment Recessed MISHEMT Capacitance ( F/cm 2 ) O 2 Plasma (n fix = 1.6 x10 13 cm -2 ) (a) O 2 Plasma and PMA (n fix = 8x10 12 cm -2 ) V g (V) Mobility (cm 2 V -1 s -1 ) Theory (n fix = 8x10 12 cm -2 ) 400C PMA (b) No PMA 20 nm Al 2 O 3 Al 0.3 Ga 0.7 N AlN GaN 5x DEG density (cm -2 ) 9nm 9 nm recesed AlGaN/AlN cap layer Both oxygen plasma and PMA were applied. Interface fixed charges were reduced to 8x10 12 cm -2 after O 2 plasma and PMA. Mobility rises after PMA, close to theory. 19

20 Oxygen plasma treatment Normally-off MISHEMT Current density (A/mm ) (a) S (c) um 0.4 um 2 um 0.4 um G native oxide GaN I ds I gs Capacitance (uf/cm 2 ) 20 nm Al 2 O 3 Al 0.3 Ga 0.7 N AlN D I d (ma/mm ) V g (V) V~0.25V I d (ma/mm ) V g (V) V g (V) (d) V ds = 7 V (b) Vg = 0V ~ 10V V = +2V over recessed V d (V) g m (ms/mm ) - Thin AlN left after recess etch - O 2 plasma + PMA treatments - 20 nm ALD Al 2 O 3 - Normally-off MISHEMT - V th = +1.5 V (at V ds = 10 ua/mm) - Saturation I ds >140 ma/mm - Maximum g m = 40 ms/mm Hung, Ting-Hsiang, et al. Applied Physics Letters (2013):

21 Backend Processing Technologies 21

22 Deep Etching of Si Structures Cryo-Process F-based chemistry; High etch rate (2~3 um/min) A clean process; Aspect ratio is temperature dependent. 22

23 High Aspect Ratio Si trench and Via Etch Etch rate 2.2mm/min, 100mm etch depth, 20:1 aspect ratio, 90º+/- 0.25ºsidewall angle. Etch Rate 2µm/min 200µm etch depth 40:1 aspect ratio >75:1 selectivity to photoresist >200:1 selectivity to oxide 23

24 Backside SiC Via Etching SiC via hole etched by ICP-RIE F- or Cl- Based chemistries High etch rate Hard mask required 24

25 Deep Dry Etching of III-Nitrides Etch profile obtained in AlGaN/GaN double heterostructure layer by ICP-RIE. Etch profile obtained in AlGaN/GaN double heterostructure layer by CAIBE. 25

26 Summary Normally-off GaN HEMTs can be designed for high frequency power switching applications with several critical issues being taken care. GaN transistors have great potential for power electronics but significant developments are still required. 26

27 Center for High Performance Power Electronics Questions? Department of Electrical and Computer Engineering