2D-2D tunneling field effect transistors using

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1 2D-2D tunneling field effect transistors using WSe 2 /SnSe 2 heterostructures Tania Roy, 1,2,3 Mahmut Tosun, 1,2,3 Mark Hettick, 1,2,3, Geun Ho Ahn, 1,2,3 Chenming Hu 1, and Ali Javey 1,2,3, 1 Electrical Engineering and Computer Sciences, University of California, Berkeley, CA, Materials Sciences Division, Lawrence Berkeley National Laboratory, Berkeley, CA Berkeley Sensor and Actuator Center, University of California, Berkeley, CA, Corresponding Author: ajavey@eecs.berkeley.edu Supporting Information S1

2 S1. Fabrication process Fig. S1. Device design. a. Fabrication process of WSe 2 /SnSe 2 heterojunction tunnel FET. (i) E-beam evaporation of gate electrode. (ii) Atomic layer deposition of ZrO 2 as gate dielectric. (iii) Dry transfer of WSe 2 /SnSe 2 heterostack. (iv) E-beam evaporation of Pd source/drain contacts. b. Optical microscope image of a representative WSe 2 /SnSe 2 TFET. Scale bar = 5 µm. On a Si/SiO 2 substrate, the bottom gate electrode is patterned using electron beam (e-beam) lithography, followed by e-beam evaporation and liftoff of 50 nm Ni, as shown in Fig. 1(a-i). ZrO 2 is deposited as the gate dielectric by atomic layer deposition. The thickness of ZrO 2 is varied between 8 nm and 20 nm. WSe 2 and SnSe 2 are purchased from commercial vendors (HQGraphene and 2D Semiconductors, respectively), and flakes are exfoliated onto Si/SiO 2 substrates. The flake thicknesses are first determined by optical contrast and confirmed by atomic force microscopy. The WSe 2 flakes selected for device fabrication are between 3 and 6 layers of thickness. The SnSe 2 flakes chosen are ~ 10 nm thick. The SnSe 2 flake of interest is dry-transferred onto the WSe 2 flake of interest, using a pick-and-place transfer method. 27 The WSe 2 /SnSe 2 heterostack formed is then transferred onto the gate stack. Ti/Pd (1 nm/50 nm) source/drain contacts are patterned using e-beam lithography and evaporation. S2

3 S2. Electrical characterization of SnSe 2 Fig. S2. SnSe 2 electrical characterization. a. I D -V G of SnSe 2 FET with flake thickness 2 nm, as a function of temperature. b. I D -V D of same device at 100 K and 300 K. c. R total vs. V GS for SnSe 2 FET Figure S2a shows the temperature dependent I D -V G characteristics of an SnSe 2 FET on 8 nm ZrO 2 gate. The device dimensions are: L = 1.6 µm, W = 4 µm. The drain current shows very little gate control at all temperatures. Figure S2b shows the I D -V D characteristics at 100 K and 300 K, for varying V G. The field effect mobility of SnSe 2 is μ FE = di D /dv G.(L/WC ox V DS ), at V DS = 0.05 V. For a ZrO 2 gate dielectric of 8 nm, with an estimated dielectric constant of 18, μ FE is calculated to be ~5 cm 2 /V-s. The 2D sheet carrier density can be extracted to ~10 13 cm -2. Figure S2c shows the R total vs. V GS of the same SnSe 2 FET. The contact resistance of SnSe 2 FET can be estimated using the same model as in Ref [1]. The total resistance of the channel can be expressed as R tot = R channel + 2 R c, where R channel is the resistance of the channel and R c is the contact resistance. At high gate voltages, R c, which is assumed to be independent of the gate voltage, dominates the total resistance, since R channel is low in those conditions. R tot is obtained from V D /I D at V D = 0.08 V. The total resistance V D /I D is a sum of the 2 contact resistances and the channel resistance for varying gate voltages. Since only a limited number of S3

4 data points were available for gate voltage, V GS, the R tot vs. V GS curve is extrapolated using the exponential function y=y 0 +Aexp(-x/x 0 ) where the fitting parameters are: y 0 = = 2R c ; A = ; x 0 = Thus, the contact resistance can be estimated to be ~3.8 kω. S3. Materials characterization of SnSe 2 Fig. S3. SnSe 2 materials characterization. a. XPS spectra of Se 3d core level. b. XPS spectra of Sn 3d core level. Figure S3 shows the Se3d and Sn3d core photoelectron spectra, indicating slight oxidation of Se atoms but little oxidation of Sn as shown by Voigtian fits of the core level peak components. S4

5 S4. WSe 2 electrical characterization Fig. S4. Electrical characterization of a 3-layer thick WSe2 FET. a. I D -V G at 300 K. b. I D -V G as a function of temperature showing increasing subthreshold swing with temperature. Figure S4a shows the I D -V G at low and high drain voltage for a WSe 2 FET with Pd contacts. The WSe 2 FET shows ambipolar characteristics. Figure S4b shows the temperature dependence of I D -V G of the WSe 2 FET. A high dependence of SS on temperature is noticeable. S5. Electrical performance of WSe 2 /SnSe 2 heterojunction TFET Fig. S5. Electrical characteristics of a WSe 2 /SnSe 2 heterojunction p-tfet at 300 K, with 20 nm thick ZrO 2 gate dielectric. a. I D -V G. b. Subthreshold swing vs. I D c. I D -V D with varying V G S5

6 Figure S5 shows the electrical characteristics of a WSe 2 /SnSe 2 heterojunction TFET, different from the one shown in Fig 3 of main text. This device was fabricated on a ZrO 2 gate of 20 nm thickness. References 1. Roy, T.; Tosun, M.; Kang, J. S.; Sachid, A. B.; Desai, S. B.; Hettick, M.; Hu, C. C.; Javey, A. Field-Effect Transistors Built from All Two-Dimensional Material Components. ACS Nano 2014, 8, S6