ECE Semiconductor Device and Material Characterization

Transcription

1 EE 483 emiconductor Device and Material haracterization Dr. Alan Doolittle chool of Electrical and omputer Engineering Georgia Institute of Technology As with all of these lecture slides, I am indebted to Dr. Dieter chroder from Arizona tate niversity for his generous contributions and freely given resources. Most of (>80%) the figures/slides in this lecture came from Dieter. ome of these figures are copyrighted and can be found within the class text, emiconductor Device and Materials haracterization. Every serious microelectronics student should have a copy of this book!

2 Why do we need to know about Nano-electronic materials details? A ase study of the evolution of the Transistor Moore s Law: The Growth of the emiconductor Industry Moore s law (Gordon Moore, co-founder of Intel, 965): Empirical rule which predicts that the number of components per chip doubles every 8-24 months Moore s Law turned out to be valid for more than 30 years (and still is!)

3 Why do we need to know about Nano-electronic materials details? A ase study of the evolution of the Transistor Moore s Law: The Growth of the emiconductor Industry > Billion Transistors 2000 Transistors

4 Why do we need to know about Nano-electronic materials details? A ase study of the evolution of the Transistor Transistor functionality scales with transistor count not speed! peed is less important. from G. Moore, I 2003

5 Why do we need to know about Nano-electronic materials details? A ase study of the evolution of the Transistor How did we go from 4 Transistors/wafer to Billions/wafer? IBM 200 mm and 300 mm wafer mm First Planar I 96, Fairchild mm

6 Why do we need to know about Nano-electronic materials details? A ase study of the evolution of the Transistor lide after Dr. John ressler

7 The Basic Device in MO Technology is the MOFET Direction of Desired urrent flow is controlled by an electric field but this field can also drive current through a small gate. Modern (pre- 2009) transistors have more power loss in the gate circuit than the source - drain! New approaches are needed.

8 Why do we need to know about Nano-electronic materials details? A ase study of the evolution of the Transistor Early MOFET: io 2 Gate Oxide, Aluminum (Al) ource/drain/gate metals Problem: As sizes shrank, devices became unreliable due to metallic spiking through the gate ide. olution: Replace Metal Gate with a heavily doped poly-silicon. This change carried us for decades with challenges in fabrication (lithography) being the primary barriers that were overcome until

9 Why do we need to know about Nano-electronic materials details? A ase study of the evolution of the Transistor emi-modern MOFET (late 990 s vintage): io 2 Gate Oxide, Polysilicon gate metals, metal source/drain contacts and Aluminum metal interconnects Problem: As interconnect sizes shrank, Aluminum lines became too resistive leading to slow R time constants olution: Replace Aluminum with multimetal contacts (TiN, TaN, etc ) and copper interconnects. This change carried us for ~ decade with challenges in fabrication (lithography) being the primary barriers that were overcome until

10 Why do we need to know about Nano-electronic materials details? A ase study of the evolution of the Transistor Microprocessor Power onsumption Gates became so thin that the leakage currents through the thin Gate insulator consumed more power than the drainsource circuit! Gate A new approach is needed! from G. Moore, I 2003

11 Why do we need to know about Nano-electronic materials details? A ase study of the evolution of the Transistor from G. Moore, I 2003 D D insulator I insulator k Gate Leakage kinsulator E Gate leakage current can be dramatically lowered by increasing Gate insulator V Gate thickness but to do so without changing the insulator t channel conductivity, you have to increase Gate the dielectric constant of the insulator. t e Gate NEW GATE INLATOR FOR THE FIRT TIME IN 60 YEAR!!!!

12 2008 Vintage Intel Microprocessor 45 nm (~200 atoms) Hafnium- ilicate (Oxide) trained i (lower bandgap higher mobility)

13 2008 Vintage Intel Microprocessor 45 nm (~200 atoms) High K Gate Dielectric: K of io 2 ~3.9< Hafnium ilicate ~? < HfO 2 ~ 22 Deviation from io 2 required reverting back to Metal Gates (no Poly-silicon) Limited peed of ilicon partially overcome by using ige to mechanically strain i channel resulting in Energy Band structure modification that increases electron/hole mobility. trained i (lower bandgap higher mobility) Hafnium- ilicate (Oxide)

14 trained ilicon MOFET from IEEE pectrum, 0/2002 ilicon in channel region is strained in two dimensions by placing a i-ge layer underneath (or more recently adjacent to) the device layer trained i results in changes in the energy band structure of conduction and valence band, reducing lattice scattering Benefit: increased carrier mobility, increased drive current (drain current) lide after Dr. Oliver Brandt

15 What is in the future? Double-Gate Transistors hange of basic transistor structure by introducing a double gate (or more general enclose the channel area by the gate) Benefit: better channel control resulting in better device characteristics hallenge: double-gate transistors require completely new device structures with new fabrication challenges lide after Dr. Oliver Brandt from IEEE pectrum, 0/2002

16 Double-Gate Transistor Designs hannel in chip plane hannel perpendicular to chip plane with current flow in chip plane (FinFET) hannel perpendicular to chip plane with current flow perpendicular to chip plane lide after Dr. Oliver Brandt from IEEE pectrum, 0/2002

17 FinFET Double-Gate Transistor lide after Dr. Oliver Brandt from

18 Vertical multi-gate structures take us back to JFET like structures but now with the advantage of insulators. Life is circular

19 io 2 and io 2 /i Interface i, i/io 2 interface, io 2 bulk, and ide defect structure A: i-i Bond (Oxygen Vacancy) Hydrogen D B: Dangling Bond : i-h Bond D: i-oh Bond A B Oxygen Dangling Bond i

20 QV Oxide harges / Interface Traps + (4) + (3) io 2 x + + x + x + x () (2) i harge Type Location ause Effect on Device ) D it (cm -2 ev - ), N it (cm -2 ), Q it ( /cm 2 ) Interface Trapped harge io 2 /i interface Dangling Bond, Hot electron damage, contaminants Junction Leakage urrent, Noise, Threshold Voltage hift, ubthreshold lope 2) N f, Q f (cm -2, /cm 2 ) Fixed harge lose to io 2 /i interface i + (?) Threshold Voltage hift 3) N ot, Q ot (cm -2, /cm 2 ) Oxide Trapped harge In io 2 Trapped electrons and holes Threshold Voltage hift 4) N m, Q m (cm -2, /cm 2 ) Mobile harge In io 2 Na, K, Li Threshold Voltage hift (time dependent)

21 QV ) Interface Trapped harges + (4) + (3) io 2 x + + x + x + x () (2) i an be either positive or negative charge Due to: tructural Defects Oxidation Induced Defects Metallic Impurities Radiation induced broken bonds Radiation induced broken bonds an be drastically improved by a low temperature (~450 ) anneal in a Hydrogen bearing gas.

22 QV 2) Fixed Oxide harges + (4) + (3) io 2 x + + x + x + x () (2) i Generally positive charge and is related to idation conditions: Increases with decreasing idation temperature an be reduced to a fixed (minimum value) by anneals in inert gases an be effected by rapid cooling

23 QV 3) Oxide Trapped harges + (4) + (3) io 2 x + + x + x + x () (2) i an be either positive or negative charge Due to electrons or holes trapped in the ide: Ionizing radiation (~>9 ev) Tunnel currents Breakdown

24 QV 4) Mobile harges + (4) + (3) io 2 x + + x + x + x () (2) i Generally positive (sometimes negative but generally limited mobility if negative) Due to contaminants (Na, K, Li) in the ide: Gate voltage slowly drives the charge across the ide changing the threshold voltage and capacitance characteristics an lead to hysteresis in the V curve an lead to time dependent threshold voltages

25 MO apacitor MO apacitor (MO-) can be used to determine Oxide charge Interface trapped charge Oxide thickness Flatband voltage Threshold voltage ubstrate doping density Generation lifetime Recombination lifetime

26 MO apacitor MO capacitor cross section and band diagram V G 0 t t +W x Voltage drop across ide V V G φ φ F E c /q E i /q E F /q E v /q urface Potential Total Gate Voltage V FB +V +φ

27 MO apacitor apacitance consists of : ide capacitance p : accumulation capacitance b : bulk (space-charge region) capacitance n : inversion capacitance it : interface trap capacitance Is generally given in units of Farads/cm 2 p p b n it

28 The capacitance is The charge is MO apacitor dq dv G G Assuming no ide charge, gate charge (-) semiconductor and interface charge This gives Q Q Q + G dq dv G G dv dq + dq s s it dqs + dq dv it G + dq ( Qp + Qb + Qn Qit p it dq dv Math dφs + dq + dq b s + dqit + dφ n ) s + dq it Hole, space charge, electron, and interface charge densities. Because V FB is fixed + p + b + n + it

29 Accumulation p >> Total ~ Depletion MO apacitance Inversion low frequency n >> Total ~ Inversion high frequency b < > it Total < b Total < p b n it p b n it p b n it p b n it Accumulation: Negative V G draws holes toward interface (Large Q p p V G ) Accumulation Depletion: Positive V G pushes holes away from interface (small Q p,n p,n V G ) Q b -qn A W ( b >> it ) b Depletion it Inversion: large Positive V G inverts surface region (Large Q n n V G dominates over b and it ) Inversion - lf HF: When excitation is significantly faster than the generation lifetime b Inversion - hf

30 Accumulation p >> Total ~ Depletion b < > it Total < MO apacitance Inversion low frequency n >> Total ~ Inversion high frequency b Total < Accumulation Depletion LF Inversion, HF Inversion (V A test faster than /τ Generation ) or Deep Depletion (V bias swept faster than τ Generation ) LF Inversion, HF Inversion (V A test faster than /τ Generation ) or Deep Depletion (V bias swept faster than τ Generation ) Depletion Accumulation / 0.8 FB / lf hf 0.2 p-ubstrate dd Gate Voltage (V) Total ~ in LF Inversion and Accumulation No inversion charge in deep depletion + / hf lf FB / 0.2 dd n-ubstrate Gate Voltage (V)

31 MO apacitance Generally omplex Mathematics ( ) ( ) [ ] ( ) F Di s lf F e e e e L K F F, 2 ˆ 0, + ε ( ) ( ) ( ), + + F e e e e F F F i s Di n q kt K L q kt 2 0 s 2 ; / ; ˆ ε φ ( ) ( ) ( ) [ ] ( ) F Di s hf F e e e e L K F F, 2 ˆ 0, ε + δ + ( ) ( ) ( )( ) ( ) [ ] F F F d F e e e F e 0 3, 2, δ ( ) [ ] 2 0, + V V V FB G dd

32 MO apacitance + V G V + φ + V V + φ FB FB + ˆ ktkstf( qk L Di, F ) / 0.8 FB / lf hf 0.2 p-ubstrate dd Gate Voltage (V) / hf lf FB / 0.2 dd n-ubstrate Gate Voltage (V)

33 Low-Frequency apacitance To measure the low-frequency -V G curve, the inversion carriers must be able to respond to both the ac gate voltage and the dc gate voltage sweep rate + ½ ycle of V G : Driven displacement current (gate) must be less than the available space charge (generation) current - ½ ycle of V G : Recombination is fast enough to not be an issue V G V G V G + V G V G V G - V G W Generation J scr W Recombination W 2 W > W > W 2 J scr qn W dv dv qn W in µm 0.046Wt in nm i G G i Jdispl V s τ g dt dt τ g τ g in µs f eff v g dv dt G

34 Low-Frequency apacitance The effective frequency is < Hz Very difficult to measure the capacitance Measure current I dq dt dq dv G dv dt G dv dt G or I ~ / With D it / With D it Gate Voltage (V) Gate Voltage (V)

35 Flatband Voltage (and apacitance) Most Junior level classes assume: A metal can be selected that aligns perfectly with the fermi-level in the semiconductor No charges exist in the Oxide These are generally not true (once again, we lied to you), leading to a pre-bias on the device This shifts the V urve and requires a voltage be applied to obtain flat band conditions. To determine V FB, one must compare the measured to theoretical V curves and thus must know the theoretical flatband capacitance

36 Flatband apacitance The flatband voltage is that gate voltage at which the capacitance is the flatband capacitance K ε K ε kt K ε kt, FB FB ;, FB ; LD 2 2 +, FB LD q ( p + n) q NA FB / N A (cm -3 ) 000 nm 500 nm 200 nm 00 nm 50 nm 20 nm 0 nm 7 nm 5 nm 3 nm t 2nm

37 Flatband Voltage Flatband voltage depends on various gate, semiconductor, and ide parameters V FB t t Q f φm Mobile 0 0 ( x t ) ρ ( x) dx ( x t ) ρ ( x) OxideTrapped Qit dx ( φ ) Weighted sum (integral) accounts for how far away the charge is from the idesemiconductor interface. No effect on V FB γ trong γ effect on V FB t x 0 t x

38 Work Function Difference The work function difference, φ M, depends on the Fermi level of the gate (polysilicon) and the substrate Assuming the gate is degenerately doped (i.e. fermi level is in the majority carrier band φ M φ M φ φ F ( gate) φ ( substrate) F E g /2q E g /2q φ F E V FB E i E F E V V FB n + Gate E F E φ F p + Gate E F E V

39 Q f, φ M Measurements Assume Q m Q ot Q it 0 V FB φ M Q f φ M qn K f ε 0 t Measure and plot V FB versus t 0.8 FB / / V FB Ideal Gate Voltage (V)

40 Mobile harge Bias-temperature stress (BT) Apply positive gate voltage to produce ε 0 6 V/cm at T for t 5-0 min. ool device with applied voltage; measure -V G at room temperature Repeat with negative gate voltage The gate voltage shift, V FB, between the two curves is due to mobile charge / Gate Voltage (V) Q V m FB

41 Mobile harge Triangular voltage sweep MO- is held at T High-frequency - V G and low-frequency I - V G measured V G V G I lf α dv I G I dq dt G dv lf ( α dt α FB ) { V [ t( V )] V [ t( V )]} FB G2 Q α { V [ t( V )] V [ t( V )]} α FB G2 FB G FB m G V G V G I lf α dvg αq m

42 Mobile harge Triangular Voltage weep (TV) Measure hf and lf -V G curves simultaneously at T 200 Q m area between lf and hf curves uitable for gate ides and interlevel dielectrics apacitance (pf) 900 N m.3x0 0 cm lf 4.x0 9 cm t 00 nm hf Gate Voltage (V) apacitance (pf) T , Gate Voltage (V) Q m VG V 2 G ( lf hf ) dv G

43 Interface Trapped harge Quasi-static method High-frequency and low-frequency -V G curves are measured lf + + it lf 2 q q lf Dit 2 VG 2 lf φs dv G + V G it / ' lf (with D it ) lf (ideal) hf Gate Voltage (V) hf hf D it q 2 lf / lf / hf / / hf

44 Quasistatic Method urrent flow through ide causes Interface state generation Oxide charge trappping 0 3 / After tress Before tress D it (cm -2 ev - ) After stress Before stress Gate Voltage (V) urface Potential (V). Data courtesy of W. Weishaar, Arizona tate niversity

45 Interface Trapped harge harge Pumping ses MOFET Apply periodically varying gate voltage Measure resulting current at the substrate or source/drain V G t V G t V R V R n n V R n n V R p p I cp I cp (a) (b)

46 harge Pumping th n e N v kt E E σ τ ) ) ( exp( f N v kt E E th n 2 ln σ s th p c p v σ τ f N v kt E E V th p V 2 ln 2 σ + f N v f N v kt E E V th p th n g 2 ln 2 ln σ σ E E V E To /D hannel Trapped electrons Hole Barrier ( ) [ ] T G it G cp V V E qd f A I + α

47 Bilevel harge Pumping Keep baseline constant, vary pulse height Vary baseline, keep pulse height constant I cp b Weak Accumulation b c d I cp Weak Inversion a V a V base V FB V T e a b a V b c d e V

48 MOFET ubthreshold I D - V G Below V T, I D depends exponentially on V G lope change due to stress is very small for thin ides I D I o e q( V V ) / nkt 2 s + q Dit n + q( NAW + qd + Kε o x0 ( N G T it A ) t W + D it ) t Drain urrent (A) Before tress V T After D it 5x0 cm -2 ev Gate Voltage (V) D it 2.3kT lope After lope Before

49 Review Questions Name the four main charges in the ide How is the low-frequency capacitance measured? What is the flatband voltage and flatband capacitance? Describe charge pumping. How does the subthreshold slope yield the interface trap density?