Ultra-Scaled InAs HEMTs

Transcription

1 Performance Analysis of Ultra-Scaled InAs HEMTs Neerav Kharche 1, Gerhard Klimeck 1, Dae-Hyun Kim 2,3, Jesús. A. del Alamo 2, and Mathieu Luisier 1 1 Network for Computational ti Nanotechnology and Birck Nanotechnology Center, Purdue University 2 Microsystems s Technology ogy Labs, Massachusetts Institute of Technology 3 Teledyne Scientific & Imaging, LLC

2 Motivation: Towards III-V MOSFET Strained channel New gate dielectrics Device geometries Channel materials High-k dielectrics Research III-V channel devices Acknowledgement: Robert Chau, Intel Low-power & high-speed

3 Motivation: Why III-V HEMTs? III-V: Extraordinary electron transport t properties HEMTs: Very similar structure to MOSFETs except high-κ dielectric layer Excellent to Test Performances of III-V material without interface defects Excellent to Test Simulation Models Develop simulation tools and benchmark with experiments Predict performance of ultra-scaled l devices 2007: 40nm 2008: 30nm D.H. Kim et al., EDL 29, 830 (2008)

4 Motivation Modeling Approach Outline Real-space EM simulator including gate leakage Atomistic tight-binding m* Realistic description of simulation domain (gate geometry) Comparison to Experiments L g =30, 40, 50nm Material parameters, I d -V gs, I d -V ds Scaling Considerations for L g=20nm Channel thickness, Insulator thickness, Gate metal work function HEMT Simulator on nanohub.org Conclusion and Outlook

5 Motivation Modeling Approach Outline Real-space EM simulator including gate leakage Atomistic tight-binding m* Realistic description of simulation domain (gate geometry) Comparison to Experiments L g =30, 40, 50nm Material parameters, I d -V gs, I d -V ds Scaling Considerations for L g=20nm Channel thickness, Insulator thickness, Gate metal work function HEMT Simulator on nanohub.org Conclusion and Outlook

6 Device Geometry and Simulation Domain Extrinsic device L g Source Drain n+ Cap n+ Cap InP etch stop R InAlAs S Source InP Substrate Gate InAs InGaAs Simulation Domain: Intrinsic device Drain δ-doped layer R D Intrinsic i device Near gate contact Self consistent 2D Schrodinger-Poisson Electrons injected from all contacts M. Luisier et. al., IEEE Transactions on Electron Devices, vol. 55, p. 1494, (2008). Extrinsic source/drain contacts t Series resistances R S and R D R. Venugopal et.al., Journal of Applied Physics, vol. 95, p. 292, (2004).

7 Gate Geometry and Gate Leakage Current 1 (a) 3 2 (b) Flat Gate 1) Include series resistances ext Vgs V int ext gs IdRs V V int ds ds I d R s R d 2) Include gate leakage current S ( E H D G ) C ( S 3) Include the proper gate geometry flat (a) or curved (b) S S D S G ) Curved Gate Gate leakage reduced in curved gate device

8 Accurate Effective Mass Calculation Full-Band Transport: Strain, Disorder, Nonparabolicity, BTBT No gate leakage, Computationally very intensive Import m* Effective Mass Transport: Gate leakage, Computationally efficient Parabolic bands, No disorder, Wrong quantization levels ~ 4 nm

9 Motivation Modeling Approach Outline Real-space EM simulator including gate leakage Atomistic tight-binding m* Realistic description of simulation domain (gate geometry) Comparison to Experiments L g =30, 40, 50nm Material parameters, I d -V gs, I d -V ds Scaling Considerations for L g=20nm Channel thickness, Insulator thickness, Gate metal work function HEMT Simulator on nanohub.org Conclusion and Outlook

10 Transfer Characteristics: I d -V gs Parameter Initial Final parameter set L g [nm] 30, 40, t ins [nm] Φ M [ev] m* ins (InAlAs) m* buf (InGaAs)

11 Output Characteristics: I d -V ds Conclusion: Good agreement for all L g s Less ballistic at L g =50nm Use models and material parameters to design ultra- scaled devices (L g =20nm)

12 Motivation Modeling Approach Outline Real-space EM simulator including gate leakage Atomistic tight-binding m* Realistic description of simulation domain (gate geometry) Comparison to Experiments L g =30, 40, 50nm Material parameters, I d -V gs, I d -V ds Scaling Considerations for L g=20nm Channel thickness, Insulator thickness, Gate metal work function HEMT Simulator on nanohub.org Conclusion and Outlook

13 What can be changed? Gate geometry Channel thickness scaling: t InAs Insulator thickness scaling: t ins Metal work function engineering: Φ M In 0.52 Al 0.48 As L g =20nm Gate Φ M Better control of surface potential Gate leakage reduction and E-mode operation Sou urce In 0.53 Ga 0.47 As InAs t InAs t ins Dr rain

14 InAs (Channel) Layer Thickness I OFF increases Gate InAs Channel Scaling: Better electrostatic control lower SS larger I ON /I OFF ratio Increase of transport m* reduced v inj, higher N inv => higher I ON Increase of gate leakage current I ON /I OFF ratio saturates Sou urce In 0.53 Ga 0.47 As InAs t InAs Dr rain In 0.52 Al 0.48 As

15 InAlAs (Insulator) Layer Thickness gate leakage Gate InAlAs Insulator Scaling: Better electrostatic control (due to larger C ox ) Increase of gate leakage current larger I OFF larger SS smaller I ON /I OFF ratio Sou urce In 0.53 Ga 0.47 As InAs t ins Dr rain In 0.52 Al 0.48 As

16 Work Function Engineering Work Function Increase: Shift towards enhancement mode Decrease of gate leakage current Allows for thinner insulator layer steeper SS larger I ON /I OFF ratio

17 Parameters and Performances Summary (1) Gate (2) Channel (3) Insulator (4) Metal work geometry thickness thickness function Improved Higher gate Gate leakage gate control leakage reduction L g =20nm 1 SS I ON /I OFF

18 Motivation Modeling Approach Outline Real-space EM simulator including gate leakage Atomistic tight-binding m* Realistic description of simulation domain (gate geometry) Comparison to Experiments L g =30, 40, 50nm Material parameters, I d -V gs, I d -V ds Scaling Considerations for L g=20nm Channel thickness, Insulator thickness, Gate metal work function HEMT Simulator on nanohub.org Conclusion and Outlook

19 HEMT Simulator on nanohub.org OMEN_FET: 2-D Schrödinger-Poisson solver Real-space effective mass quantum transport t model Injection (white arrows) from Source, Drain, and Gate contacts HEMTs, Single- and Double-Gate devices Electron transport in Si and III-V Ballistic transport (no Scattering) Current Flow Visualization Run your own simulations!

20 Conclusion and Outlook Multiscale Modeling Approach EM transport including gate leakage m* from tight-binding Good Agreement with Experiments Scaling Considerations for 20nm Device HEMT Simulator Deployed on nanohub.orgorg Challenges and Future Directions S/D contacts, high-k insulator, scattering, interface traps Extrinsic device Simulation Domain: Intrinsic device L g =20nm V d =0.50 V V d =0.05 V

21 Thank You!

22 Transfer Characteristics: I d -V gs (2) L g [nm] SS [mv/dec] DIBL I ON /I OFF V inj [cm/s] [mv/v] 30 Expt Sim Expt Sim Expt Sim

23 Gate Leakage Mechanism Electrons tunnel from gate into InAs channel Tunneling barriers InAlAs and InGaAs Position dependent barriers Current crowding at edges (due to lower tunneling barriers) Barriers modulated by Φ M Φ M

24 Work Function Engineering (2) Φ M =4.7 ev Φ M =5.1 ev Characteristics: Same Gate Overdrive same thermionic current (source to drain) Gate Fermi levels shifted by Φ M different tunneling barrier height Φ M =4.7 ev tunnel through InAlAs only larger I g Φ M =5.1 ev tunnel through InAlAs and InGaAs lower I g