III-V Nanowire TFETs
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1 III-V Nanowire TFETs Lars-Erik Wernersson Lund Univeristy, Sweden Final Workshop 10 November 2017 Energy Efficient Tunnel FET Switches and Circuits imec 1
2 OUTLINE Status of III-V NW TFETs TFET Variability and Statistics Where are the Defects? Band Tails: The Myth, the Data, and a Model Conclusions Final Workshop 10 November 2017 Energy Efficient Tunnel FET Switches and Circuits 2
3 TFET Process VLS growth combined with top-down processing Digital etching - ozone surface oxidation - citric acid oxide etching Diameter scaling down to 11 nm Typical diameter 20 nm
4 TFET characteristics TFET benefits Higher drive current at V overdrive Option for power saving! j
5 Transfer Characteristics Sub 60 mv/decade operation at I DS ~ na/µm Good electrostatic control (DIBL 25 mv/v), 5 mv Hysteresis Gate-current <I DS /100 S min = 48 mv/dec at 0.3 V I 60 = 0.31 μa/μm at 0.3 V E. Memisevic et al., IEDM 2016
6 Variability among Devices Transfer characteristics of 10 TFETs 6
7 Variability among Devices Transfer characteristics of 10 TFETs Adjust Vt Shift! 7
8 Variability among Devices Transfer characteristics of 10 TFETs Yield varies with bias and number of NWs Adjust Vt Shift! 8
9 What is limiting I on? At V ds =0.1V I on is limited by S At V ds =0.3V? 9
10 What is limiting I on? At V ds =0.1V I on is limited by S At V ds =0.3V I on is limited by g m 10
11 Materials Characterization Nanowire with WZ-ZB InAs transition Slowly varying composition gradient with transition over about 20 nm Strong strain field within heterostructure (2-3%) 28% Sb in InGaAsSb E. Memisevic et al., Nano Lett 2017
12 Where are the Defects? Excellent fit by TCAD modeling (ETH) Bulk trap main contribution to leakage current Oxide traps have vanishing influence besides electrostatic effect E. Memisevic et al., Nano Lett 2017
13 Defects within the Oxide Multiple jumps detected in some IVs E. Memisevic et al., Nano Letters 2017 M. Hellenbrand et al ESSDERC 2017 Each event can be viewed as RTN Time constants fit with model of defects within oxide
14 Band Tails: The Myth, the Data, and a Model Excess current in Esaki diodes have been described by: I D,off =κ 2q h න T r (E)(fd fs)exp( E ) de E c E 0 It has been suggested that Esaki diodes may be used to evaluate TFETs
15 Band Tails: The Myth, the Data, and a Model Excess current in Esaki diodes have been described by: I D,off =κ 2q h න E c T r (E)(fd fs)exp( E E 0 ) de It has been suggested that Esaki diodes may be used to evaluate TFETs Representative value for Lund TFET Note S<<E 0!!! E. Memisevic et al., IEEE EDL 2017
16 S<<E o!!! I D,off =κ 2q h න E c T r (E)(fd fs)exp( E E 0 ) de S=(dlog(ID,off )dvg) 1 =2.3 kte 0 kt+e C it C ox If E 0 <<kt; S proportional to E 0 If E 0 >kt; S proportional to kt, although lower than 2.3 kt!!!
17 Thermal Excitation of Carriers into States Representative value for Lund TFET Note S<<E 0!!! Note that the temperature dependence is back! TFET Esaki Diode
18 What about Doping in the Channel? Valley current increases E 0 increases (> 100 mev) Bias dependent E 0 S increases S min 77 mv/dec
19 What about Doping in the Channel? Valley current increases E 0 increases (> 100 mev) Bias dependent E 0 S increases S min 77 mv/dec Impurities: One source of band tails Binding energy<e 0 Potential screened by E f Lund Conclusion: p + /n + diodes not good references!
20 TFET Model Can Be Used to Describe IV! Esaki Diode I D,off =κ 2q h න E c T r (E)(fd fs)exp( E E 0 ) de
21 Same LFN Mechanism Same channel/gate stack for MOSFETs and TFETs Electron trapping in gate oxide defects Channel potential fluctuations as main LFN mechanism Channel e - S ID 2 I = q2 k T λ N bt S f γ 2 L G W G C ox g m 2 I S 2 = S V fb g2 m 2 I S Defect-assisted tunnelling high-k TFETs MOSFETs Hellenbrand et al. EDL 2017
22 Different Affected Areas Same mechanism but different affected areas Same S Vfb L G W G Hellenbrand et al. EDL 2017
23 Conclusions III-V NW TFETs consistently delivers S < 60 mv/dec I on = V I on limited by slope (low V ds ) and g m (high V ds ) I DS = 92 μa/μm at V DS = V GS = 0.5 V Peak transconductance g m of 205 μs/μm at V DS = 0.5 V Device not so sensitive to defects (charging, TAT, band tails) Band Tails: Now included in a model to describe IV! Final Workshop 10 November 2017 Energy Efficient Tunnel FET Switches and Circuits
24 Thank you LU Erik Lind, Johannes Svensson, Mattias Borg, Lars Ohlsson Elvedin Memisevic, Markus Hellenbrand, Abinaya Adam Jönsson, Karl-Magnus Persson, Jun Wu, Martin Berg, Anil Dey, Cezar Zota, Aein Shiribabadi, Fredrik Lindelöv, Olli-Pekka Kilpi, Sebastian Heunisch Final Workshop 10 November 2017 Energy Efficient Tunnel FET Switches and Circuits imec 24
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