30 nm In 0.7 Ga 0.3 As Inverted-type HEMT with Reduced Gate Leakage Current for Logic Applications

Transcription

1 30 nm In 0.7 Ga 0.3 As Inverted-type HEMT with Reduced Gate Leakage Current for Logic Applications T.-W. Kim, D.-H. Kim* and J. A. del Alamo Microsystems Technology Laboratories MIT Presently with Teledyne Scientific Sponsors: Intel & FCRP-MSD Fabrication: MTL, NSL, SEBL IEDM December 7-9, 2009 Acknowledgements:MBE Technology for epi wafer UNIST in Korea for TEM analysis 1

2 Outline 1. Introduction 2. Device Technology 3. Logic Characteristics 4. Benchmarking with normal HEMT and Si CMOS 5. Conclusions 2

3 Insulator Scaling in III-V HEMTs Motivation : - III-V HEMT: Model system for future III-V logic FETs - HEMT scaling: L g t ins - Problem: t ins I G 10-3 t ins = 10 nm I D, I G [A/ m] t ins = 7 nm t ins = 4 nm t ins = 4 nm 7 nm I D nm -9 VDS = 0.5 V I G InAlAs/InGaAs HEMT L g = 30 nm <del Alamo, TWHM 09> V GS [V] Inverted HEMT design: reduced I G 3

4 Concept of Inverted HEMT <Normal HEMT > <Inverted HEMT > Cap. Insulator Channel Barrier Si doping Cap. Insulator Channel Barrier Gate CB Profiles [ev] Normal HEMT V GS = +0.3 V n s,ch = 1.6 X /cm Vertical depth [nm] Electron density [x /cm 3 ] CB Profiles [ev] Inverted HEMT V GS = V n s,ch = X /cm Vertical depth [nm] Electron density [x /cm 3 ] Lower leakage current due to higher barrier under gate 4

5 Trade-off of Inverted HEMT : Access region : Contact region CB Prof ile [ev] n -0.2 s,ch = -0.2 n s,ch = 068x /cm 2 06X10 0.6X10 12 /cm Electron Den nsity [10 18 /cm 3 ] Vertical depth [nm] Vertical depth [nm] n s,ch ~ 2.7 x /cm 2 for Normal HEMT n s,ch ~ 3 x /cm 2 for Normal HEMT Problem: - low n s in access region - large energy barrier under contact region CB Profi iles [ev] Electron De ensity [10 18 /cm 3 ] 5

6 New Approach Gate New doping layer : Access region : Contact region CB Pro ofile [ev] Electron Dens sity [10 18 /cm 3 ] CB Pro ofiles [ev] n s,ch = 2.4 x /cm Vertical depth [nm] Vertical depth [nm] -0.2 n s,ch = 24x10 12 /cm 2 2.7X10 12 /cm n s,ch ~ 2.7 x /cm 2 for Normal HEMT n s,ch ~ 3 x /cm 2 for Normal HEMT 1 0 Electron Dens sity [10 18 /cm 3 ] High n s in access region Low barrier in contact region 6

7 Epitaxial Heterostructure Etch stopper Barrier n+ In 0.65 Ga 0.35 As 5 nm Cap n+ In 0.53 Ga 0.47 As 15 nm n+ In 0.52 Al 0.48 As 15 nm InP 6 nm In 0.52 Al 0.48 As 2 nm In 0.52 Al 0.48 As 8 nm Si -doping g Channel Back Barrier + Buffer Substrate In 0.53 Ga 0.47 As 2 nm In 0.7 Ga 0.3 As 8 nm In 0.53 Ga 0.47 As 3 nm In 0.52 Al 0.48 As 5 nm In 0.52 Al 0.48 As S. I. InP n,hall = 9,800 cm 2 /V-sec 7

8 Device Technology S Oxide D Cap Etch stopper Barrier Channel Buffer L side L g t ins t ch - Triple-recess process - t ins = 4 nm, L side = 80 nm - Gate: Ti/Pt/Au - L g : nm 8

9 Output & Transfer Char. : L G = 30 nm V GS =0.3 V V DS =0.5 V I D [m ma/ m] I D [m ma/ m] V DS [V] V GS [V] GM [ms S/mm] Good I D saturation, pinch-off behavior G m = 127S/ 1.27 DS =0.5 05V 9

10 Subthreshold Char. : L g = 30 nm I D 10-4 I D & I G [A/ m] V DS = 0.5 V V DS = 0.05 V I G V GS [V] DIBL = 118 mv/v, S = 83 mv/dec. Excellent I OFF I ON /I OFF = 3.9 X 10 4 for V DS = 0.5 V 10

11 f T & f max Char. : L g = 30 nm H 21 U Gain [db] 20 MAG/MSG f max = 550 GHz 10 V GS =0.2 V V DS =0.8 V f T = 500 GHz Frequency [Hz] f T =500 GHz & f max =550 GHz Highest f T & f max reported on Inverted HEMTs 11

12 Inverted vs. Normal HEMTs: I G 10-3 Inverted HEMT I D Normal HEMT VDS 10-4 DS L g = 30 nm 10-5 V DS = 0.5 V = 50 mv V DS = 0.5 V V DS = 50 mv & I G [A/ m m] I D V DS I G I G = 50 mv V DS = 0.5 V V GS [V] <D.-H. KIM IPRM 09> Inverted HEMT: ~100 X less I G than normal HEMT 12

13 Inverted vs. Normal HEMTs: I ON /I OFF vs. L g 10-2 I ON Inverted HEMT Normal HEMT I ON & I OFF [A A/ m] I ON /I OFF 10-9 I OFF V DS = 0.5 V L g [nm] Inverted HEMT: Excellent I ON /I OFF scalability down to L g = 30 nm 13

14 Inverted vs. Normal HEMTs: g mi 3.2 Inverted HEMT : n,hall = 9,800 cm 2 /V-s Normal HEMT n,hall = 11,000 cm 2 /V-s 2.8 g mi & g m,ext [S/mm m] g mi g m,ext g mi from S-parameters 1.2 V DS =0.5V Inverted HEMTs: Gate Length [nm] - Lower values of g mi : from reduced and velocity - Better g mi scalability down to 30 nm 14

15 Inverted vs. Normal HEMTs: R s [ohm.mm] * R s <Using gate current injection technique> Inverted HEMT Normal HEMT R S =0.27 ohm.mm R sh =100 ohm/sq R sh =70 ohm/sq R 020 = S ohm.mm L g [nm] Higher R s in inverted HEMT Why? Lower n s in access region, higher R c 15

16 Inverted vs. Normal HEMTs: f T and f max f T & f max [G GHz] 700 Inverted HEMT Normal HEMT V DS = 0.8 V f max f T Outpu conductanc ce g o [S/mm] 0.25 f T 0.20 f max V GS [V] L g = 30 nm Inverted HEMT Normal HEMT V DS = 0.8 V L g = 30 nm V GS [V] Inverted HEMTs: Lower f T & higher f max Improved g o : possibly due to lower n s in access region 16

17 Benchmarking : SS & DIBL pe [mv/dec] Subth hreshold Slo Si FETs (IEDM) Inverted dhemt Normal HEMT Gate Length [nm] DIBL [mv V/V] Si FETs (IEDM) Inverted HEMT Normal HEMT Gate Length [nm] Excellent SCE of inverted HEMT 17

18 Benchmarking : I ON vs. I Leak x V DD = 0.5 V 0.4 I leak 1 2 ( I OFF InGaAs Inverted HEMT L g = 30 nm I G,ON ) InGaAs normal HEMT L g = 30 nm 65 nm HP-CMOS (L g = 35 nm) g N [A/ m] I ON nm LP-CMOS (L g = 55nm) I leak [A/ m] At I leak = 100 na/μm, 1.3X higher I ON than 65 nm HP CMOS 18

19 Benchmarking : CV/I vs. L g 10 Inverted HEMTs Normal HEMTs GATE DELA AY [psec] 1 Si NMOSFETs (V DD = 1.1~1.3V) In 0.7 Ga 0.3 As HEMTs (V DD = 0.5V) Inverted HEMT: Gate Length, L g [nm] Comparable Gate delay with L g but at lower V DD < Ref. : Chau et al. (T-Nano 2005) > 19

20 Conclusions Inverted InGaAs HEMT Scaling benefit: Reduced I g allows for further L g scaling At 30 nm, inverted HEMTs exhibit excellent characteristics: ti DIBL < 120 mv/v, S < 85 mv/dec and I ON /I OFF ~ 4 x 10 4 f T > 500 GHz and f max > 550 GHz, CV/I ~ 1 psec Inverted InGaAs HEMT: promising layer structure for future high-k/iii-v MOSFET 20