EE 330 Lecture 18. Small-signal Model (very preliminary) Bulk CMOS Process Flow

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1 EE 330 Lecture 18 Small-signal Model (very preliminary) Bulk CMOS Process Flow

2 Review from Last Lecture How many models of the MOSFET do we have? Switch-level model (2) Square-law model Square-law model (with λ and bulk additions) α-law model (with λ and bulk additions) BSIM model BSIM model (with binning extensions) BSIM model (with binning extensions and process corners)

3 Review from Last Lecture The Modeling Challenge I D Actual Modeled with one model V GS3 (and W/L variations or Process Variations) Local Agreement with Any Model V GS2 (and W/L variations or Process Variations) V GS1 (and W/L variations or Process Variations) V DS (and W/L variations or Process Variations) I G I D V DS I = f V,V D 1 GS DS I = f V,V G 2 GS DS I = f V,V B 3 GS DS V GS I B V BS = 0 Difficult to obtain analytical functions that accurately fit actual devices over bias, size, and process variations

4 Review from Last Lecture Model Status Simple dc Model Square-Law Model Small Signal Better Analytical dc Model Sophisticated Model for Computer Simulations BSIM Model Square-Law Model (with extensions for λ,γ effects) Short-Channel α-law Model Frequency Dependent Small Signal Simpler dc Model Switch-Level Models Ideal switches R SW and C GS

5 Review from Last Lecture D n-channel. p-channel modeling D S S G G G G S D S D D D G B G B S S G I G V GS I D D I B B V BS V DS V GS G I G S B I B V BS V DS S I D D I D V GS4 V GS3 Models essentially the same with different signs and model parameters 1 V GS V GS V DS VDS VGS4 VGS3 VGS2 V GS1> 0 0 VGS VTn W V L 2 W 2 μ C V V V V V V V 2L I =I =0 DS I μ C V V V V V V V V D n OX GS Tn DS GS Tn DS GS Tn G B n OX GS Tn GS Tn DS GS Tn 0 V V GS Tp W V L 2 W 2L I =I =0 DS I -μ C V V V V V V V V D p OX GS Tp DS GS Tp DS GS Tp G B 2 -μ C p OX VGS VTp VGS VTp VDS VGS VTp

6 Review from Last Lecture Model Relationships G D R SWn C GSn V GS Determine R SW and C GS in the switch-level model for an n-channel MOSFET from square-law model in the 0.5u ON CMOS process if L=1u, W=1u (Assume μc OX =100μAV -2, C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) S 0 V V GS T W V L 2 W 2L DS I μc V V V V V V V V D OX GS T DS GS T DS GS T 2 μc V V V V V V V OX GS T GS T DS GS T when SW is on, operation is deep triode

7 Review from Last Lecture Model Relationships G D R SWn C GSn V GS Determine R SW and C GS for an n-channel MOSFET from square-law model in the 0.5u ON CMOS process if L=1u, W=1u (Assume μc OX =100μAV -2, C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) When on operating in deep triode W V W L 2 L DS I μc V V V μc V V V D OX GS T DS OX GS T DS V 1 1 DS R = 4K SQ I W 1 D V GS =VDD μc V V ( E 4) OX GS T L V GS =3.5V 1 S C GS = C OX WL = (2.5fFµ -2 )(1µ 2 ) = 2.5fF

8 Review from Last Lecture Model Relationships G D C GSp R SWp V GS Determine R SW and C GS for an p-channel MOSFET from square-law model in the 0.5u ON CMOS process if L=1u, W=1u ( C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) Observe µ n \ µ p 3 S 0 V V GS T W V L 2 W 2L DS -I μc V V V V V V V V D OX GS T DS GS T DS GS T 2 μc V V V V V V V OX GS T GS T DS GS T When SW is on, operation is deep triode

9 Review from Last Lecture Model Relationships D G R SWp C GSp V GS Determine R SW and C GS for an p-channel MOSFET from square-law model in the 0.5u ON CMOS process if L=1u, W=1u Observe µ n \ µ p 3 ( C OX =2.5fFu -2,V T0 =1V, V DD =3.5V, V SS =0) W V W L 2 L DS -I μ C V V V μ C V V V D p OX GS T DS p OX GS T DS -V 1 1 DS R = 12K SQ -I W 1 1 D V GS =VDD μ C V V ( 4) p OX GS T L E V GS =3.5V 3 1 C GS = C OX WL = (2.5fFµ -2 )(1µ 2 ) = 2.5fF Observe the resistance of the p-channel device is approximately 3 times larger than that of the n-channel device for same bias and dimensions! S

10 Modeling of the MOSFET Goal: Obtain a mathematical relationship between the port variables of a device. I f V,V,V I I D G B 1 f f 2 3 GS DS BS VGS,V DS,VBS V GS,V DS,VBS Drain V DS I D I B Gate Bulk I D Simple dc Model V GS V BS Small Signal Better Analytical dc Model Sophisticated Model for Computer Simulations Frequency Dependent Small Signal Simpler dc Model

11 Small-Signal Model Goal with small signal model is to predict performance of circuit or device in the vicinity of an operating point Operating point is often termed Q-point

12 Small-Signal Model y Y Q Q-point X Q x Analytical expressions for small signal model will be developed later

13 Technology Files Design Rules Process Flow (Fabrication Technology) Model Parameters

14 n-well n-well n- p-

15

16

17 Bulk CMOS Process Description n-well process Single Metal Only Depicted Double Poly This type of process dominates what is used for high-volume lowcost processing of integrated circuits today Many process variants and specialized processes are used for lowervolume or niche applications Emphasis in this course will be on the electronics associated with the design of integrated electronic circuits in processes targeting highvolume low-cost products where competition based upon price differentiation may be acute Basic electronics concepts, however, are applicable for lower-volume or niche applicaitons

18 Components Shown n-channel MOSFET p-channel MOSFET Poly Resistor Doubly Poly Capacitor

19 C D A A B B C D

20 Consider Basic Components Only Well Contacts and Guard Rings Will be Discussed Later

21 A A B B

22 A A B B

23 Metal details hidden to reduce clutter A A D G S B D B S B n-channel MOSFET G

24 A A D G S B B B W L

25 A A Capacitor Resistor p-channel MOSFET B B n-channel MOSFET

26 n-well n-well n- p-

27 N-well Mask A A B B

28 N-well Mask A A B B

29 Detailed Description of First Photolithographic Steps Only Top View Cross-Section View

30 ~ Blank Wafer Implant n-well Photoresist Mask p-doped Substrate Will use positive photoresist (exposed region soluble in developer) A A B Develop Expose B

31 Develop N-well Exposure Photoresist Mask A-A Section B-B Section

32 Implant A-A Section B-B Section

33 N-well Mask A-A Section B-B Section

34 n-well n-well n- p-

35 Active Mask A A B B

36 Active Mask A A B B

37 Active Mask Field Oxide A-A Section Field Oxide Field Oxide Field Oxide B-B Section

38 n-well n-well n- p-

39 Poly1 Mask A A B B

40 Poly1 Mask A A B B

41 Poly plays a key role in all four types of devices! A A Capacitor Resistor P-channel MOSFET B B n-channel MOSFET

42 Poly 1 Mask A-A Section Gate Oxide Gate Oxide B-B Section

43 n-well n-well n- p-

44

45 Poly 2 Mask A A B B

46 Poly 2 Mask A A B B

47 Poly 2 Mask A-A Section B-B Section

48 n-well n-well n- p-

49

50 P-Select A A B B

51 P-Select A A B B

52 P-Select Mask p-diffusion p-diffusion A-A Section Note the gate is self aligned!! B-B Section

53 n-select Mask n-diffusion A-A Section n-diffusion B-B Section

54 n-well n-well n- p-

55

56

57 Contact Mask A A B B

58 Contact Mask A A B B

59 Contact Mask A-A Section B-B Section

60 n-well n-well n- p-

61

62

63 Metal 1 Mask A A B B

64 Metal 1 Mask A A B B

65 Metal Mask A-A Section B-B Section

66 A A B B

67 A A Capacitor Resistor P-channel MOSFET B B n-channel MOSFET

68 Should now know what you can do in this process!! Can metal connect to active? Can metal connect to substrate when on top of field oxide? How can metal be connected to substrate? Can poly be connected to active under gate? Can poly be connected to active any place? Can metal be placed under poly to isolate it from bulk? Can metal 2 be connected directly to active? Can metal 2 be connected to metal 1? Can metal 2 pass under metal 1? Could a process be created that will result in an answer of YES to most of above?

69 How we started this course CAD Tools Circuit Structures and Circuit Design Device Operation and Models Semiconductor and Fabrication Technology

70 Thanks for your patience!! The basic concepts should have now come together Semiconductor and Fabrication Technology CAD Tools Device Operation and Models Circuit Structures and Circuit Design

71 How does the inverter delay compare between a 0.5u process and a 0.18u process? V DD V IN V OUT V IN V OUT V SS

72

73

74

75

76 How does the inverter delay compare between a 0.5u process and a 0.18u process? Feature Units Vtn V Vtp V ucoxn ua/v^2 ucoxp ua/v^2 Cox ff Vdd V fosc MHz V IN Assume n-channel and p-channel devices with L=Lmin, W=1.5Lmin V OUT n t HL =R pd C R L pd ncoxw n VDD VTN t LH =R pd C L Lp Rpu C W V V Feature Units L p OX p DD TP C C W L W L L OX n n p p CL ff Rpd ohms Rpu ohms THL psec TLH psec f GHz Note 0.18u process is much faster than 0.5u process

77 End of Lecture 18

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