Quantification of Trap State Densities at High-k/III-V Interfaces

Transcription

1 Quantification of Trap State Densities at High-k/III-V Interfaces Roman Engel-Herbert*, Yoontae Hwang, and Susanne Stemmer Materials Department, University of California, Santa Barbara *now at Penn State University, Department of Materials Science and Engineering International Symposium on Advanced Gate Stack Technology September 9, 00 Albany, NY

2 Acknowledgements TEM/STEM Joel Cagnon, Nick Rudawski, James LeBeau Temperature-dependent CV and conductance Jeff Huang (Sematech) Funding SRC Nonclassical CMOS Research Center

3 Outline CV characteristics of high-k/inga0.7as interfaces Methods to quantify Dit Conductance method CV-based method (Terman) Guidelines to determine Fermi level unpinning and quantify Dit Dit reduction using forming gas anneals Summary

4 Introduction HfO ZrO Y. C. Chang et.al., Appl. Phys. Lett. 9, 0790 (008). S. Koevshnikov et.al., Appl. Phys. Lett. 9, 90 (008). Typical room temperature characteristics of high-k/n-inga0.7as interfaces: False inversion due to response of midgap states Sometimes incorrectly attributed to true inversion or weak inversion Finite slope of MHz curve at negative gate bias Large frequency dispersion in accumulation

5 Introduction Simulations for GaAs with midgap Dit peak of. 0 cm - ev - Experiments for HfO/InGa0.7As with midgap Dit of??? 00 K Capacitance [µf/cm ] K 00 Hz khz 0 khz 00 khz MHz Gate Voltage [V] CV measurements: Jeff Huang, Sematech 00 K Capacitance [µf/cm ] Hz khz 0 khz 00 khz MHz 00 K K. Martens, Ph.D. Thesis, KU Leuven (009) Gate Voltage [V] This talk focuses on InGa0.7As channels, where Dit can be probed at room temperature

6 Introduction Reported Dit values span several orders of magnitude, despite often very similar admittance characteristics Many different methods have been used Need to characterize Dit from MOSCAPs because transistor fabrication may introduce additional defects

7 Introduction As-decapping: Clean, well-defined growth surface HAADF/STEM InGa0.7As HfO n+-inp RHEED of growth surface InGa0.7As No interface layer Films are crystalline Source: Hf[OC(CH)] Hf bonded to four oxygens No excess oxidant O O Hf O O Films are subjected to different post-deposition anneals in nitrogen and forming gas, respectively, which results in very different Dit Systematic evaluation and comparison of analysis methods

8 Reduction in mid-gap Dit by forming gas anneals No forming gas anneal After forming gas anneal.0.0 Capacitance density [µf/cm ] nm HfO N anneal - 0 Gate Voltage [V] f khz 0 khz 00 khz MHz Capacitance density [µf/cm ] nm HfO FG anneal - 0 f khz 0 khz 00 khz MHz Capacitance density [µf/cm ] nm HfO FG anneal f khz 0 khz 00 khz MHz Large midgap-dit response Fermi level effectively pinned at midgap Much reduced midgap-dit response Very efficient Fermi level movement for 9 nm HfO film across midgap Y. Hwang, R. Engel-Herbert, N. G. Rudawski, S. Stemmer, Effect of postdeposition anneals on the Fermi level response of HfO /In Ga 0.7 As gate stacks, J. Appl. Phys. 08, 0 (00).

9 Conductance Method Advantages No forming gas anneal After forming gas anneal Log (f) [Hz] G p /Aωq [0 /evcm ] Log (f) [Hz] nm HfO 9 nm HfO Efficient movement of conductance peak with gate bias provides evidence for Fermi level movement around midgap Conversely, if the conductance peak does not move, the Fermi level is effectively pinned at midgap In principle, the Dit at midgap can be obtained directly: G p /Aωq [0 /evcm ] But...

10 Conductance Method Issues Requires knowledge of Cox, which is not equal to Cacc (n-type) If Cox is overestimated, the peak height is reduced and thus the Dit is lower than the true value At high Dit and high EOT, errors become very large (see papers by IMEC group) Lin et al., Appl. Phys. Lett. 9, 5508 (009).

11 Conductance Method Issues No forming gas anneal After forming gas anneal Log (f) [Hz] G p /Aωq [0 /evcm ] Log (f) [Hz] nm HfO 9 nm HfO G p /Aωq [0 /evcm ] Cox < qdit Cox > qdit Cannot get a reliable Dit from conductance method for this stack Dit estimate should be ok

12 Only midgap Dit can be determined At room temperature only midgap Dit responds Conductance Method Issues In principle, lower temperatures should move the characteristic frequency of traps near the band edges into the measurable frequency range Trap response freezes out at low temperatures Reduced thermal broadening causes fewer traps to respond

13 Conductance Method Issues No forming gas anneal Dit values near the band edges are likely too low Is the apparently sharply peaked midgap Dit real or an artifact from the conductance method?

14 Requires calculation an ideal CV curve CV-Based Methods Terman Method Ideal CV must take into account electronic structure of III-V semiconductor Nonparabolicity of Γ band Filling of X, L valleys Fermi level moves deep into the conduction band Boltzmann statistics not appropriate to calculate charge in the semiconductor d "( x) dx = # $ ( x ) % s = # q p " x { [ ( )] # n ["( x) ] + N D # N A } % s Equations ( ) = # s E $ ( x = 0) Q s " s = % Sign " s [ ] { [ ] % n [ $ ( x) ]}d$ x $ b +" s ( ) & %q# s N D % N A + p $ ( x) $ b R. Engel-Herbert, Y. Hwang, S. Stemmer, Appl. Phys. Lett. 97, 0905 (00). ( )! [ ] = $ n " #( x) & % $ k B T m ) ( ", " (+ -, " )(+ -, " ) + 7 ' h * exp, ". q# ( x d, 0 ) " 0 k B T + / 5 " 5 + [ ] = $ n i ["( x) ] n "( x) i=#, X,L C dos " s D it (" s ) = C ox q ( ) = # dq s (" s ) ## % %% $ $ d" s dv g & ( ' ) d" s & )( ( ) C dos " s ' ( ) Terman

15 CV-Based Methods Terman Method Calculated ideal CV and band bending for a nm EOT Capacitance [µf/cm ] HF curve C ox classic Γ α=0 Γ Γ α +X+L Gate Voltage [V] Band bending ψ s [ev] classic Γ α=0 Γ Γ α +X+L R. Engel-Herbert, Y. Hwang, S. Stemmer, Appl. Phys. Lett. 97, 0905 (00). The classical CV curve does not reveal the asymmetry due to the difference in the density of states of valence and conduction bands. The parabolic valley approximation underestimates the increase of semiconductor charge with band bending and thus the semiconductor capacitance, causing the asymmetry in the CV to be overestimated. At a gate bias of V, Cdos is 5% lower for the parabolic case.

16 CV-Based Methods No forming gas anneal Terman Method After forming gas anneal Capacitance [µf/cm ] C ox 8 nm N anneal measured ideal Gate Voltage [V] Large CV stretch-out Minimum capacitance does not reach semiconductor capacitance calculated from doping Capacitance [µf/cm ] C ox 9 nm HfO FG anneal Minimum capacitance reaches the semiconductor capacitance calculated from doping Band bending ψ s [ev] measured ideal Gate Voltage [V] Band bending is less then half of semiconductor band gap Fermi level is effectively pinned at midgap Band bending ψ s [ev] FG (9 nm HfO ) Band bending exceeds half of semiconductor band gap Fermi level can be moved past midgap R. Engel-Herbert, Y. Hwang, S. Stemmer, Appl. Phys. Lett. 97, 0905 (00). Y. Hwang, R. Engel-Herbert, N. G. Rudawski, S. Stemmer, J. Appl. Phys. 08, 0 (00).

17 Comparison of Different Methods Both conductance method and Terman method agree qualitatively Provide a consistent picture of Fermi level (un)pinning and midgap Dit response Capacitance [µf/cm ] Pinned at midgap Pronounced midgap Dit reponse Capacitance does not reach minimum capacitance C ox measured ideal Gate Voltage [V] Log (f) [Hz] Band bending ψ s [ev] - 0 Capacitance density [µf/cm ] No forming gas anneal G p /Aωq [0 /evcm ] 8 nm HfO N anneal - 0 Gate Voltage [V] Gate Voltage [V] f khz 0 khz 00 khz MHz Band bending less than half of the band gap Limited conductance peak movement Capacitance density [µf/cm ] Capacitance [µf/cm ].5.0 khz 0 khz 00 khz MHz Band bending more than half of the band gap Conductance peak movement C ox 9 nm HfO FG anneal Log (f) [Hz] 9 nm HfO FG anneal f Band bending ψ s [ev] - 0 Not pinned at midgap (FG anneal) Reduced midgap Dit reponse Capacitance reaches minimum capacitance G p /Aωq [0 /evcm ] After forming gas anneal FG (9 nm HfO )

18 Criteria to Establish Fermi Level Unpinning. The dopant concentration and oxide capacitance should be determined independently, as they are needed both in conductance and CV-based methods.. To establish that the Fermi level is not effectively pinned at midgap, it should be shown that the high-frequency CV reaches the ideal depletion capacitance determined by the semiconductor doping Capacitance [µf/cm ] C ox pinned measured ideal Gate Voltage [V] Capacitance [µf/cm ] C ox unpinned 9 nm HfO FG anneal The room temperature parallel conductance should show a frequencydependent shift of the conductance peak maximum with gate voltage. If the conductance peak maximum shifts to frequencies that are less than khz for n-moscaps it is indicative that the Fermi level can be moved into the lower part of the band gap. Log (f) [Hz] pinned G p /Aωq [0 /evcm ] Log (f) [Hz] unpinned G p /Aωq [0 /evcm ] R. Engel-Herbert, Y. Hwang, S. Stemmer, Appl. Phys. Lett. 97, 0905 (00). Y. Hwang, R. Engel-Herbert, N. G. Rudawski, S. Stemmer, J. Appl. Phys. 08, 0 (00).

19 Criteria to Establish Fermi Level Unpinning. The room temperature conductance method gives reasonable estimates of the fast Dit around midgap, only if Cox > qdit. 5. The ideal CV curve must be calculated taking into account the low conduction band density of states and the nonparabolicity of the Γ valley.. If true inversion is claimed it should be shown that the experimentally achieved bend bending is sufficient to achieve inversion. Q s [cm - ] T=00K N D =x0 7 cm ψ s [ev] classic Γ α=0 Γ Γ α +X+L Band bending ψ s [ev] FG (9 nm HfO ) Capacitance density [µf/cm ] nm HfO FG anneal f khz 0 khz 00 khz MHz A bend bending of more than -0. ev is needed for inversion FG annealed stack No indication of inversion response at khz Lower frequencies needed? R. Engel-Herbert, Y. Hwang, S. Stemmer, Appl. Phys. Lett. 97, 0905 (00). Y. Hwang, R. Engel-Herbert, N. G. Rudawski, S. Stemmer, J. Appl. Phys. 08, 0 (00).

20 Dit From Different Methods Near midgap: good agreement Conductance method only measures fast Dit while Terman measures all Dit Issues with Terman Method E VB E CB Issues with Conductance Method The HF CV curve is not a true HF curve Causes errors near band edges D it [cm - ev - ] 0 0 Terman method conductance method Conductance method as developed by Nichollian and Brews assumes that Dit and capture cross-section are independent of energy, which works for Si, with its very uniform Dit distribution ΔE [ev] Does not work for III-V Conductance method needs to be revisited for III-V s Recommendation: Use Terman method until issues with conductance method are fixed R. Engel-Herbert, Y. Hwang, S. Stemmer, Appl. Phys. Lett. 97, 0905 (00). Y. Hwang, R. Engel-Herbert, N. G. Rudawski, S. Stemmer, J. Appl. Phys. 08, 0 (00).

21 Dit From Different Methods Is the sharply peaked midgap Dit predicted by the conductance method real? GaO/GaAs AlO/InGaAs G. Brammertz et al., J. Electrochem Soc. 55, H95 (008). No forming gas anneal After forming gas anneal D it [ev - cm - ] Trap level [ev] D it [ev - cm - ] 0 0 E CB 0 nonparabolic Γ Trap level [ev] E CB For high-dit stacks, a peak at midgap is indeed observed also in the Terman method Terman method reveals clear changes in Dit distribution with forming gas anneal (not just magnitude) R. Engel-Herbert, Y. Hwang, S. Stemmer, Appl. Phys. Lett. 97, 0905 (00). Y. Hwang, R. Engel-Herbert, N. G. Rudawski, S. Stemmer, J. Appl. Phys. 08, 0 (00).

22 How to reduce the Dit of high-k/ingaas stacks Most high-k/ingaas MOSCAPs look like this... Forming gas anneals significantly reduce mid-gap Dit Y. C. Chang et.al., Appl. Phys. Lett. 9, 0790 (008). Capacitance density [µf/cm ] nm HfO N anneal - 0 Gate Voltage [V] Huge mid-gap Dit f khz 0 khz 00 khz MHz Capacitance density [µf/cm ] Y. Hwang, R. Engel-Herbert, N. G. Rudawski, S. Stemmer, J. Appl. Phys. 08, 0 (00). Band bending ψ s [ev] nm HfO FG anneal f khz 0 khz 00 khz MHz FG (9 nm HfO ) E. Kim et al., Appl. Phys. Lett. 9, 090 (00) Largest band bending ever reported, due to combination of lower Dit and high Cox, though Dit is still high

23 Summary Developed a set of guidelines to establish Fermi level unpinning at high-k/ingaas interfaces Dit quantification: Many issues with conductance methods, some poorly understood Terman method gives upper estimate for slow and fast Dit Many pitfalls in all methods: incorrect semiconductor doping, Cox, need correct band structure model,... Forming gas anneals reduce the midgap Dit significantly