A study on interface traps and near interfacial bulk traps in the interfaces of dielectric/semiconductor and semiconductor hetero-junction

Transcription

1 final examination Tokyo Institute of Technology A study on interface traps and near interfacial bulk traps in the interfaces of dielectric/semiconductor and semiconductor hetero-junction Chunmeng Dou Supervisor: Prof. Hiroshi Iwai & Prof. Kuniyuki Kakushima Electronics and Applied Physics Interdisciplinary Science and Engineering Group Tokyo Institute of Technology 1

2 2 Content of this thesis Ch.1. Introduction Ch.2. Review of interfacial traps characterization techniques Interfacial traps on Si fins Ch.3. Profiling interface traps distribution on Si fins by charge-pumping method Oxide traps in high-k/iii-v Ch.4. Evaluation of oxide traps distribution by C-V measurement Ch.5. Modified conductance method Interfacial traps in nitride hetero-junctions Ch.6. Investigation on Interface traps and near interfacial bulk traps in AlGaN/GaN by conductance method Ch.7. Conclusion

3 Future trend of IC technology New Application digital+analog+optical Silion+III-V/III-Nitride Electrical+Mechanical CMOS More Moore New structures/materials High-k/metal-gate Multi-gate structure High mobility channel M. Bohr, Moore s law in the innovation era, Proc. of SPIE, vol. 7974, pp /1-8 (2011) New Technologies Carbon Based Spintronics Magnetic Domains Molecular Switches. Future progress driven by CMOS scaling, semiconductor device diversification, and revolutionary device concepts. 3

4 Emerging FETs with novel structure/material New structure Multi-gate for high I ON /I OFF ratio: New material III-V/Ge for low power-consumption digital IC: III-Nitride for high power/frequency application: dex de de dx dy dz y z 4

5 Log (I d ) Interface and near interface traps: device-killing factor w/o traps S with traps Interface trap bulk trap Gate Oxide or barrier layer D w/o traps with traps C ox C s Degraded I ON Relaxed subthreshold control Gate voltage Evaluation and control of interfacial traps is crucial for introducing novel structure and material 5

6 etched surface Interfacial issues of 3D nanostructures varying crystalline orientation Si SiO 2 (111) (100) Cross-sectional view of Si fins D. Schroder, Semiconductor material and device characterization, 3rd edition, Willey Interscience, 2006 Spatial distribution of density of interface states, D it, at the 3D surface, depending on crystalline orientation and fabrication process, has to be investigated 6

7 Interfacial issues of III-V based MOS systems Non-stoichiometry in compound semiconductor: Lack of high-quality interfacial oxide layer with large band-offset: Si: disruption of periodic crystal GaAs: + traps due to additional vacancies Large amounts of interface traps SiO 2 /Si: ~ 2.5 ev Al 2 O 3 /InGaAs ~ 2.0 ev large amounts of oxide border traps Separate evaluation of interface traps and oxide border traps is necessary 7

8 Interfacial issues of AlGaN/GaN hetero-interface Lattice constant Al 0.25 Ga 0.75 N Tensile strain Metal Al 0.25 Ga 0.75 N SP: spontaneous polarization PE: piezo-electric polarization Polarization interface charge P SP 2DEG GaN GaN Sub. P PE P SP Metal AlGaN GaN Due to the lattice mismatch Interface traps exist at the hetero-interface. Bulk traps may exist in the thin AlGaN layer under tensile strain 8

9 Purpose of this study Developing characterization techniques to analyze the interfacial issues of representative devices with novel structure (3D) and materials (III-V/III-Nitride) 3D structure III-V MOS system Nitride hetero-junctions Spatial distribution of D it D it and N bt evaluation D it the hetero-interface (1) Provide general guideline for interface characterization when new structure and material are introduced. (2) Strengthen the understanding of trapping/de-trapping mechanisms 9

10 10 Content of this thesis Ch.1. Introduction Ch.2. Review of interfacial traps characterization techniques Interfacial traps on Si fins Ch.3. Profiling interface traps distribution on Si fins by charge-pumping method Oxide traps in high-k/iii-v Ch.4. Evaluation of oxide traps distribution by C-V measurement Ch.5. Modified conductance method Interfacial traps in nitride hetero-junctions Ch.6. Investigation on Interface traps and near interfacial bulk traps in AlGaN/GaN by conductance method Ch.7. Conclusion

11 Problems Advantages Comparison on different characterization techniques C-V based-method 1. Common method for evaluate MOS capacitor Admittance analysis Conductance method 1. Sensitive to low D it, and other information is available 2. Convenient measurement for MOS capacitor Charge-pumping method Direct evaluation of D it by measuring the electronhole recombination current at the trap sites 1. Required theoretically ideal C-V model or equivalent circuit model 2. Not applicable for MOS capacitors on SOI 3. Separate evaluation of interface traps and near interface bulk traps is lack of discussion Requiring MOSFET or diode configuration Preliminary evaluation when new materials are introduced Accurate profiling in advanced structures 11

12 Choosing proper characterization techniques New structure New material III-V MOS system D it and N bt evaluation Tensile strain Metal Al 0.25 Ga 0.75 N GaN Sub. Charge-pumping method to evaluate spatial distribution of D it at 3D surface (Ch.3) Admittance analysis Capacitance (Ch.4) and conductance (Ch.5) analysis in III-V MOS capacitance conductance analysis (Ch.6) in hetero-interface 12

13 III. Profiling interface traps distribution on Si fins by charge-pumping method Experimental setup and sample preparation Optimal forming gas annealing condition for lowering D it Evaluation of the spatial distribution of D it on the 3D surfaces of Si fins 13

14 Charge-pumping (CP) method for SOI structure Gated-diode structure: CP current Gate pulse waveform: accumulation V R Pulse V g W N + e - h + P + BOX Si sub. T. Ouisse, et al., IEEE Trans. Electron Devices, vol.38, no. 6, pp (1991) A Electron trapping t r V gamp t r t f V base E f,inv E f,acc Inversion CP method can be applicable to SOI structure by Gated p-i-n diode E C E V t f hole trapping 14

15 Devices fabrication Fin Patterning Starting wafer:p type 140ohm-cm SOI wafer (100)-oriented SOI layer (70nm) / BOX layer (50nm) BOX Si Sub. W SiO 2 Gate oxide film formation by a dry oxidation at 1000 o C for 10min. W film deposition by RF sputtering P implantation (Phosphorus, 30keV, cm -2 ) BF 2 implantation (Boron, 30keV, cm -2 ) Activation annealing in N 2 gas ambient at 800 o C for 5min. Al contacts deposition by thermal evaporation (source and drain regions and back side ) Annealing in F.G. ambient at 300 o C to 440 o C by 20 o C steps for 30 min. BOX Si Sub. N + W BOX Si Sub. N + BOX Si Sub. N + BOX Si Sub. W W P + P + Al 100 N + P + W For Fin: W fin : nm H fin : 70 nm For planar W: 46 & 78 mm BOX 15

16 (a) I cp (na) I cp (na) I cp,max (na) Typical charge-pumping characteristics V amp = 2V V r = 0.05V f = 500kHz t r = 100nsec L = 4.0mm W = 78mm V base (V) V base (V) t f = 100nsec t f = 200nsec t f = 300nsec t f = 400nsec (b) 29 0 I cp,max (na) D it D(E it (E em,e ) L = 4.0 mm W = 78 mm V amp = 2V V r = 0.05V f = 500kHz t r = 100nm (a) Fall time t f t(ns) f (ns) (b) Typical hat shape charge pumping current is confirmed By changing t f and t r, D it at the upper and lower halves of band-gap can be extracted 16

17 D it (cm -2 ev -1 ) Forming gas annealing for passivation of the D it on Si fins W fin = 100 nm, H fin = 100 nm, (a) (b) Passivation of Si dangling band: From 300 o C to 420 o C: Si-H bond formation (c) (d) Optimal F.G annealing temperature ~ 420 o C From 420 o C to 540 o C: Si-H bond dissociation E E i (ev) For Si fins: optimal F.G. annealing temperature at 400 ~ 420 o C; similar to planar SiO 2 /Si(100) case 17

18 D it (cm -2 ev -1 ) Channel widths dependence of the D it (a) planar (b) planar For planar devices: D it does not depend on W Uniform D it distribution (c) 3D (d) 3D For Si fins: D it increases as W decreases Non-uniform D it distribution (lower D it at the top walls) E E i (ev) The average D it on the surfaces of Si fins increases as channel width decrease 18

19 D it (cm -2 ev -1 ) W fin from 80 to 110 nm Evaluation the local D it distribution E-Ei = 0.29 ev H fin = 70 nm D it,2δ 2 Fitting with corners D it W 2 D, 2( H ) D, 2 D, fin it top fin it side it corner, D W D D it fin it top it W fin W fin 2H 2( H ) D 2 D 2 2 H fin fin it, side it, corner fin 1 D it of (100) planar SOI W fin (nm) with corners (100) (110) cm -2 ev -1 cm -2 ev -1 cm -2 ev -1 D it, corners > D it, side > D it, top 19

20 Chapter 3: Summary of achievements Method for profiling the spatial distribution of D it on 3D nanostructure is established Optimal forming gas annealing temperature for Si fins is confirmed (400 ~ 420 o C) At the surface of Si fins patterned from (100) SOI wafer, D it, corners > D it, side > D it, top mainly due to surface crystalline orientation 20

21 IV. Evaluation of oxide traps distribution by C-V measurment Origin of the frequency dispersion of C-V curves in accumulation region Distributed model considering the frequency and temperature dependent response of oxide border traps Evaluation of oxide border traps distribution in energy and space by C-V technique 21

22 Capacitance (mf/cm 2 ) Characteristic Frequency Origin of the frequency dispersion in accumulation Pt/HfO 2 /Al 2 O 3 /n-in 0.53 Ga 0.47 As MOSCAP accumulation Hz depletion V fb Voltage (V) 1MHz Trap energy level In depletion, the frequency dispersion can be attributed to mid-gap D it. In accumulation, the time constant at interface can be given by: t 0 (N DOS s v th ) ~10-10 s f=1/2pt 0 & t 0 = (n s s v th ) -1 which is too fast to cause frequency dispersion from 100 Hz to 1MHz 22

23 Origin for the frequency dispersion in accumulation Trapping/de-trapping of the near interfacial oxide traps, i.e., border traps Tunneling front model: F.P. Heiman et al., IEEE TED, 12(4) (1965) Time constant of border trap t ( ) E, x t e k bt 0 2 E x t with (N s v ) 0 C n th 1 & k( E) 2m ( E E) / * ox C Band-offset for Al 2 O 3 /In 0.53 Ga 0.47 As: for SiO 2 /Si: ox C E E 2 ev Considering lack of thermal-dynamically stable interfacial layer with large band-offset in III-V MOS system, there are a large amount of electrically active border traps reside in the high-k layer. ox C E E 2.6 ev C C 23

24 Capacitance (mf/cm 2 ) Combined influence of frequency and temperature Although the direct tunneling model suggest ignorable temperature dependence of the frequency dispersion in accumulation K 210 K 150 K 77 K 100 Hz 1MHz V g (V) Investigate the frequency and temperature dependent response of Oxide traps Establish a method to readily evaluate the quality of the high-k oxide. Multi-frequency C-V at various temperatures Oxide traps distribution in energy and space 24

25 Distributed border traps model for MOS capacitor x = t ox x = t ox /N x = 0 G N Sub C ox gate ε ox / x ε ox / x C S substrate C bt C bt G bt C bt G bt G bt Border traps: Charge storage + energy loss Y. Yuan, et al., IEEE TED, vol.59, No.8 (2012) By inputting: (1) C ox and t ox ; (2) C s ; (3) N bt (x) ; (4) t 0 and k Admittance characteristics can be numerically calculated and fitted with experimental results 25

26 Empirical evaluation for frequency and temperature dependence (a) Measuring Frequency (f) dependency wt=1 condition: Border traps with t bt = t 0 e 2kx < 1/2pf can response Metal (b) Measuring Temperature (T) dependency ~ thermal activated capture cross section ~ x 0 (f, T) Eb s s0 exp kt n-iii-v sub. D.K. Schroder et al., Semiconductor Material and Device Characterization (Wiley, 2006) T dependence t 0 = (N c v th s) -1 : f and T depend probing depth x 0 : T T Eb t0(t) NC0 v th0 s0 exp T0 T 0 kt 1 x (f,t) ln 2k 2p f t (T) 0 26

27 Distance from interface into the oxide(nm) mpirical evaluation for frequency and temperature dependence III: x max <x< t ox II: x min <x< x max x x 0.4 I:0 < x < x min Temperature (K) Probing depth decreases with increasing frequency or decreasing temperature For our measurement window (100 Hz to 1MHz): Region I: too fast ; Region II: frequency dispersion; Region III: no influence 27

28 Accumulation Capacitance (mf/cm 2 ) Method demonstration 1: Approaching the intrinsic capacitance 2.6 high freq. low freq. V g = 1.0 V 0.8 V V V 0.8 V 0.6 V Temperature (K) The intrinsic capacitance of the InGaAs MOSCAP, without the influence of border traps, can be sufficiently approached by 1MHz/77K C-V measurement. 28

29 Distance from interface into the oxide(nm) Method demonstration 2: temperature dependence of t III: x max <x< t ox x II: x min <x< x max 0.8 x 0.4 I:0 < x < x min Temperature (K) C ox Accumulation capacitance decided by: C s, acc C tot C bt (f,t) Therefore: C ox : constant C S,acc : weak dependence on f and T C BT : depends on probing depth x 0 (f,t) x (f,t) ln 2k 2p f t (T) 0 if ft 0 (T) = constant Same C bt Same C tot 29

30 Capacitance (mf/cm 2 ) Frequency (Hz) Method demonstration 2: temperature dependence of t 0 -cont d f = khz, T = 300 K f = 8.32 khz, T = 210K -0.5 (a) f = Hz, T = 150K V g (V) f = khz, T = 210 K f = 25.12kHz, T = 150K (b) f = Hz, T = 77 K t 0 (T)/t 0 (T 0 ) K 150 K 210 K 210 K 150 K 300 K t ( T) t0( T0 300K) t0 ( T ) t ( T0 210K) Temperature (K) T T Eb t0(t) NC0 v th0 s0 exp T0 T 0 kt (c) (d) with E b = 65 mev Accumulation capacitance can be well reproduced by lower frequency at decreased temperature Inside the conduction band of InGaAs, t 0 changes from 10-9 ~10-10 s to 10-6 ~ 10-5 s ( 10 3 ) as temperature decreases from 300 K to 77 K. 30 1

31 Extraction of energy and spatial distribution of oxide traps Methodology: 1). Extraction of energy-voltage relationship from high-frequency/low-temperature C-V 2). Preliminary evaluation of the spatial distribution assuming uniformly distributed oxide traps concentration (N bt ) 3). Extraction of the non-uniform distributed oxide traps concentration (N bt ) 31

32 Step 1: Extract energy distribution of border traps from high-frequency/low-temperature C-V At Room Temperature, C-V has distortion in two directions 77K 150K 210K 300K Evaluated with considering oxide traps N. Taoka, et al., IEDM, pp , 2011 To avoid the over-estimation of the C ox and surface potential, V g - energy relationship can be extracted from high-frequency/low-temperature C-V by Terman technique. 32

33 Capacitance, C tot (mf/cm 2 ) Capacitance, C tot (mf/cm 2 ) Step 2.Preliminary evaluation the spatial distribution of oxide traps concentration Fitting of V g = 1V, 300K Region I,II 3.5 Region I,II, III Fitting of V g = 1V, 77K 3.5 Region II, III Measurement window 2.5 Measurement window Region II 2.0 Region II w (rad/s) N bt : cm -3 t 0 : s w (rad/s) N bt : cm -3 t 0 : s C tot (w) measured at different temperatures cannot be consistently fitted by assuming border traps concentration (N bt ) with uniform spatial distribution Increased N bt profile toward the gate may exist. 33

34 Step 3. Extract the non-uniformed distributed oxide traps distribution (a) N bt spatial profile (b) t 0 as a function of temperature (c) Fitted C(w) at different temperature (d) Fitted G(w) at different temperature Spatial distribution of N bt from the interface into the oxide can be gradually formed from low-to-high temperature C-V 34

35 Extracted border trap distribution in energy and space Charge pumping method ALD- Al 2 O 3 /In 0.53 Ga 0.47 As High concentration of oxide border traps ( cm -3 ) reside in the oxide and increases as energy or depth increases. The increased N bt as depth increases may attributed to accumulated defects during high-k growth or the dual layer structure used in this study. 35

36 Chapter 4: Summary of achievements A convenient way to evaluate the oxide traps distribution in energy and space from frequency- and temperature-dependent C-V is established An empirical way to evaluate the frequency- and temperature-dependent response of oxide border traps is demonstrated. Capturing process of oxide traps tends to be thermal activated. Temperature dependent frequency dispersion of the accumulation capacitance results from non-uniform distributed oxide border traps. High concentration of oxide traps ( cm -3 ) reside in the oxide, which is consistent with the results attained by other techniques. 36

37 V. Modified conductance method with considering the influence of oxide border traps Distortion of conductance curve due to oxide border traps Temperature dependency of the conductance behaviors Evaluation of distribution of interface traps and oxide border traps from conductance curves 37

38 Conductance method with considering oxide traps N. Taoka, et al., Microelectron. Eng., vol. 88 (2011) D it = 3.0e12 cm -2 ev -1 D it = 9.8e11 cm -2 ev -1 ALD-Al 2 O 3 /InP MOSCAP: Same surface treatment, different oxide deposition parameter The influence of oxide traps is negligible: Large amount of active oxide traps: C ox C S C it (w) G p (w) 25. Gp D it ( ) q w max The G p /w versus w plot does not have obvious peak behaviors The influence of oxide traps has to be taken into consideration 38

39 G p /w (mf/cm 2 ) Conductance behaviors with increasing temperature Pt/HfO 2 /Al 2 O 3 /n-in 0.53 Ga 0.47 As near flat-band E E T increases 20, 40, 60, 80 o C t it = (n s N C sv th ) -1 exp( E/kT) where n s = N C exp(- E/kT) t bt = t it exp (2kx) w (rad/s) T, n s, thus t it &t bt low frequency response can be confirmed by high temperature measurement, indicating of existence of the slow traps. No obvious peak behaviors 39

40 N bt (cm -3 ev -1 ) G p /w (mf/cm 2 ) Determination of D it, N bt from conductance curves Symbols: exp. Lines: fitted Pt/HfO 2 /Al 2 O 3 /n-in 0.53 Ga 0.47 As near flat-band For interface traps: Standard conductance method D it = cm -2 ev -1 s s = 60 mev (surface potential fluctuation) t it = s (20 o C), s (40 o C), s (60 o C), s (60 o C), Oxide traps response Interface traps response w (rad/s) 80 o C 60 o C 40 o C 20 o C G p /w characteristics can be well fitted considering oxide traps w/o N bt, D it may be overestimated For oxide traps: Distributed oxide traps model k = 5.5 nm Depth (nm) 40

41 Determination of energy level from T dependence of t it 10-7 t it (s) o C 20 o C 40 o C 60 o C E 0.22eV /kT (ev -1 ) The energy level can be derived from T dependence of previously extracted t it without requiring additional sample parameters 41

42 Chapter 5: Summary of achievements Conductance method is modified to be applicable when there is a large amount of electrically active oxide border traps High temperature conductance measurements are carried out to confirm the oxide traps. Incorporating the influence of oxide traps on conductance, distorted Gp/w versus w curves can be well fitted. Without considering oxide traps, D it may be considerably overestimated, which leads to misunderstanding the origin of defects. Energy level can be easily extracted by various temperature measurement. 42

43 VI. Investigation on interface traps and near interfacial bulk traps in AlGaN/GaN by conductance method Device structure Comparison on conductance spectra in AlGaN/GaN heterojunctions with Ni and TiN electrodes Proposed model for the influence of electrodes on the interfacial traps in AlGaN/GaN heterojunctions 43

44 Devices structure TEOS-SiO 2 TiN /Al /Ti Metal TiN /Al /Ti Al 0.25 Ga 0.75 N (25nm) AlN (1nm) GaN(1mm) Buffer layer (1mm) Si(111) Substrate 2DEG T. Kawanago, et al., ESSDERC2013, Bucharest, Romania (1) Metal electrode: TiN, Ni (2) 25 nm Al0.25Ga0.75N barrier layer (3) 1 nm AlN layer for polarization enhancement 44

45 G p /w (S sec/cm 2 ) G p /w (S sec/cm 2 ) Comparison between AlGaN/GaN and High-k/InGaAs (x10-8 ) E-8 5.0E E-8 3.0E E-8 1.0E-8 Typical interface traps response AlGaN/GaN V g = -6.0V Ni -4.4V -6.0V E+0 1.0E+2 1.0E+3 1.0E+4 1.0E+5 1.0E+6 Frequency (Hz) Conductance spectra (G p /w) in depletion TiN V g = -4.4V (x10-8 ) Frequency (Hz) relatively low D it in the AlGaN/GaN hetero-interface Large amounts of distributed border traps do not likely exist in AlGaN layer distributed border traps response V g = 0.5 V High-k/InGaAs V g = 0.7V 45

46 G p /w (S sec/cm 2 ) D it (cm -2 /ev) (x10-8 ) AC analysis of interface traps in depletion region E-8 5.0E E-8 3.0E E-8 1.0E-8 Conductance spectra (G p /w) V g = -6.0V -4.4V -6.0V V g = -4.4V E+0 1.0E+2 1.0E+3 1.0E+4 1.0E+5 1.0E+6 t (sec) 1.0E E E E D it and time constant (t) TiN TiN 1.0E Ni Ni Frequency (Hz) Gate voltage (V) Ni and TiN electrode: (1) Almost same D it profile in depletion region (5% higher in Ni case) (2) Time constant (t ) is longer in case of Ni electrode 46

47 G p /w (S sec/cm 2 ) D it (cm -2 /ev) (x10-8 ) AC analysis of interface traps in inversion region E E E E-8 5.0E-9 Conductance spectra (G p /w) Ni gate 0.0E+0 1.5E E+2 1.0E+3 1.0E+4 1.0E+5 1.0E TiN gate -3.0V V E+0 1.0E+2 1.0E+3 1.0E+4 1.0E+5 1.0E+6 Frequency (Hz) V g = -4.1V V g = -3.6V t (sec) 1.0E E D it and time constant (t) 1.0E E E Ni TiN Ni and TiN electrode: (1) Almost same D it profile in inversion region (2) Similar time constant (t ) TiN Ni 1.0E Gate voltage (V)

48 Model for carriers trapping in depletion & inversion N vacancies Depletion Inversion Ni TiN Ni TiN AlGaN GaN Trap sites with discrete energy level or position may exist In depletion: There are trapping sites whose energy level and position depend on metal electrode In inversion: There are trapping sites that are less dependent of metal electrode, which may be caused by N vacancies. 48

49 Chapter 6: Summary of achievements Conductance method is applied to analyze the distribution of interfacial traps in AlGaN/GaN heterojunction Traps with discrete energy or position in the AlGaN layer are found near hetero-interface While the traps that influence the depletion region seems sensitive to the electrode, those influence the inversion region are less electrode-dependent 49

50 50 Conclusion Ch.1. Introduction Ch.2. Review of interfacial traps characterization techniques Interfacial traps on Si fins Ch.3. Profiling interface traps distribution on Si fins by charge-pumping method Oxide traps in high-k/iii-v Ch.4. Evaluation of oxide traps distribution by C-V measurement Ch.5. Modified conductance method Interfacial traps in nitride hetero-junctions Ch.6. Investigation on Interface traps and near interfacial bulk traps in AlGaN/GaN by conductance method Ch.7. Conclusion

51 Conclusion of this thesis By adopting proper techniques and proposing models, proper method is chosen and improved to evaluate the interfacial issues of 3D nanostructures, high-k/iii-v MOS systems, and nitrides heterojunctions. Method to evaluate the spatial distribution of D it on Si fins is developed. The results reveal high D it at corners. (Chapter III) Method to profile the distribution of N bt in MOS devices from frequency- and temperature-dependent C-V is developed. The results show a large amount of oxide border traps in high-k/iii-v MOS systems. (Chapter IV) Conductance method for D it characterization is modified to be applicable for the case that there are considerable amounts of oxide border traps. The influences of D it and N bt on the conductance curves are divided. (Chapter V) Conductance method is adopted to evaluate the interfacial traps in III-nitride hetero-junction.. (Chapter VI) 51

52 Future works: guidelines for structure/material optimization Optimizing capture cross-section of the 3D channel, or the curvature of the corners, is important to lower D it. Further physical analysis need to be carried out to clarify the species of the electrical active oxide traps in high-k/iii-v MOS systems. Further work need to be done to identify the species of the traps and corresponding strategy should be proposed 52

53 Publication list (a) 論文 : 3 編 ( フルペーパー ) 論文リスト 1. C. Dou, D. Lin, A. Vais, T. Ivanov, H. -P. Chen, K. Martens, K. Kakushima, H. Iwai, Y. Taur, A. Thean, and G. Groeseneken, Determination of energy and spatial distribution of oxide border traps in InGaAs MOS capacitors from capacitance-voltage characteristics measured at various temperature, accepted by Microelectronics Reliability 2. C. Dou, T. Shoji, K. Nakajima, K. Kakushima, P. Ahmet, Y. Kataoka, A. Nishiyama, N. Sugii, H. Wakabayashi, K. Tsutsui, K. Natori, and H. Iwai, Characterization of Interface State Density of Three-Dimensional Si Nanostructure by Charge Pumping Measurement, accepted by Microelectronics Reliability 3. C. Dou, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, and H. Iwai, Resistive switching behavior of a CeO2 based ReRAM cell incorporated with Si buffer layer, Microelectronics Reliability, vol. 62, no. 4, pp (2012) 53

54 (b) 国際会議 : 2 編 Publication list 1. C. Dou, S. Sato, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai, Si nanowire with asymmetric channel, G-COE PICE International Symposium and IEEE EDS mini-colloquium on Advanced Hybrid Nano Devices, Tokyo Institute of Technology, Japan (Nov., 2011) 2. C. Dou, K. Mukai, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai, Resistive switching behaviors of ReRAM having W/CeO 2 /Si/TiN structure, ECS Trans., vol. 35, no. 4, pp (2011) (c) 国内会議 : 2 編 1. C. Dou, M. Mamatrishat, D. Zade, S. Sato, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai, Resistance switching behaviors in rare earth(ce, Eu) oxide based MIM structures, the 69th meeting of Japan Society of Applied Physics (JSAP), Japan (Spring, 2010) 2. C. Dou, K. Mukai, K. Kakushima, P. Ahmet, K. Tsutsui, A. Nishiyama, N. Sugii, K. Natori, T. Hattori, H. Iwai, Investigation of the effect of Si buffer layer in CeO 2 based RRAM Devices, the 70th meeting of Japan Society of Applied Physics (JSAP), Japan (March, 2011) 54

55 Thank you very much! 55