Reliability of 3D IC with Via-Middle TSV: Characterization and Modeling

Transcription

1 Reliability of 3D IC with Via-Middle TSV: Characterization and Modeling Victor Moroz *, Munkang Choi *, Geert Van der Plas, Paul Marchal, Kristof Croes, and Eric Beyne *

2 Motivation: Build Reliable 3D IC Technology From product idea... Mobile wide IO on logic ~1k TSV 1-2 layers DRAM...to integrated prototype LOGIC Logic die FCBGA substrate LOGIC TSV Backside RDL and Cu µbump Cu µbump SnAg Cu µbump Backside Polymer isolation DRAM DRAM 1

3 3D-Reliability Domains TSV TSV and its environment Stacking Chip Package Interaction Backside Processing 2

4 3D-Reliability Domains TSV TSV and its environment Stacking Chip Package Interaction Backside Processing 3

5 TSV Process Flow via etch oxide liner barrier seed Cu ECD Fill TSV anneal & CMP Top Liner PMD STI Si 5µm Middle Bottom 4

6 Cu Chemistry Impact on Cu Stress 3 Cu chemistries were studied: A, B, and C Chemistry A Chemistry B Chemistry C Chemistry C shows 3 times higher stress exhibits more elastic response 5

7 Cu Chemistry Impact on Cu Grains Chemistry A Chemistry B Chemistry C As deposited Cu film After sintering temperature cycling Grain growth Grain growth No significant 50um grain growth 6

8 Annealing Impact on Cu Properties To understand the evolution of the material response of Cu-TSV w.r.t the applied thermal treatment. Test performed by nano-indentation 7

9 Cu Properties Evolution Nano-Indentation Top FIB Bottom Top EBSD Bottom 8

10 Control of Copper Pumping Model Does the pumping damage barrier oxide and brings charges/traps there? 9

11 Capacitance TSV Parasitic Capacitance 0 C w/o Nit C with Nit Q f Q it VTSV, V Effect of Interface states on MOS C-V... Can we control the oxide charges reliably?... Is the method repeatable and reliable? Interface trapped Charges (Q it ): Exist at the Si-SiO 2 interface Negative interface states cause undesired C-V shift Fixed Oxide Charges (Q f ): Exist near the Si-SiO 2 interface Positive fixed oxide charges cause desired C-V shift Oxide Trapped Charges: May exist in the entire oxide Positive trapped oxide charges cause desired C-V shift Negative trapped oxide charges cause undesired C-V shift Mobile Ionic Charge (Q m ): Undesirable Source: Physics of Semiconductor Devices by S. M. Sze 10

12 TSV Capacitance [ff] Thermo-Cycling Impact on TSV CV TC = 0 TC = 200 TC = 1000 QuasiStatic TC = 0 QuasiStatic TC = 200 QuasiStatic TC = 1000 T = 25 o C; Freq. = 100kHz-1MHz TSV Voltage [V] Thermo cycling: -40 o C (15 min) +125 o C (15 min) No significant change in TSV C-V behavior before and after thermo-cycling 11

13 CV-t: Detect Barrier Integrity Issues Lifetime of carriers is extracted from slope Change of lifetime is indicating Cu migration into Si 12

14 TSV Capacitance [ff] TSV Capacitance [ff] Thermo-Cycling Impact on C-t Freq = 1KHz-10KHz Freq = 10KHz-100KHz Freq = 100KHz-1MHz Quasi Static Temp = 25 o C TSV Voltage [V] TC = 0 TC = 200 TC = 1000 T = 25 o C; Freq. = 100kHz-1MHz Barrier Integrity preserved after thermo cycling Charges in oxide useful for capacitance reduction are harmless and do not deteriorate C- V and C-t behavior after thermocycling Time [sec] No significant change in TSV C-t behavior before and after thermo-cycling 13

15 3D-Reliability Domains TSV TSV and its environment Stacking Chip Package Interaction Backside Processing 14

16 Control of Copper Pumping Model Does the pumping damage interconnects above it? 15

17 R [Ohm] Resistance R [Ohm] TSV impact on M1 M1 meanders around TSVs OPEN ME1 ME2 ME3 ME4 M2 Top M1 Meanders with and without TSVs RES_M2_TSV RES_M2 OPEN_RES_M1-M2_TSV OPEN_RES_M1-M2 M1 Meanders M1 Top No evident impact of TSV Percent % Percent 16

18 Resistance R [Ohm] R [Ohm] TSV impact on M2 M2 meander-fork structures running above TSVs M2 (Top Die) meander-fork OPEN RES. MF AND TSV OPEN RES. MF WITH TSV OPEN RES. MF RES. MF WITH TSV RES. MF 10 4 TSV with starting pad in M1 (Top Die) No evident impact of TSV Percent % 17

19 Delta Ion, % Delta Ion, % TSV Stress Impact on Transistors 6 Transverse Direction 1 Longitudinal Direction Distance From TSV Along Y, um Distance From TSV Along X, um Good agreement of model and Si data No fitting necessary, just using measured Cu properties 18

20 Temperature Impact on TSV Stress Stress drops with temperature: Cu/Si thermal mismatch Linear trend suggests elastic stress behavior Will storage/operation temperature affect this? 19

21 Temperature Impact on TSV Stress Test approach Measure I on before and after thermal storage and cycling Test material HKMG gate stack CMOS technology TSV s: 5mm wide, 40mm deep Two splits in plating chemistry (Chem. D and Chem. E) Test structure Long channel pmos devices (from DAC Array) Reference transistors: > 20mm away from TSV Transistors close to TSV: 1.7mm away from TSV Today: Focus on transitors below TSV (i.e. transverse) 20

22 Ion change of device next to TSV (%) Equivalent Zero Stress Temperature ( C) Temperature Impact on TSV Stress Results before aging ºC ºC 80ºC 80ºC ºC 1 Chem. D Chem. E Chem. D Chem. E 120 Proposed aging tests 1 week at 175ºC ( ezst for chem. D and ezst for chem. E) 150 cycles between -45ºC and 125ºC 21

23 Ratio Temperature Impact on TSV Stress Results after aging 1.5 Proposed parameter: Ratio between %- difference before and after thermal stress T-storage below ezst (chem. D) 0.9 Stress increases T-storage above ezst (chem. E) Stress reduces 0.8 Chem. D T-Storage Chem. D T-Cycle Chem. E T-Storage T-cycling has even bigger impact 22

24 3D-Reliability Domains TSV TSV and its environment Stacking Chip Package Interaction Backside Processing 23

25 3D Stacking Approaches Die-to-wafer bonding approach: fast and accurate pick-and-place step, followed by collective bonding. Process of Record: Cu/Sn Scaling: 40 20µm Cu/Sn Transient-Liquid-Phase, TLP, (250 C) Diffusion bonding (150 C) 24

26 Micro-Bump Impact on N-FET Array BEOL FET array with ubump REF FET array Objective 25um LOGIC Determine Impact of ubump on long channel N-type logic devices Method Dummy ubump LOGIC NUF FEOL Compare Ion of Ref FET array with ubump FET array on stacked dies w/wo NUF 3.62 Device size = 800 x 600nm x16 FET array

27 Micro-Bump Impact on N-FETs Ubump REF FET w/o Ubump REF I ON Column Row FET with Ubump Normalized I ON vs REF Column Row Huge, 40% NMOS current impact! 26

28 Under-Fill Impact on N-FETs ETNA stacks with NUF 1 Cross-section for comparison ETNA stacks w/o NUF Row Row Column Column No underfill no stress 27

29 Normalized Ion wrt REF Cross-Section for FETs Above Ubump MOSFET # in row 6 of the array Si: w/o NUF Model Si: with NUF This effect is easy to model There is apparent ubump misalignment Combination of ubump and NUF has been identified as the main contributor of stress on thinned dies (25um) Stress induced by ubump w/o NEF on the FEOL is around 5% 28

30 Normalized Ion change wrt reference Ubump Stress at Elevated T FET Column FET Column x deg 60 deg 80 deg MOS position in row 6 of FET array Cross-section on FET row 6 Stress drops with temperature 29

31 Normalized Ion Change wrt Reference Ubump Stress vs Temperature Linear extrapolation shows 55% change at 0 degrees Close to linear change of Ion versus T from 25 0 to 80 0 C y = x Temperature, o C equivalent Zero Stress Temperature (ezst) is around Celsius Stress drops with temperature: Cu/NUF thermal mismatch Linear trend suggests elastic stress behavior 30

32 Modeling Micro-Bump Stress Saddle point (tensile Sxx but compr. Syy) Valley bottom (biaxial compr.) Hill top (biaxial tensile) Saddle point (compr. Sxx but zero Syy) 31

33 Modeling Micro-Bump Stress Map of vertical displacement (vertical scale exaggerated) Non-circular features due to anisotropic Si crystal properties Hills over m-bumps, valleys in between 32

34 Electron Mobility Map: 48% Range Strong hills, weak saddles, neutral valleys +42% -6% 33

35 Hole Mobility Map: 77% Range! Strong longitudinal saddles, weak transverse saddles, but neutral hills and valleys +31% -46% 34

36 Summary 35

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