Delamination Modeling for Power Packages and Modules. Rainer Dudek, R. Döring, S. Rzepka Fraunhofer ENAS, Micro Materials Center Chemnitz

Transcription

1 Delamination Modeling for Power Packages and Modules Rainer Dudek, R. Döring, S. Rzepka Fraunhofer ENAS, Micro Materials Center Chemnitz

2 The Micro Materials Virtual Prototyping Finite Element Analysis Optimization Deformation/Stress Measurement MicroDAC e.g. FIB- resolution: 3 nm Diagnostics/Failure Analysis Tomography, SEM, LSM, Testing Temperature, Moisture, Vibration

3 Outline Introduction: Delamination failure and Finite Element Modelling Delamination failure in a plastic power package Stress analyses on a power module with Transient Liquid Phase interconnects Evaluation of interface delamination risk by the Cohesive Zone Method delamination analyses on a sintered power module Summary

4 Important Mechanical Reliability Issues in Electronics Addressed by Finite Element Analysis temperature voltage (Coupled) mechanical analysis mechanical loading fracture fatigue high cycle low cycle overload cracking delamination vibration noise environmental T/moist.-cycle power on-off

5 Examples: Interface Delamination in Electronics SAM Thermo-mechanically driven interface delamination is a major reliability concern SAM X- ray die Glob Top FR-4 Board UF SAM FCoB 20µm

6 Modeling of Interface Delamination Failure by Finite Element Analysis Fracture mechanics based approaches consider the real or fictious presence of initial defects singular crack or delamination tip stress field Cohesive zone based approaches fracture zone of finite size describe interface debonding as the gradual degradation between two materials (avoids crack tip singularity) do not describe a fully brittle fracture, but cohesive parameters were chosen such to describe quasi-brittle fracture fracture criterion: G C cohesive energy, critical fracture energy release rate to cause failure failure criterion has to be chosen in dependence on mode mixity, as delamination toughness in shear loading is much higher than in tension

7 Delamination Analysis of Power IC Package - Cohesive FE Model P-DSO 8 Interface Si (SiO 2 ) to MC (top) Interface heat slug to MC Interface Si (SiO 2 ) to MC (edge) Interface die attach to MC, CZM analysis used to predict interface delamination onset and propagation Scalar stiffness degradation (D) used as damage metric 0.99 D 1 = delaminated

8 Delamination Onset for Package - P-DSO 8 Subjected to Thermal Loading T = C T = C Delamination onset Si-die/MC = Cu-heatsink/MC T = C during a very small temp. decrease, i.e. between -47 C and -48 C maximum degradation shifts to lower leadframe-mc edge Delamination shift

9 Delamination Evolution for Si-Die/ Molding Compound and Heatsink/ MC Delamination occurs by unstable crack growth at one certain temperature Delaminated area in red T = C

10 Delaminated Package P-DSO C out of plane displacement u-y (mm) D deformation 10x delamination complete opening of the delaminated area package undergoes a warpage towards the outer edges

11 Reliability Studies on Power Modules Characteristic control unit for high power (IGBTs on DCB) (PCB) Power Terminals Case Auxilliary Terminals Temperature load Substrate 1 2 Solder Casting Base Plate Soft Casting Characteristic failure mechanism: USM: after 2000 cycles Soft (high lead) solder undergoes cyclic plastic (creep) deformation Solder fails from the outer pheriphery of the joint areas

12 New Interconnects by Transient Liquid Phase (TLP) Soldering Soft (high lead) IGBT die attach is replaced by new TLP solder layer. TLP layer (IMC dominated) is less ductile. Solder fatigue is no longer the dominating failure mechanism. New reliability issues, e.g. delamination of metallizations, due to stiff interconnect! Transient liquid phase soldering layer (Project HotPowCon)

13 Simulations on Failure Risk of IGBTs, TLP-Soldered Symmetry IGBT (10 x 10 x 0.365mm³) Cohesive-Interface DCB Chipmetallis ation solder, optional TLP solder Thermo-mechanical Loading (Temperature loading) Active: P = 440 W, t= 45 ms Cyclic passive 100 Temperatur [ C] Zeit [s]

14 Critical Stresses for SAC vs. TLP Die Attach Risk of brittle fracture/delamination due to stress at IGBT Fatigue failure risk due to plastic strain in solder Stress concentration at chip edge Passive loading Creep strain concentration at solder edge Cooling to - 65 C SAC IMC SAC IMC SAC New interconnection technologies cause shift in failure risk!

15 Evaluation of Delamination Die- Interface for SAC vs. TLP Solder D SAC die attach D IMC die attach No delamination (D = 0) Delamination initiates for adhesion parameters assumed T = - 65 C bad interface adhesion between metallization and die assumed for SAC the damage parameter D is equal to 0 everywhere, i.e. at the entire interface absolutely no risk of delamination for the IMC layer a delamination risk is given in the peripheral region

16 Simulations on Failure Risk of IGBTs, Ag-Sintered On heatsink Die (10.23 x 9.73 x 0.07mm³) Var 1 DCB Copper Cohesive zone interfaces prone to delamin. Sinter Ag (20µm thick)

17 IGBT Loading: Active T-Cycle 3s on /3s off, 700 W T ( K)

18 Delamination Failure Risk of Ag-Sinter Layer Dependent on Adhesion D Good interface adhesion D equally bad interface adhesion D = 1 D = 0 everywhere D = 0 for characteristic good metal-metal adhesion no delamination risk delamiantion starts from periphery, is stable for bad but equal adhesion, upper interface Ag to die metallization is critical D very bad adhesion delaminated zone D = 0

19 Summary More rigid multi-material assemblies in power electronics makes them prone to interface delamination failure. Characteristic low cycle fatigue solder failures become unlikely and are replaced by kinds of brittle failure. Multiple failure modes must be considered in FEA based virtual prototyping. Cohesive Zone Modeling based investigations show great potential to evaluate interface delamination failure.