Design of Power Electronics Reliability: A New, Interdisciplinary Approach. M.C. Shaw. September 5, 2002

Transcription

1 Design of Power Electronics Reliability: A New, Interdisciplinary Approach M.C. Shaw September 5, 2002 Physics Department California Lutheran University 60 W. Olsen Rd, #3750 Thousand Oaks, CA (805) mcshaw@clunet.edu

2 Acknowledgements Overview - MCS 2 Dr. Vivek Mehrotra, Design and Reliability Department, RSC Prof. Elliott Brown, Electrical Engineering Department, UCLA Dr. Jun He, Packaging and Interconnect Department, Intel Mr. Bruce Beihoff, Manager, Solid State Power Assembly Laboratory, RA

3 Variable Speed Drive & Motor Automation System Overview - MCS 3 Variable Speed Drive Performance Metrics: Power Density Cost Reliability AC Motor Converts AC power (fixed frequency, voltage) to AC Power (variable frequency, current, and voltage) Enables exact control of speed (RPM) and torque of motors Motors become controlled electromechanical energy converters.

4 Variable Speed Drive and Motor Applications Factory assembly lines Heating, ventilation and air-conditioning Refrigeration Disc drives / digital storage Electric / hybrid vehicles - commercial and military Rail transport Elevators Actuation of e.g., military aircraft controls, ship controls Practically anything that moves! Overview - MCS 4

5 Variable Speed Motor Drive Block Diagram Electrical Power Input Source Overview - MCS 5 Torque / Speed Control Electronics Electrical Power Electrical Power AC / DC Power Conversion Heatsink Solid State Power Assembly Motor / Load Variable Speed Motor Drive Controlled Mechanical Power Output

6 The Heart of the Motor Drive: The Solid-State Power Assembly Power Terminals Overview - MCS 6 Plastic Housing Silicon Power Transistors Soldered Interconnections Wirebonded Interconnections Ceramic Insulation Gel Metal Baseplate Heatsink Schematic Cross Section of Typical Solid State Power Assembly

7 Thermal Management Goal: Decrease Power Density Between Device & Heatsink Baseplate Power Density ~ 10 5 W/m 2 Overview - MCS 7 5 hp Motor Drive Example Silicon Transistor Power Density = 10 6 W/m 2 Heatsink Power Density ~ 10 3 W/m 2

8 Thin, Large Area Solder Joints Unique to Solid-State Power Assemblies Overview - MCS 8 Examples of Buried, Continuous Solder Layers Schematic Side View Devices Solder Devices Substrate Solder Baseplate Not to scale Copper-Clad Ceramic Substrates 1 cm Copper Baseplate Internal top view of a 1200A, 3300V solid-state module (courtesy: Eupec GmbH+ Co.)

9 Solder Joint Cracking/Delamination Raises Package Thermal Resistance Pristine condition Overview - MCS 9 Substrate Device, T j. Heat.. Solder Heatsink Damaged condition After Some Period of Operation No Heat Flow b/c Fatigue Crack Device. ~. Solder Substrate Fatigue Crack / Delamination Heat

10 Driving Force for Delamination: Mechanical Strain Energy Release Rate, G I Overview - MCS 10 Stress, σ ( α Τ) Z σ 2 h E ( 2 ) 1 υ = GI h Solder Interface Silicon Device Crack Z ~ 0.3 for this geometry E = Young s modulus ν = Poisson s ratio σ = In-plane mechanical stress h = Top layer thickness G I = Applied strain energy release rate α = Coefficient of thermal expansion mismatch T = Range of temperature excursion Substrate Mechanical strain energy release rate, G I, is the applied load

11 Experimental Methodology: Materials and Architectures Overview - MCS 11 Stress, σ xx + σ yy Test Article Z Y 1 inch X h c Silicon Chip H Solder, h s 1/4 Copper Substrate Three silicon device sizes: Small: 0.2 square Medium: 0.6 square Large: 1.0 square Three substrate coefficients of thermal expansion (CTE) Low: Kovar (~ 6 ppm/ C) Medium: mild steel (~12 ppm/ C) High: copper (~17 ppm/ C) Four solder compositions: 97.5Pb/1.5Ag/1.0Sn (T m =309 C) 80Au/20Sn(T m =280 C) 96.5Sn/3.5Ag(T m =221 C) 63Sn/37Pb(T m =183 C)

12 Different Solders Exhibit Large Differences in Delamination 0.6 Overview - MCS 12 80Au-20Sn Solder α = 14.1 ppm /ºC Intact Damaged As Soldered 1 cycle 10 cycles 100 cycles 1000 cycles Sn-Pb or Au-Sn Solder Cu Si 63Sn-37Pb Solder α = 14.1 ppm /ºC Intact Damaged Ultrasonic Acoustic Micrographs

13 Recall: Driving Force for Delamination, G I Overview - MCS 13 Stress, σ ( α Τ) Z σ 2 h E ( 2 ) 1 υ = GI h Solder Interface Silicon Device Crack Z ~ 0.3 for this geometry E = Young s modulus ν = Poisson s ratio σ = In-plane mechanical stress h = Top layer thickness G I = Applied strain energy release rate α = Coefficient of thermal expansion mismatch T = Range of temperature excursion Substrate Greater Damage Suggests Higher Stress and Higher G I..Right?

14 Piezospectroscopy: Stress Mapping through Raman Spectroscopy Overview - MCS 14 Stress-Sensitive Raman Peaks Raman Probe Optical Path 250 Silicon LO Phonon VIEWING SCREEN Intensity (counts/secound) Si Si 200 Cu Wavenumber (cm -1 ) LASER BEAM SAMPLE MICROSCOPE OBJECTIVE Additive Mode Adaptation PMT Double Premonochromator Stag CCD AMP Third Stage PHOTOMULTIPLIER AMPLIFIER Mono 1 Mono 2 Mono 3 SPECTRAL DISPLAY

15 Solder Damage Depends on both Stress and Material Resistance Compressive Stresses, σ xx +σ yy (MPa) Au20Sn Four different solders Silicon Substrate 97.5Pb1.5Ag1Sn 63Sn37Pb σ Position(mm) 95Sn5Ag Damaged Intact Overview - MCS 15

16 Material Resistance, G Ic, Depends on Degree of Cyclic Plastic Work, W p Overview - MCS 16 Stress, σ 1) Plastic Work, W p = σ dε p 2) Low-Cycle Fatigue Life, N f ~ (W p ) m Stress, σ B. B. A. A. ~ C. Strain, ε Strain, ε ε σ Plastic Work, W p Plastic Response Elastic Response ( W p ~ 0 ) Force, F

17 Delamination Only Occurs of G I is Greater than G Ic Stress, σ Overview - MCS 17 Z σ 2 h E ( 2 ) 1 υ = GI vs. G Ic h Solder Interface, G Ic Silicon Device Fatigue Crack Z ~ 0.3 for this geometry E = Young s modulus ν = Poisson s ratio σ = In-plane mechanical stress h = Top layer thickness G Ic = Critical G I for fracture Substrate G Ic is Intrinsic Material Property - G I is Applied Load

18 Thus, Fatigue Life Depends on Response of Solder Material as Compared to G I Different Physical Damage Mechanisms Operate in Different Solders! Overview - MCS 18 Stress, σ Stress, σ B. Damaged B. Difference in Peak Stress Intact ~ A. C. Strain, ε A. Strain, ε Plastic Work, W p Plastic Response: Low Stress (Low G I ), BUT ( W p >> 0 ), so Low G Ic (Crack Resistance) G I Exceeds G Ic Elastic Response: High Stress ( High G I ) BUT ( W p ~ 0 ) so High G ic (Crack Resistance) G I Is Less Than G Ic

19 Back to Our Problem: Unpredictable Performance Changes! Overview - MCS 19 Large Electrical Deviations May Occur During Operation Forward Voltage, V be Packaged Bipolar Power Transistor Should Remain Constant!! Number of Power Cycles, N Now we can apply our detailed knowledge of thermomechanical stress and response of solder (Evans and Evans, IEEE Trans. Comp. Pack., Mfg. Tech., Part A, v. 21 no. 3 pp , 1998)

20 Predicted Electronic Parameter Shift Correlates with Experimental Data Junction Temp, T j 2N3773 npn bipolar I C = 1.5 A V CE = 100 V P D = 150 W B 1 Cycle Time, t C E Bipolar Transistor Change in base-emitter voltage (δv be ) (a) Vbe (V) (b) Experimental (Evans and Evans, IEEE CPMT, 1998) The Problem Predicted The Solution 2N3773 bipolar junction transistor t = 0.8 t = 0.5 N c t = silicon thickness Overview - MCS N c Num ber of Cycles

21 Conclusions Overview - MCS 21 Power Electronics Packaging Demands Highly Interdisciplinary Analyses, Experiments & Knowledge New Methodology Developed to Quantitatively Assess Device/Circuit/System Interactions Resulting from Degradation Rigorous, Physics-Based Coupling of Electronics / Mechanics / Materials / Heat Transfer Interfaces are Crucial Expanding Approach to Explore Biomechanics, Biomaterials Applications and Interactions