NEGATIVE bias temperature instability (NBTI) or the

Transcription

1 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 8, NO. 1, MARCH Effect of the Interfacial SiO 2 Layer in High-k HfO 2 Gate Stacks on NBTI Arnost Neugroschel, Fellow, IEEE, Gennadi Bersuker, Member, IEEE, Rino Choi, Senior Member, IEEE, and Byoung Hun Lee, Senior Member, IEEE (Invited Paper) Abstract A relative contribution of the interface and bulk dielectric defects to negative bias temperature instability (NBTI) in the metal/hfo 2 /SiO 2 gate stacks was investigated. Interface trap generation was assessed by the direct-current current voltage (DCIV) technique, which independently measures the interface defect density from bulk oxide charges and delineates the contribution of the interface defect generation to the overall NBTI measured by the threshold voltage shift ( V TH ). The metal/high-k induced traps in the interfacial SiO 2 layer were found to control the fast transient trap charging/generation processes, which affect the power-law exponents of V TH and the stress-generated interface trap density D IT stress time dependencies. Similar kinetics of the long-term V TH (t) and D IT (t) dependencies in the high-k and SiO 2 gate stacks suggests that the degradation is governed by the same mechanism of trap charging/generation in the SiO 2 film. The investigation leads to a novel methodology for the time-to-failure (TTF) extrapolation, in which the measured V TH and D IT values are adjusted for the contributions from the fast transient defect charging/generation processes. It is shown that the conventional TTF analysis might greatly overestimate TTF. Post-NBTI stress recovery at zero relaxation voltage measured by the DCIV method showed that oxide charges and interface traps relax at the same rate indicating that the interface processes may dominate V TH relaxation. At positive relaxation voltages, however, the oxide charge relaxation exhibits a fast transient component. Relaxation at positive bias also shows an as yet unexplained fast component in the interface trap recovery. Index Terms High-k, interface traps, metal oxide semiconductor (MOS) devices, negative bias temperature instability (NBTI), oxide traps. I. INTRODUCTION NEGATIVE bias temperature instability (NBTI) or the threshold voltage shift V TH in MOSFETs stressed at elevated temperatures is of a major concern for the reliability of MOSFETs with both SiO 2 [1] [7] and high-k gate stacks [8] [10]. In the SiO 2 and SiON gate dielectrics, the NBTI Manuscript received July 1, 2007; revised September 4, A. Neugroschel is with the Department of Electrical and Computer Engineering, University of Florida, Gainesville, FL USA ( neug@ufl.edu). G. Bersuker and B. H. Lee are with SEMATECH, Austin, TX USA. R. Choi was with SEMATECH, Austin, TX USA. He is now with School of Materials Science and Engineering, Inha University, Incheon , South Korea. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TDMR has been predominantly attributed to the H dissociation from the Si H bonds at the SiO 2 /Si interface and subsequent diffusion (and, possibly, trapping) of the hydrogen species into the dielectric leaving behind (positively charged) Si dangling bonds. The reaction diffusion (R D) models vary on defining the major driving force for H dissociation [1], [3], [4], [11] and the relative contribution to V TH shift from the interface and bulk defects. Charging of as-grown hole traps and generation of new hole traps near the Si/SiO 2 interface may significantly contribute or even dominate V TH during an NBTI stress, particularly in the case of nitrided oxides [12] [16]. It was also suggested that positive oxide charge buildup may be caused by protons (H + ) released from the P H complexes in the phosphorus-doped Si depletion layer and diffused into the oxide [11]. Introduction of the Hf-based high-k dielectrics and metal gate electrodes as a potential replacement for the SiO 2 / poly-si further complicates reliability evaluation of the gate stack. The HfO 2 gate stack consists, actually, of two layers, a HfO 2 film and a thin 0.5- to 1.5-nm SiO 2 -like interfacial layer (IL), which is grown either intentionally or spontaneously on the Si surface. Thus, a stress-induced change of the threshold voltage V TH of the HfO 2 /SiO 2 stack may include contributions from high-k and interfacial SiO 2 oxide layers. Although degradation of the SiO 2 IL could be expected, in general, to be somewhat similar to that of the conventional silicon dioxide dielectrics, additional defects in the IL caused by its interaction with the metal/high-k film may modify the NBTI kinetics and magnitude. Additionally, the high density of as-grown high-k bulk defects, as well as the fast transient charge trapping/ detrapping (FTC) phenomenon observed in HfO 2 films [17] [19], may lead to new NBTI features. Some recent data obtained using ultrafast ( 100 ns) I D V G measurements have shown that thin 1.3-nm SiON gate dielectrics under the NBTI stress exhibit fast reversible transients [20], [21]. The measured large ultrafast V TH during the stress/recovery phases under the dynamic NBTI stress cannot be explained by the R D model and was attributed to the trapping/detrapping at the preexisting hole traps in the oxide layer [20], [21]. Similarities in the V TH behavior during the NBTI stress in p-channel metal oxide semiconductor fieldeffect transistors (pmosfets) with high-k dielectric and SiON were also noted [9] /$ IEEE

2 48 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 8, NO. 1, MARCH 2008 The main objective of this paper is to systematically investigate the degradation of metal/high-k pmosfets during the NBTI stress to assess the relative importance of the high-k and IL contributions to the instability of transistor parameters. The obtained results demonstrate that during stress and poststress relaxation, the threshold voltage and the interface state density include contributions from the fast and slow components of trap charging/discharging and generation/passivation processes. The results further suggest that the SiO 2 IL is largely responsible for the NBTI in the metal/high-k gate stacks. However, certain NBTI features were found to be quite different from those of the conventional gate dielectrics due to the modification of the composition of the interfacial SiO 2 layer induced by its interaction with the overlaying metal/high-k stack [22]. In particular, the fast NBTI component, which affects the value of the power-law exponent n, used for NBTI evaluation, t n, is significantly enhanced. It is shown that, from a practical point of view, the separation of the fast and long-term degradation components is required to properly assess the relative role of the high-k and IL degradation in the total stress-induced instability (without necessarily committing to a specific mechanism, which will be discussed elsewhere). In this paper, we propose and demonstrate a new methodology for time-to-failure (TTF) analysis in pmosfets with the Hf-based gate stacks that includes separation of the fast and slow processes in the bulk dielectric charging and the interface trap generation. We also show that failure to consider this separation may lead to a significant overestimation of the device lifetime. Although the methodology is demonstrated on the HfO 2 /SiO 2 gate stacks, it is applicable to other high-k gate stacks, as well as SiO 2 and SiON gate oxides. The device preparation and measurement methods data are described in Section II. In Section III, we discuss measurements and data analysis, and propose an approach for the separation of the fast and slow oxide charging contributions. The kinetics of the interfacial degradation in pmosfets during the NBTI stress and the poststress relaxation kinetics are covered in Sections IV and V, respectively. II. SAMPLE PREPARATION TiN/HfO 2 and reference poly-si/sio 2 gate stack n-channel metal oxide semiconductor field-effect transistors (nmosfets) and pmosfets were fabricated on the Si (001) 200-mm wafers using a standard complimentary metal oxide semiconductor transistor process flow, which includes 1000 C/10 s dopant activation and 480 C forming gas anneals. HfO 2 dielectric films have been grown with the atomic layer deposition chemistry TEMAHf+O 3 followed by the postdeposition anneal at 600 CinN 2. The gate electrode was formed by a 10-nm chemical-vapor-deposited TiN film capped with 150 nm of polysilicon. The 3.3-nm SiO 2 gate oxide devices with a polysilicon gate electrode were used as a reference. High-k gate stacks include 4-, 3-, and 2-nm HfO 2 films deposited on either thermal SiO 2 layers grown by the in situ steam generation (ISSG) process and then etched back in a well-controlled process to a desired thickness of 1.1 or Fig. 1. Magnitude of the threshold voltage shift during the NBTI stress (V TH 1V)/relaxation (+1 V) 1000-s cycles on 3- and 2-nm HfO 2 devices at 125 C. Low relaxation bias was selected to prevent stressing during relaxation resulting in incomplete charge detrapping. Both stress and relaxation show fast and slow processes. 1.4 nm, or an HF- or O 3 -treated Si surface that resulted in the about 1.1-nm-thick postprocessed interfacial SiO 2 layer [23]. During the NBTI measurements, a constant-voltage stress was applied to the gates of the transistors with the aspect ratios of W/L = 20/20, 10/1, and 10/0.4 µm, with the source, drain, and body kept at 0 V. Variations of the threshold voltage with the stress time were extracted by using a linear extrapolation from the maximum transconductance point of the I D V G curves at low V DS = 0.05 V. The interface trap density was measured by the direct-current current voltage (DCIV) method [24] [26] on large 20/20-µm devices and by the chargepumping (CP) method using 10/1-µm devices. The stress was interrupted at periodic intervals to collect I D V G, DCIV, and CP data. The total measurement (stress interruption) time was about 2 10 s. III. MEASUREMENTS AND DATA ANALYSIS A. Bulk Transient Effects During the NBTI Stress A distinct characteristic of the HfO 2 film is a mostly reversible and repeatable charge trapping/detrapping shown in Fig. 1 for high-k pmosfets with the 2- and 3-nm HfO 2 gate dielectric deposited on the 1.1-nm ISSG-SiO 2 layer. The stress and relaxation phases exhibit fast and slow components in the V TH degradation. The fast transient stress component is apparent in the magnified linear portion of the I D V G curve in Fig. 2(a), which presents data of the high-k device with the 1.1-nm ISSG/3-nm HfO 2 gate stack (effective oxide thickness = 1.2 nm) stressed at 1.8 V/125 C (E o = 3.4 MV/cm). The threshold voltage shift after the initial 1 s of stress is V TH (1s) = 50 mv, which corresponds to an equivalent stress-induced charge trap density of oxide and interface traps, Q OT (1s)+ Q IT (1s)=C o V TH (1s), or an equivalent trap density of C o V TH /q = traps/cm 2, where C o is the oxide capacitance, and q is the electron charge. V TH (1s) demonstrates strong electric field dependence, as shown in Fig. 3(a), although it is only weakly temperature dependent, as shown in Fig. 3(c). It is important to emphasize that the V TH values in Fig. 2(a) include the effect of spontaneous relaxation occurring during

3 NEUGROSCHEL et al.: EFFECT OF THE INTERFACIAL SiO 2 LAYER IN HIGH-k HfO 2 GATE STACKS ON NBTI 49 Fig. 2. (a) I D V G characteristics of pmosfets with 1.1-nm SiO 2 / 3-nm HfO 2 gate stack before and after several short stress times. The initial V TH (1s) = 50 mv is due to the FTC at the preexisting traps. The oxide field is estimated from E o = (VG V FB V S )/x o,wherev FB is the flatband voltage, V S = 2VF is the voltage drop in Si where V F is the majoritycarrier Fermi potential, and x o is the total physical thickness of the gate stack. (b) DCIV curves for the stress conditions corresponding to the I D V G curves in (a) measured in the top-emitter DCIV biasing configuration (TE-DCIV) with the source and drain junction forward-biased at V PN = 0.2 V. The curves show the magnitude of the base (body) current due to the recombination at the interface traps under the gate versus the gate-base voltage V GB. The bottom curve is the prestress dependence. The other curves are measured at 1, 2, 5, and 10 s, respectively. The initial peak voltage shift is consistent with the FTC from I D V G curves and gives V GB pk (1s) = 45 mv compared to V TH (1s) = 50 mv. (c) Threshold voltage shift and DCIV peak current increase ( D IT ) versus the stress time demonstrating contributions from fast and slow processes. For the stress times > 1 s, each data set [ V TH (t) and I B pk (t)] is fitted with a single power-law function (solid line) for the stress interval from 1 to 10 4 s (see Fig. 6 for the fit within a total stress time range). Fitting the changes of the parameter values during the first 1 s of the stress time (broken line) requires much stronger time dependence (faster process). the dc measurements. The magnitude of the fast transient component seen in Fig. 2(a) can be affected by the fast recovery of the stress-generated interface trap density and/or oxide charge density. To estimate the interface trap contribution to the relaxed V TH (1s) = 50 mv, we use the DCIV [24] [26] data shown in Fig. 2(b), which yield for the interface trap density Fig. 3. (a) Stress voltage dependence of V TH shifts at 125 C for a SiO 2 /HfO 2 gate stack with 2- and 3-nm HfO 2 layers. (b) Stress voltage dependence of V TH shifts at 125 CforaSiO 2 /HfO 2 gate stack with a 4-nm HfO 2 layer. (c) NBTI stresses at various stress temperatures for 3- and 2-nm-thick HfO 2. generated during the first second of stress, N IT (1s) cm 2, as calculated from the increase in the peak DCIV current after the initial 1 s of stress, I B pk (1s). TheDCIV was calibrated by comparing the prestress N IT with that from the CP method (see also Section IV). The DCIV data correlate with the spin-dependent recombination (SDR) measurements, which reflect the density of the Si dangling bonds at the interface (P b centers), as well as E -like centers very near the interface [27]. N IT (1s) translates to the interface contribution of only 3 mvto V TH compared to the measured V TH (1s) = 50 mv. However, this comparison may not be completely correct due to the difference in sensing (that is, relaxation) times during the I D V G and DCIV measurements. To remove this uncertainty, the interface trap density and the oxide charge density were simultaneously extracted from the peak value and the position, respectively, of the same DCIV signal. The DCIV curves in Fig. 2(b) correspond to the I D V G curves in Fig. 2(a). The initial DCIV peak voltage shift due to the FTC is V GB pk (1s) = 45 mv, which should be compared to V TH (1s) = 50 mv.

4 50 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 8, NO. 1, MARCH 2008 V GB pk tracks the flatband voltage shift during the stress [25], V GB pk V FB =[ Q OT + Q IT (V S )]/C o, where Q IT (V S ) is the charge trap density residing in the surface band states, which is dependent on the surface potential V S.At V GB = V GB pk corresponding to V S pk = VF V PN /2 0.3 V [25], most of the donor traps (P b centers) are occupied by electrons and are neutral. Thus, the charge on stress-generated traps residing in the surface band states is approximately Q IT 0, i.e., V GB pk Q OT /C o.on the other hand, in inversion, the interface traps in the I D V G measurement are above the Fermi level and positively charged contributing to V TH =[ Q OT + Q IT (V S = 2 V F )]/C o. Thus, the difference V TH (1s) V GB pk (1s) Q IT (1s)/C o = 5 mv may be attributed to NIT (1s) = cm 2 and comparable to 3 mv independently obtained from I B pk (1s) discussed above. This indicates that the relaxed V TH (1s) is mostly due to the bulk dielectric charges. To explicitly show very distinct time components in V TH shift and interface trap generation during stress, we plot V TH (in millivolts) and I B pk (in nanoamperes) in a logarithmic y-scale versus the stress time [see Fig. 2(c)]. It is evident that fitting each characteristic, either V TH (t) or I B pk (t) requires very different time dependencies for data above and below the 1-s stress time. The first two data points (prestress 0 s and first stress point at 1 s) point to a much faster process contributing to the stress-induced parameter change compared to the slow process for t>1s. The fast and slow components during relaxation are discussed in Section V. Finding the actual magnitude of the FTC without relaxation requires fast pulse measurements in the nanosecond-scale range [20], [21]. We can still, however, show that bulk charging dominates the FTC by estimating the prerelaxed interface trap generation from the measured relaxed data. The magnitude of the interface trap relaxation can be roughly estimated on the basis of the R D model, which yields the following expression for the interface trap density measured after the delay or measurement time t m : N IT (t, t m ) = At n /[1 +(t m /t) 1/2 ] [28], where the term in the numerator is the actual stress-generated degradation after stress time t, and the denominator describes the recovery term. For t m < 5 s, typical for our measurements, this gives [1 +(5/1) 1/2 ] 3, i.e., according to the R D model, N IT is expected to relax by about a factor of 3, which would still make the bulk dielectric charges dominating even when the interface unrelaxed contribution is compared to the relaxed bulk contribution. The positive charge trapping may, in principle, occur in both the interfacial and high-k layer. From positive bias temperature instability (PBTI) experiments in nmosfets, it has been established that the HfO 2 layer contains shallow electron traps, which are responsible for the fast initial trapping resulting in V TH (1s) [18]. On the other hand, the occupied deep gap states corresponding to neutral and positively charged oxygen vacancies in HfO 2 [29] [31] may, potentially, serve as the hole traps. It was previously suggested [32], [33] that the reversible FTC in high-k stacks in pmosfets can be caused by the hole trapping on these preexisting deep traps in the HfO 2 layer, which can communicate with the inverted p+ layer in the Si substrate. A complimentary/alternative FTC process would be Fig. 4. Comparison of the FTC or V TH (1s) for high-k gate stacks with an 1.1-nm interfacial layer fabricated by different processes: HF-last treated Si, O 3 clean, and thermally grown ISSG-SiO 2. The figure also shows the comparison of the ISSG layer before and after NH 3 anneal. associated with the traps in the interfacial SiO 2 layer, in which its quality is greatly degraded by oxygen gettering from the IL layer and its contamination by Hf atoms (in the order of cm 2 ) [22]. Recent SDR measurements have strongly pointed to the stress-induced fast generation of the Hf-related defects in the IL [27]. Defect density associated with oxygen deficiency and Hf contamination may be sufficiently high to be responsible for the observed FTC. To assess the relative contributions of the HfO 2 and SiO 2 layers to the FTC, we stressed three high-k stacks with an identical high-k film of 3 nm and ILs of the same physical thickness ( 1 nm), which were fabricated using different oxidation processes. The layers are the thermally grown ISSG-SiO 2 layer, the chemical oxide grown during the substrate ozone (O 3 ) cleaning, and the oxide film grown during the processing of the high-k film deposited on the HF-last treated Si surface. V TH (1s) plotted as a function of the stress voltage in Fig. 4 clearly shows strong FTC sensitivity to the IL properties: V TH (1s)=42.5 mv for ISSG, 48 mv for O 3, and 85 mv for the HF-last layer, respectively, under the V G V TH = 1.2 V stress condition. This trend matches the trend in the stoichiometry of the SiO 2 layers as reflected in the values of their dielectric constants [22], [34]: the FTC is the smallest for the high-quality thermal ISSG oxide, and it increases in the chemical oxide devices and further increases in the case of the HF-last samples, which exhibit a higher degree of oxygen deficiency as judged by a higher value of their dielectric constants [34]. The large sensitivity of the charge trapping to the quality of the IL suggests that the large and reversible FTC in high-k stacks may include significant contribution due to the hole trapping on the preexisting traps in the IL, similar to the case of the SiON gate dielectrics [14] [16], [20], [21]. This is also consistent with our previous results on frequencydependent CP measurements showing that the stress-induced trap generation primarily occurs within the IL [35]. We need to note, however, that the contribution from the reversible charge trapping at the preexisting deep gap states in the high-k film near its interface with the IL [32] cannot be excluded at this point. Taking into account that the hole trap density in the high-k film near its interface with the IL (N h ) should not

5 NEUGROSCHEL et al.: EFFECT OF THE INTERFACIAL SiO 2 LAYER IN HIGH-k HfO 2 GATE STACKS ON NBTI 51 depend on the high-k film thickness (in the thickness range where the film crystallinity is not affected), one may expect V TH caused by the charge trapping in the high-k dielectric (under the stress conditions used for data collection in Fig. 3) to scale with the high-k film thickness: V TH = qn h t h k, where t h k is the electrical thickness of the high-k film (note that the charges Q = qn h located in SiO 2 near the interface with the high-k film would produce a similar effect). Since the measured difference between the V TH (1s) values of all the high-k films in Fig. 3(a) and (b) (including 3- and 4-nm films, which were demonstrated to exhibit a very similar degree of crystallinity) significantly exceeds the differences expected from the high-k film thickness scaling, one may conclude that the trapping solely in the high-k dielectric cannot explain the FTC phenomenon. Alternatively, an increase in V TH with the thickness of the high-k film suggests a higher trap density in the IL covered by a thicker high-k layer, which is consistent with the earlier observations by electron spin resonance (ESR) measurements [27]. Further support for the suggestion that the defects in the IL may contribute to the FTC is based on the observation that the FTC in the high-k stack with the nitrided (using NH C anneal) ISSG-IL is significantly higher than that of the otherwise identical gate stack not subjected to the NH 3 anneal, V TH (1s) = 55 mv versus V TH (1s) = 42.5 mv, respectively (Fig. 4). NH 3 anneal before high-k deposition is known to introduce nitrogen near the Si interface in the IL layer, which results in the buildup of oxide charge and mobility degradation, whereas high-k layer properties are largely not affected [23]. On the other hand, the decrease in the FTC as the HfO 2 layer deposited on the same 1.1-nm IL is scaled from 4 to 2 nm [Fig. 3(a) and (b)] does not scale with the high-k film thickness indicating that charge trapping in the high-k film alone cannot account for the observed differences in the FTC values. Further evidence for the significance of the IL contribution to V TH is based on the similarity of the degradation kinetics of high-k and SiO 2 devices discussed in Section III-C. B. Comparison of High-k to Baseline SiO 2 Gate Dielectrics To delineate the contributions to the dielectric degradation from the high-k film and the IL, it is essential to compare V TH during stress/relaxation cycles obtained from high-k devices with those of the reference baseline transistors with pure SiO 2 gate oxide. Fig. 5(a) and (b) shows V TH for a baseline device with 3.3-nm SiO 2 gate oxide during stress/relaxation at 4 V/+3 V and the expanded scale I D V G curves measured on the SiO 2 devices during the 3.2-V stress, respectively. The stress/relaxation dependencies for the SiO 2 device in Fig. 5(a) and (b) and the high-k device in Figs. 1 and 2(a) are qualitatively similar except for a much smaller V TH (1s) magnitude in the SiO 2 case even though the stress field is much higher: about 10 MV/cm compared to 3.4 MV/cm for the SiO 2 versus high-k devices (in both cases, devices experienced spontaneous relaxation during stress interruption for the I D V G measurements). As has been recently shown by the ultrafast I D V G measurements in 1.3-nm SiON films [20], [21], as well as by modeling of the possible relaxation processes Fig. 5. (a) Threshold voltage shift during stress/relaxation cycles at 4 V/ 3 V cycles for a baseline pmosfet with 3.3-nm SiO 2 gate oxide and p+ polysilicon gate. The fast V TH recovery cannot be explained by the slow interface trap relaxation process. The slow relaxation tail is attributed to the interface trap repassivation and is only a small fraction of the total recovered V TH.(b)I D V G characteristics of pmosfets with 3.3-nm SiO 2 gate oxide before stress and after several short stress times. The expanded view in the insert shows an initial V TH (1s) qualitatively similar to that for the high-k device in Fig. 2(a). [28], the fast V TH recovery observed after long stresses [see Fig. 5(a)] cannot find explanation within the R D model since it would require unrealistically fast diffusion of the hydrogen species back to the interface to passivate the Si dangling bonds. The observed fast recovery in the high-k device in Fig. 1 and the SiO 2 device in Fig. 5(a) can be assisted by fast hole trapping/detrapping at the oxide traps via a tunneling process [14] [16], [20], [21], although recent simulation results have shown [28] that this process may not be universal. The amount of charge recovered during the relaxation period strongly depends on the magnitude of the positive (discharge) bias applied during the relaxation [21] (see also Fig. 16). The relaxation in Figs. 1 and 5(a) is not complete since the applied relaxation voltage was sufficiently small to prevent additional dielectric degradation due to electron injection from the gate. The slow V TH relaxation tail seen in Figs. 1 and 5(a) could be attributed to the interface trap repassivation. If so, a small magnitude of this slow V TH relaxation suggests that the interface trap repassivation is not effective, in agreement with the SiON results [14]. Regardless of the specific charging mechanisms and trap locations (ILs or high-k layers), the fact that the threshold voltage shift has fast and slow components requires a new methodology for the TTF extrapolation that would separate the

6 52 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 8, NO. 1, MARCH 2008 Fig. 6. (Filled triangles) Measured and (open triangles) adjusted for a fast transient V TH shift versus stress time. (Open circles) V TH shift for the reference SiO 2 device. (Broken lines) Extrapolated least-squares fits. The projected 10-year TTF (> s) is much smaller for the adjusted V TH. Note the very similar kinetics with n 0.2 for the adjusted V TH V TH (1s) and SiO 2, suggesting that the slow process of threshold degradation is controlled by the IL in a high-k gate stack. slow component, which eventually leads to the failure, from the fast component contributing to a parameter change during the initial moment of stress. C. Separation of Fast and Slow Trapping Processes Typical stress time dependence of the threshold voltage change V TH (t) for a device with an HF-last/3-nm HfO 2 gate stack measured by dc (relaxed) I D V G and plotted in log log scale is shown in Fig. 6 as solid triangles. These types of plots are usually used for an extrapolation [36] of parameter degradation measured during stress time (typically s) to the required TTF. Due to the nature of the log log scale, the slope within the measured time range is strongly affected by the initial V TH shift caused by the fast process. Larger initial V TH in high-k stacks leads to the power-law dependence V TH t n with a smaller n. The FTC provides a one-time contribution of V TH (t = t FTC 1s), whereas the degradation during the rest of the stress time is controlled by the slow processes. To verify that the characteristic FTC time constant t FTC is 1 s would require fast (in microseconds) pulse stress measurements similar to those reported for the PBTI in high-k nmosfets [18]. In the absence of such data for pmosfets, it is, nevertheless, reasonable to expect, based on the data presented in Fig. 2(c), that the characteristic time constants for V TH (t) and I B pk (t) dependencies for short stress times t<1sare much smaller than those for t 1 s. The 1-s demarcation value between the fast and slow processes is just a matter of practical convenience from the dc-type measurement standpoint; a 1-s stress is long enough to include all contributions from the fast process while still being negligibly impacted by the long-term process since its typical characteristic times are > 100 s. Therefore, following the approach proposed earlier for the PBTI case [18], to obtain the slope corresponding to the long-term degradation processes, which leads to eventual device failure, one has to subtract the FTC contribution. Since the fast process contribution is assumed to saturate within less than 1 s, it is practically convenient to use the V TH (1s) value Fig. 7. (a) Threshold voltage shift adjusted for the FTC giving the same n = for several different stress temperatures and voltages. (b) Comparison of measured and adjusted threshold shifts for 2- and 3-nm HfO 2 films on top of the 1.1-nm ISSG-SiO 2 IL showing different FTC but the same adjusted threshold shift with n = 0.21 as expected for the same IL. to correct for the FTC. After the subtraction, one obtains a new slope with much larger n 0.2 (open triangles) in Fig. 6, which leads to a significant reduction in the projected 10-year TTF. A large FTC may result in nearly flat measured V TH (t) dependence erroneously exaggerating the device lifetime. For the stress times larger than the crossover time of 10 7 s ( 1 year) in Fig. 6, the measured slope (n 0.1) is expected to merge with the adjusted slope of n 0.2. For t<100 s, the adjusted V TH (open triangles) shows the effect of relaxation with a variable slope factor n. For t>100 s, however, where the ratio of the stress time to measurement (relaxation) time t stress /t measure > 100, the relaxation is insignificant [see also Fig. 17(a)], and the slope becomes constant with n = 0.2, which is a characteristic of the slow process. It is also interesting to note that the slopes n for the adjusted V TH curves of the high-k and SiO 2 devices are very similar, giving n 0.2 [this value was found for a wide range of stress voltages and temperatures in the high-k devices, as shown in Fig. 7(a) for the 1.1-nm ISSG-SiO 2 /3-nm HfO 2 gate stack]. Such similar kinetics should, in fact, be expected if the slow charge buildup occurs in the SiO 2 IL rather than in the high-k layer, as proposed above. This also holds for a 2-nm HfO 2 film, as shown in Fig. 7(b), where the FTC is larger in the 3-nm film, but after subtracting the FTC contribution, the adjusted V TH V TH (1s) t n with n = 0.21 for both 3- and 2-nm films, as expected, if the IL dominates the slow process.

7 NEUGROSCHEL et al.: EFFECT OF THE INTERFACIAL SiO 2 LAYER IN HIGH-k HfO 2 GATE STACKS ON NBTI 53 Fig. 8. Activation energy of V TH for 2- and 3-nm HfO 2 films obtained from the temperature dependence shown in Fig. 3(c) at a stress time of 10 4 s fitted by the Arrhenius relation. Small activation energy suggests tunnelingcontrolled mechanism. Further evidence for charge trapping in the SiO 2 IL during the NBTI stress of the high-k gate stacks may come from the activation energies extracted from the data in Fig. 3(c), as shown in Fig. 8. The weak temperature dependence, with very small activation energies of only mev, is consistent with the tunneling mechanism of the dielectric charging and much smaller than 0.2 ev reported for the interface component of the NBTI degradation in SiO 2 gates [1], [3]. These values are also very close to 60 mev reported for SiON pmosfets [14], [37]. Weak temperature dependence in SiON was attributed to the variation of the effective hole capture cross section with temperature [14]. IV. KINETICS OF INTERFACIAL DEGRADATION We use the DCIV method [24] [26] to simultaneously measure interface trap generation and bulk trap charging during the NBTI stress in high-k and SiO 2 pmosfets [Fig. 9(a) and (b), respectively]. The shift in the peak current position after a short 1-s stress in the high-k device, i.e., V GB pk (1s), is in agreement with V TH (1s) observed by the I D V G measurements [see Fig. 2(a)] and is attributed to a positive charge buildup. At the same time, we also observe a very large fast initial increase in the magnitude of the interface recombination current, which is directly proportional to the initial increase in the interface trap density, i.e., I B pk (1s) D IT (1s). This initial fast increase is followed by a slow process that is similar to that in the reference SiO 2 device [Fig. 9(b)]. In Fig. 9(c), we compare I B pk plotted in the loglinear scale for high-k and SiO 2 devices. As was demonstrated above, in Fig. 2(c), I B pk (t) and V TH (t) for the high-k devices exhibit fast and slow components. On the contrary, I B pk (t) of the SiO 2 device in Fig. 9(c) does not show any contribution from a markedly fast process for the stress duration of < 1s. The question is whether the initial increase in the interface state density D IT (1s) in the HfO 2 gate stack is of similar nature with that in SiO 2, albeit much greater in magnitude. Since the direct comparison of D IT (1s) values in the SiO 2 /HfO 2 and SiO 2 gate stacks is inaccurate due to the difficulties with applying the same stress conditions in both types of gate stacks, we compare the rates of the initial interface Fig. 9. DCIV curves for pmosfets with (a) HfO 2 and (b) SiO 2 gate dielectric before stress and after several short stress times. DCIV curves were measured in the TE-DCIV bias configuration at V PN = 0.2 V. The comparison of the DCIV curves shows that the fast transient in I B pk and V GB pk is enhanced in high-k dielectric. (c) Interface trap generation versus stress time in high-k and SiO 2 devices. The data of high-k devices show contributions from fast (< 1 s; broken line) and slow (> 1 s, a power-law fit; solid line) processes. No fast component is observed in the SiO 2 devices in the total range of stress time (a power-law fit; solid line). trap density increase with the stress voltage, i.e., D IT (1s) versus V G stress, rather than the D IT (1s) values (Fig. 10). The rate of D IT (1s) increase in the HfO 2 devices is very different from that in SiO 2, which points to a different nature of defects generated at the initial moment of stress in the SiO 2 IL in the high-k gate stack. An SDR technique, which combines a DCIV measurement and ESR, and, thus, allows identifying the g-tensor of the electron trapping defect, was applied to the same devices to verify the nature of the fast-generated defects [27]. Whereas in SiO 2, the electrical stress generated only interface Si dangling bonds (P b centers) and bulk (E centers), in the HfO 2 devices, a new very broad signal was observed suggesting

8 54 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 8, NO. 1, MARCH 2008 Fig. 10. Stress voltage dependence of the initial (after a 1-s stress) increase in the peak DCIV current (or an interface trap density) in high-k and SiO 2 devices. A very strong initial increase in the high-k device compared to SiO 2 suggests additional defects associated with Hf atoms in the IL. Fig. 11. Charge pumping current magnitude before stress and after several stress time periods for pmosfets with a 1.1-nm SiO 2 /3-nm HfO 2 gate stack. Measurement performed at f = 1 MHz and pulse magnitude V pulse = 1.5 V. The bottom line is the prestress curve. The large initial increase in the CP current after a 1-s stress is consistent with that measured in Fig. 9(a) by the DCIV method. that the defects generated at the initial moment of stress might be associated with the Hf atoms, which were found to be present in low concentration (about /cm 2 ) in the interfacial SiO 2 layer [22]. To verify that the large initial D IT (1s) shift is not an artifact of the DCIV technique, we have used CP measurements [38] (Fig. 11), which also showed a fast initial increase in the charge pumping current I CP (1s), followed by a slow process, similar to the dependencies found by the DCIV technique in Fig. 9(a). A fast initial interface trap generation stage followed by a slow stage was observed in all HfO 2 samples regardless of stress voltage and temperature. Following the approach of separating fast and slow contributions to the trap generation employed above in the V TH (t) analysis, an extraction of the intrinsic power-law coefficient for the slow interface defect generation process requires subtraction of the contribution to N IT due to the defect of a completely different nature generated at the initial moment of stress. Fig. 12(a) shows the measured stress-generated trap density D IT and the one adjusted for the traps generated during the first moment of stress, i.e., D IT (t) D IT (1s). D IT was calculated from Fig. 12. Comparison of the interface trap degradation kinetics of high-k and baseline SiO 2 gate stacks. The top curve (squares) shows the measured D IT ; the triangles give D IT D IT (1s) adjusted for the initial fast component. The broken lines are the power-law fits with n = Measured D IT suggests saturation for t>10 4 s, whereas the adjusted curve gives an excellent power-law fit with n = 0.16, similar to that of SiO 2 (bottom curve), for at least two decades with no saturation yet at 10 5 s. (b) Stress-generated D IT D IT (1s) for different interfacial layers showing a universal slope n = 0.16 at long stress times (> 10 3 s), where the relaxation error in the slope and the magnitude is negligible [21], [28]. These data and the OFIT data [39] are consistent with the R D model for the interface trap generation with H 2 as the diffusion species. the peak value of the DCIV current, i.e., I B pk, assuming a uniform interface trap density at the midgap and using the mean capture cross section of (σ ns σ ps ) 1/2 = cm 2 [26]. The value for the capture cross section was also confirmed by comparing the prestress D IT from the DCIV measurements with that from the CP measurements. The adjusted interface trap generation follows the power-law time dependence D IT t n, with the n value of = 0.16 for at least two decades of time [Fig. 12(a)] similar to that for the SiO 2 reference devices pointing to a similar nature of defects generated during the long NBTI stress in the high-k and SiO 2 stacks. It should be emphasized, again, that for the data shown in Fig. 12, where the stress time is much longer than the sense delay time (ratio > 100), the error in the magnitude and the slope of the measured D IT caused by spontaneous relaxation of the generated trap during sense measurements is negligible [21], [28]. Fig. 12(b) shows a consistent value n = 1/6 for the high-k gate stacks with different ILs after the subtraction of the initial shift. This may, in fact, be expected since the IL in all measured high-k gate stacks is still essentially SiO 2, although it may contain a very low concentration of Hf atoms and a higher-than- standard concentration of oxygen vacancies [22]. Hence, the dominant interfacial defect is still expected to be

9 NEUGROSCHEL et al.: EFFECT OF THE INTERFACIAL SiO 2 LAYER IN HIGH-k HfO 2 GATE STACKS ON NBTI 55 the Si dangling bonds (P b -like centers), as will be discussed in Section V. This conclusion is reinforced by a comparison of the D IT degradation kinetics of the high-k and SiO 2 gate stacks [Fig. 12(a)]. The interface degradation rate seems to be relatively insensitive to IL quality, as demonstrated by a similar value of the power-law exponent of very different ILs, HF-last and ISSG layers in Fig. 12(b), in contrast to the strong V TH (1s) dependence shown in Fig. 4. The interface trap generation kinetics during the NBTI stress with D IT t n with n = 1/6 has also been recently observed by the fast on-the-fly interface trap measurements (OFIT) [39] using a very fast CP method that minimizes the relaxation effects. The results presented here and in [39] are consistent with the interface R D NBTI model with H 2 as the diffusion species [3], [4]. Some possible reasons for the differences in the slopes for D IT (t) in Fig. 12, and V TH (t) in Figs. 6 and 7 are discussed in [40]. Note also that the measured (without adjustment) D IT (t) curve of the high-k gate stack in Fig. 12(a) shows an indication of saturation for t>10 5 s. However, the slope of the adjusted high-k D IT curve is very similar to that of SiO 2, with no signs of saturation up to 10 5 s of stress. This indirectly justifies the D IT adjustment procedure, which reveals the intrinsic kinetics of the long-term interface trap generation process. A. Separation of Interface and Bulk NBTI Contributions Using stress-generated D IT measured by the DCIV technique, we estimate the interface state contribution to the threshold voltage shift as V TH (Q IT ) = (q/c o ) N IT, where C o is the gate stack capacitance, and N IT D IT E G assuming a uniform interface trap density D IT (E) across the Si energy gap E G. The DCIV curves were measured with the variable forward bias and yielded nearly uniform D IT (E) within about 0.5 ev of the midgap. If the interface trap energy distribution is of the U-shape type, with the D IT magnitude rising toward the band edges of the Si gap, DCIV measurements underestimate the interface trap contribution V TH (Q IT ) to the total V TH. An accurate comparison of the magnitudes of V TH and V TH (Q IT ) is rather challenging because of possible differences in the effect of spontaneous relaxation on V TH and N IT using the I D V G /DCIV measurement sequence (or its reverse) as well as uncertainty in the N IT values calculated from either CP or DCIV data. In Fig. 13(a) and (b), we compare V TH and V TH (Q IT ) for two different gate stacks, 1.1 nm SiO 2 /3nmHfO 2 and 1.4 nm SiO 2 /2nmHfO 2, respectively, both stressed at V G = 1.4 V/75 C. First, note a much larger FTC in the thicker HfO 2 stack, which can be attributed to the lower quality of the thinner 1.1-nm IL affected by a thicker overlaying HfO 2 film [22] and partially to a slightly larger electric field in the 1.1-nm IL. Due to the large FTC, V TH (Q IT ) calculated from the as-measured D IT values is only about 25% of the measured V TH. After subtracting the FTC component, the adjusted V TH values are close to the calculated contribution to V TH from D IT, i.e., V TH V TH (1s) V TH (Q IT ), as expected at a short stress time. At long stress times, however, the adjusted V TH is greater than V TH (Q IT ) Fig. 13. (a) Measured V TH (solid triangles) compared with stressgenerated interface contribution. V TH (Q IT ) (solid circles) shows V TH (Q IT ) V TH for a 1.1-nm IL/3-nm HfO 2 stack stressed at E o 2.3 MV/cm. The FTC-adjusted values (open symbols) are comparable at short times, but significantly deviate at long times due to oxide charging contributions. (b) FTC-adjusted V TH and V TH (Q IT ) for a 1.4-nm IL/ 2-nm HfO 2 stack stressed at lower E o 2 MV/cm. The interface contribution V TH (Q IT ) V TH (within the measurement accuracy of N IT ) due to the reduced FTC at short times, but clearly deviates from V TH (t) at long stress time. The insert in (b) shows similar interface trap generation kinetics with n = 0.16 for 2- and 3-nm films. presumably due to bulk contributions. In contrast, in the absence of a large FTC [Fig. 13(b)], V TH = VTH (Q IT ),except at long stress times where V TH clearly deviates from V TH (Q IT ), again, likely due to the bulk charge buildup. The inset of Fig. 13(b) shows a D IT (t) dependence t 0.16, which is very similar for the 2- and 3-nm HfO 2 stacks. A small difference in the D IT magnitudes likely originates from a higher initial defect density in the thinner SiO 2 IL [22]. B. Comparison of DCIV Parameters With Those Based on SRH Recombination Model To verify that the DCIV method used to characterize the interface degradation during the NBTI stress originates from the recombination process at the stress-generated interface traps (P b centers), we compare the measured DCIV parameters with the ones used in the Shockley Read Hall (SRH) recombination theory [25]. Fig. 14 shows experimental I B V GB curves at several forward biases, i.e., V PN from 0.1 to 0.18 V for high-k pmosfets with a 1.1-nm ISSG-SiO 2 /3-nm HfO 2 gate stack stressed at 1.6 V/10 5 s. The peak voltage V GB pk shifts toward accumulation with increasing V PN in agreement with the theoretical dependence, i.e., V GB pk V F + V PN /

10 56 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 8, NO. 1, MARCH 2008 Fig. 14. DCIV curves for 20/20-µm high-k pmosfets (1.1 nm SiO 2 / 3nmHfO 2 ) in the TE-DCIV biasing configuration for several forward biases V PN. The line through the peak voltage follows the theory [25] predicting the peak shift toward the accumulation with V GB pk V PN /2. for a discrete midgap level model D IT exp(qv PN / 2kT). An excellent agreement between the experiment and the theory confirms that the DCIV current in the stressed high-k pmosfet is due to the electron-hole recombination at the stress-generated traps at the Si/dielectric interface even in the presence of a large density of oxide traps in the SiO 2 IL. The excellent fit to the distributed trap model with a uniform DOS within at least the 350-meV energy range near the midgap [Fig. 15(b)] is consistent with the spin resonance results that show two overlapping signals corresponding to P b0 and P b1 states with a fairly uniform overall density at the midgap [41]. The good fit in Fig. 15(b) also indicates that σ ns σ ps within at least 350 mev at the midgap. It should be noted here that whereas the DCIV method is sensitive to the interface traps (and very near interface bulk traps [27]), the CP method is much more sensitive to the oxide bulk traps [40], with probing depth estimated to be 6 7 Å even at a high frequency of 1 MHz [42]. In contrast to the poststress results in Fig. 15(b), the prestress I B pk V PN dependence cannot be fitted using the uniform DOS model. However, it can be fitted quite well using the model of a discrete trap level located at about 10 kt from the midgap, i.e., E T E I 10 kt, similar to the SiO 2 case [25, Fig. 4]. The discrete-like nature of prestress D IT indicates that the prestress P b center density is reduced below the detectable level by forming gas anneal. The origin of the prestress interface trap distribution requires further investigation and will be discussed elsewhere. The above results clearly show that D IT calculated based on the DCIV data provides correct kinetics of the interface trap generation process. Fig. 15. (a) Dependence of the peak voltage V GB pk on forward bias V PN (open circles). The solid line is the fit to the theory. (b) Peak DCIV current I B pk versus forward bias (open circles). The solid line shows an excellent fit to the SRH theory with a uniform DOS distribution of interface traps within thesienergygap. 2 ln(c ns /c ps ) 1/2 V PN /2 [25], where V F is the bulk majority-carrier Fermi potential. The dependence of V GB pk on V PN is plotted in Fig. 15(a), where the open circles denote the measured points, and the solid line follows the theoretical expression V GB pk V PN /2. The variation of the I B pk amplitude with forward bias V PN is shown in Fig. 15(b). Open circles denote the experimental data, and the solid line through the circles is the theoretical fit to the distributed density of states (DOS) within the Si energy gap with the uniform D IT = cm 2 ev 1 and (σ ns σ ps ) 1/2 = cm 2. The broken line is the theoretical dependence V. P OSTSTRESS RELAXATION EFFECTS Since V TH and D IT values experience recovery during stress interruption, the DCIV method may be particularly useful since it can simultaneously measure oxide charge and interface trap changes (from the position and the magnitude of the peak of the DCIV current, respectively), which allows to compare the stress-induced evolution of V TH and D IT under the condition of the same measurement delay time. Fig. 16 shows poststress relaxation DCIV curves at three relaxation voltages, V G = 0, +1, and +2 V for pmosfets with 1.1-nm IL/3-nm HfO 2 stressed at 2 V for 10 s. Several important features can be noted. 1) The stress-induced DCIV peak amplitude I B pk D IT decreases with the relaxation time, unmistakably indicating that the interface trap density decreases since I B pk recovery is solely due to the reduction of the interface trap density. 2) The DCIV peak voltage V GB pk shifts to the right, indicating a decrease in the positive charge in the dielectric and at the interface. 3) For relaxation with V G =+1 and +2 V, we observe a fast initial V GB pk transient, which is similar to the FTC during the stress discussed above [Fig. 9(a)], but corresponds to the detrapping of the positive charges. This fast relaxation process, which is sensitive to the detrapping

11 NEUGROSCHEL et al.: EFFECT OF THE INTERFACIAL SiO 2 LAYER IN HIGH-k HfO 2 GATE STACKS ON NBTI 57 Fig. 16. Poststress relaxation DCIV curves (TE-DCIV, V PN = 0.4 V) at three relaxation gate voltages, i.e., V G relax = 0, 1, and 2 V. The high-k pmosfet (20/20 µm) was stressed at V G = 2V/10 s at 25 C. The bottom lines (open circles) are the prestress curves. The top curves are the initial relaxation curves at t relax = 0 s. The additional curves are measured at 3, 10, 100, 300, and 1000 s, respectively. The arrow in the bottom figure shows the fast field sensitive interface recovery transient for V G relax > 0V. (positive) voltage, is followed by a slow process. For long relaxation at +2V,V GB pk has shifted further to the right of the unstressed value, indicating an electron injection from the strongly accumulated layer in the Si substrate. 4) In addition to the V GB pk transient, we also observe a field-dependent fast interface trap relaxation of I B pk or D IT at positive relaxation biases, which is labeled in the bottom of Fig. 16. The recovered fraction of V GB pk and I B pk as a function of relaxation time is plotted in Fig. 17(a). For V G relax = 0 V, both values relax at exactly the same rate, i.e., % V GB pk (t) =% I B pk (t), from the initial stress-induced V GB pk = 80.4 mv and I B pk = pa, suggesting a common relaxation mechanism. Since I B pk (t) is independent from oxide charges, it indicates that the V GB pk (t) recovery at 0 V might be predominantly due to the repassivation of the interface traps. At the positive recovery bias (V G relax = +1 V), however, we note a transient in both V GB pk and I B pk. Furthermore, V GB pk (1s) recovery is much larger, and the relaxation rates for V GB pk and I B pk are different. Fig. 17. (a) I B pk and V GB pk recovery (in percent) from DCIV curve peak current and voltage, respectively, for V G relax = 0and1V.For0V, both curves relax at the same rate. For 1 V, we see a fast initial component in both curves and different relaxation kinetics for I B pk (interface) and V GB pk (interface plus bulk). (b) I B pk during relaxation in a log-linear scale for three relaxation voltages in high-k pmosfets. Open symbols are for baseline 3.3 nm SiO 2 relaxed at 0 and 3 V after a 4-V stress for 100 s. Similar relaxation kinetics for high-k and SiO 2 devices suggests a common mechanism for interface trap repassivation. (c) I B pk I B pk (1s) after adjustment for the initial fast contribution plotted in the log log scale. The very weak field dependence for high-k and SiO 2 devices suggests a diffusion-limited interface trap repassivation mechanism. A field-dependent V GB pk recovery is expected for a process involving positive charges, for instance, holes detrapping from the bulk oxide traps [14] [16], [43], [44], or protons [11]. The field-accelerated D IT recovery is observed in the SiO 2 devices as well [Fig. 17(b)] and could be caused by H + biasdriven toward the interface causing the initial fast interface trap repassivation, which was also suggested in [45]. This supposition needs, however, further verification. One needs to note that the large sensitivity of D IT relaxation to the positive relaxation voltage, as illustrated in Fig. 17(a) by the I B pk relaxation at V G relax = 1 V in the high-k

12 58 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 8, NO. 1, MARCH 2008 Fig. 19. Long-time (11.57 days) interface trap recovery at 0- and +1.5-V relaxation voltages for high-k pmosfets stressed at 2 V/10 4 sat 25 C. The open triangles correspond to the adjusted I B pk I B pk (1s) relaxation curve. Fig. 18. (a) V GB pk relaxation at different relaxation voltages as a function of relaxation time at 25 C. The initial V GB pk (1s) shift reflects a fast relaxation transient. Open symbols give the adjusted shifts after subtracting the initial fast contribution. (b) Temperature dependence of V GB pk relaxation. device, and in Fig. 17(b) for the SiO 2 device at V G relax = 3V, may compromise the NBTI stress kinetics data collected by the charge pumping measurements, which employ high positive bias (Fig. 11). On the other hand, the I D V G and DCIV measurements are performed in the V G < 0-V range [Fig. 2(a) and (b)] resulting in a lesser relaxation rate [40]. Similar relaxation kinetics for SiO 2 and high-k devices shown in Fig. 17(b) suggests a common mechanism of interface trap repassivation. After the subtraction of the fast component [Fig. 17(c)], the adjusted interface trap relaxation I B pk I B pk (1s) demonstrates a weak field dependence expected from a hydrogen diffusion-limited interface trap repassivation process. The measured V GB pk plotted versus relaxation time in Fig. 18 (solid symbols) exhibits fast and slow components. Note a significant fast transient magnitude V GB pk (1s) = 70 and 30 mv, for relaxation at 2 and 1 V, respectively, compared to only = 3 mv at 0 V. Furthermore, the dependencies obtained with the 2- and 1-V relaxation biases are nearly straight lines with a small slope due to the combination of large fast (< 1 s) and much smaller slow relaxation processes, similar to the stress case in Fig. 6. Following the stress methodology, we separate the fast initial relaxation process from the slow relaxation process by subtracting the first measured point, i.e., V GB pk (1s), which results in the adjusted curves shown by the open symbols in Fig. 18(a). After subtracting the large initial transient, V GB pk relaxation values at all gate biases exhibit very similar relaxation time dependence (all adjusted open-symbol curves have the same shape, and the 1- and 2-V curves are nearly identical) controlled by the slow relaxation process that may include contributions from both the positive charge in the dielectric bulk and the interface recovery. The bulk charge relaxation kinetics at different temperatures at V G relax = 0 V is presented in Fig. 18(b). Note that at t = 1 s, the as-measured values are independent of the temperature, suggesting that the fast (transient) detrapping process is of tunneling nature. For t>1s, one observes a larger V GB pk magnitude at 125 C compared to that at 25 C that may be interpreted in terms of a temperature-activated slow charge migration between the traps. As expected, the adjusted V GB pk values exhibit a similar relaxation time dependence at all temperatures (a parallel shift of the time dependence curves). The top curve, labeled as t = 0 s in Fig. 16, is obtained at 1 s after the termination of the stress, which is the time needed to switch from the stress to the measurement mode. The same delay affects other DCIV data in Fig. 16. However, these delays have only a small effect on the relative recovery fractions in Fig. 17(a) since, as already mentioned above, I B pk (t) and V GB pk (t) are simultaneously obtained from the same peak value of the DCIV curves. Last, in Fig. 19, we investigate the interface trap recovery after a s stress at a rather high-voltage stress at 2 Vfor 10 4 s, which generated about D IT cm 2 interface traps. The stress is followed by a relaxation for up to t relax = 10 6 s (11.57 days), or t relax /t stress = 100, at 0- and +1.5-V relaxation voltages. The data show that only about 40% of the NBTI stress-generated traps recovered during the relaxation time of 10 6 s when the D IT recovery already shows strong signs of saturation. This result is in contradiction to the R D model, which predicts nearly complete recovery due to the trap repassivation for t relax /t stress > 100 [4], [28]. V GB pk also saturated at about 30% and about 50% of the stress-generated shift at 0- and 1.5-V relaxation voltages, respectively. The D IT fraction not recovered during the relaxation seems to be insensitive to the stress time, as seen by comparing Fig. 17(a) for a short stress with Fig. 19 for a long stress. A permanent nonrecoverable D IT has been recently reported using CP measurements [46] in nitrided SiO 2. However, as was discussed above, the CP method suffers from a very significant relaxation, which may lead to a less sensitive assessment of the fraction of the recovered D IT compared to the DCIV method.

13 NEUGROSCHEL et al.: EFFECT OF THE INTERFACIAL SiO 2 LAYER IN HIGH-k HfO 2 GATE STACKS ON NBTI 59 The data in open triangles in Fig. 19 correspond to the D IT relaxation values under the +1.5-V condition adjusted to the initial D IT (1s) transient. The adjusted curve is nearly identical to the 0-V curve, suggesting that the initial fast transient recovery is due to a field-driven process, which is superimposed on the slow (repassivation) process. The observed incomplete repassivation (< 50%) may have important implications for TTF predictions for the NBTI stress. VI. CONCLUSION A systematic investigation of the NBTI in SiO 2 /HfO 2 /metal gate stacks was performed to assess the relative contributions of the metal/high-k and SiO 2 layers to the threshold voltage shift and the interface state generation. The results show that V TH and D IT during stress and relaxation contain fast and slow components that are similar to those observed in thin SiON films [14], [21]. The fast V TH component (FTC) could be due to the charge tunneling process, for instance, from the substrate into the preexisting traps (or the trap precursors) in the dielectric. The trap density associated with the FTC is in the order of cm 2, which is reasonable for the SiO 2 IL degraded by oxygen gettering induced by the high-k/metal gate stack [22]. The FTC is reversible; the trapped charge can be detrapped, which occurs more effectively when a positive bias is applied to the gate. High-k and SiO 2 gate stacks show a similar long-term growth rate of the stress-generated interface traps, i.e., D IT t n, n , as monitored by the DCIV technique. For short stress times (< 1 s), an additional fast interface trap generation has been observed in the metal/high-k gate stacks, which could originate from the as-processed precursor defects. SDR measurements [27] indicate that this fast interface trap generation could be associated with defects that are related to the Hf atoms, in which the density in the IL was found to be in the order of cm 2 [22]. To separate the fast trap generation process from the slow one, which is responsible for the long-term D IT degradation, an analysis procedure is proposed where the contribution of the fast transient trap generation process is approximated by the D IT value after the first 1 s of stress, i.e., D IT (1s). The slow conventional interface trap generation is then obtained by subtracting D IT (1s) from the measured D IT (t) dependence. This procedure results in physically correct kinetics of the slow process in the high-k gate stacks, which is similar to SiO 2. The share of the interface trap contribution to the total V TH magnitude was found to increase with respect to the bulk dielectric charging contributions when the high-k film thickness is scaled down. Poststress recovery was investigated by the simultaneous measurement of the oxide charge and the interface trap relaxation using the DCIV method. At zero relaxation voltage following an NBTI stress, the oxide charges and the interface traps relax at exactly the same rate indicating, thus, that the interface processes may dominate the observed V TH relaxation. At positive relaxation voltages, however, the oxide charge relaxation exhibits a fast transient component, and its relaxation rate is different from that of the interface traps, indicating that the fast processes that are different from those controlling the interface trap relaxation (in particular, holes detrapping via tunneling [32], [33]) may play an important role. Relaxation at the positive bias also shows an as yet unexplained fast component in the interface trap recovery. An incomplete interface trap recovery or repassivation (< 50%) was observed for a long relaxation time of 10 6 s (11.57 days) in an apparent contradiction to the R D model. The initial FTC-related V TH and D IT values, which are likely to be associated with metal/high-k processing-induced defects in the IL layer and do not contribute to a long-term degradation, strongly affect (lower) the slope of the powerlaw V TH ( D IT ) t n dependence in the log log scale. As a result, the conventional method for the TTF estimation using straight-line extrapolation from the measured log log plotted data overestimates the TTF. Extraction of the intrinsic NBTI power-law exponent value characteristic of the slow process of the dielectric charging and the interface trap generation that eventually leads to the device failure requires correcting of the measured V TH (D IT ) shift for the fast transient contribution. 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Lee, Characterization, modeling, and minimization of transient threshold voltage shifts in MOSFETs, IEEE J. Solid-State Circuits, vol. 29, no. 3, pp , Mar [45] B. Kaczer, V. Arkhipov, D. Degraeve, N. Collaert, G. Groeseneken, and M. Goodwin, Disorder-controlled-kinetics model for negative bias temperature instability and its experimental verification, in Proc. Int. Rel. Symp., 2005, pp [46] V. Huard, C. Parthasarathy, N. Rallet, C. Guerin, M. Mammase, D. Barge, and C. Ouvrard, New characterization and modeling approach for NBTI degradation from transistor to product layer, in IEDM Tech. Dig., 2007, pp Arnost Neugroschel (M 76 SM 80 F 90) received the B.S. degree in electrical engineering from the Slovak Technical University, Bratislava, Slovak Republic, in 1965 and the Ph.D. degree in electrical engineering from Technion Israel Institute of Technology, Haifa, Israel, in From 1973 to 1975, he was a Research Associate with the University of Illinois, Urbana. In 1975, he joined the Department of Electrical and Computer Engineering, University of Florida, Gainesville, where he is currently a Professor of electrical engineering. He spent the summer of 1982 at the IBM T.J. Watson Research Center, Yorktown Heights, NY, where he worked on the properties of polysilicon contacts in bipolar transistors. From September 1985 to June 1986 he was at SEMATECH, Austin, TX, as a Visiting Scholar working on the reliability of high-k MOSFETs. He was on a sabbatical leave in 1996 at the Interuniversity Microelectronics Center, Louvain, Belgium, studying the properties of amorphous silicon for solar cell applications. His current research interests include semiconductor device physics, semiconductor material and device characterization, and the reliability of high-k MOSFETs.

15 NEUGROSCHEL et al.: EFFECT OF THE INTERFACIAL SiO 2 LAYER IN HIGH-k HfO 2 GATE STACKS ON NBTI 61 Gennadi Bersuker (M 95) received the M.S. degree in Physics from Leningrad State University, Saint Petersburg, Russia, and the Ph.D. degree in physics from Kishinev State University, Chisinau, Moldova. After graduation, he joined the Moldavian Academy of Sciences, Chisinau. Then, he was with Leiden University, Leiden, The Netherlands, and the University of Texas at Austin. Since 1994, he has been with SEMATECH Inc., Austin, as a SEMATECH Fellow, working on process-induced charging damage, electrical characterization of Cu/low-k interconnect, high-k gate stacks, and advanced CMOS process development. He has more than 200 publications on electronic properties of dielectrics and semiconductor processing and reliability. Rino Choi (M 04 SM 05) received the B.S. and M.S. degrees from Seoul National University, Seoul, South Korea, in 1992 and 1994, respectively, and the Ph.D. degree in materials science and engineering from the University of Texas, Austin, in From 1994 to 1999, he was with Daewoo Motors Company as a Development and Test Engineer. Since 1999, he has studied various high-k dielectrics. After graduation, he was with the SEMATECH, Austin, working on the electrical characterization and the reliability of advanced gate stacks. Since September 2007, he has been with School of Materials Science and Engineering, Inha University, Incheon, South Korea. He has published more than 50 journal and conference papers. Byoung Hun Lee (SM 05) received the B.S. and M.S. degrees in physics from Korea Advanced Institute of Science and Technology, Daejeon, South Korea, in 1989 and 1992, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Texas, Austin, in From 1992 to 1997, he was with Samsung Semiconductor. From 2001 to 2007, he was with IBM. Since 2007, he has been with the SEMATECH, Austin. He is the author or the coauthor of more than 300 journal and conference papers in various semiconductor research areas, including gate oxide reliability, SOI devices and processes, strained silicon devices, and high-k and metal gate processes and devices. He is currently managing three technical programs including a metrology project, a high-k dielectric project, a metal electrode project, a dual metal gate CMOS integration project, a memory project, and an electrical characterization project.