Negative Bias Temperature Instability Characterization and Lifetime Evaluations of Submicron pmosfet

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1 Negative Bias Temperature Instability Characterization and Lifetime Evaluations of Submicron pmosfet S. F. Wan Muhamad Hatta a, H. Hussin *a, b, F. Y. Soon a, Y. Abdul Wahab a, D. Abdul Hadi a, N. Soin a, A. H. M. Zahirul Alam c, A. N. Nordin c a Department of Electrical Engineering, University of Malaya, Kuala Lumpur, Malaysia b Center of Electronic Engineering Studies, Universiti Teknologi MARA, Selangor, Malaysia c Department of Electrical & Electronic Engineering, International Islamic University Malaysia, Kuala Lumpur, Malaysia corresponding author: hanimh@salam.uitm.edu.my Abstract A major effect of different measurement delay in seconds is revealed through quasi DC Stress Measure Stress experiments. We found that different delay of measurements in seconds contributed to different stress time needed to achieve target 10% degradation of Vth. The longer delay, the more time needed for the device to achieve 10% degradation of Vth. The effect on NBTI degradation is shown to be reliant on stress conditions (stress voltage, temperature) and device architecture (gate dimensions, gate oxide thickness). The NBTI lifetime was predicted by extrapolating lifetime to the nominal operating voltage from Time-to-Fail versus stress bias and oxide electric field plots. Both plots show that the lifetime of degradation parameter of Vth is lower compared to the lifetime of degradation parameter of Idsat. Keywords negative bias temperature instability (NBTI); pmosfet; semiconductor reliability estimation; threshold voltage instability; interface states I. INTRODUCTION The NBTI degradation is an important mechanism to consider when designing pmosfet since it causes a systematic shift in transistor parameters, specifically the drive current, transconductance, and threshold voltage, when the device is biased in inversion [1]. This in turn will lead to reduction of the transistor s speed and accelerates failure for logic and analog circuits. This degradation mechanism is further enhanced by the scaling of the transistor [2], the increase of temperature due to high dissipation of power and the increase of the electric field in the gate oxide. Similar to hot carrier degradation [3], the threshold voltage shift and instability due to NBTI need to be fully evaluated and modelled for ultra short channel device. It has been reported that the essence and consensus of the NBTI phenomenon are as the follows: (1) The degradation is fielddriven and is related to interface traps at the Si/SiO 2 interface; (2) Threshold voltage degradation due to NBTI is given by V th ~ A exp(-ne D/kT) t n with n ~ ; (3) Once NBTI stress is removed, a fraction of interface traps can self-anneal [3,4,5]. The concept of the Reaction Diffusion (RD) model has been commonly applied [7] to interpret the NBTI degradation mechanism and in this framework, the NBTI degradation is assumed to emerge due to hole-assisted breaking of Si-H bonds at the Si-SiO 2 interface. Numerical solution of the RD model [8] has shown that the time exponent n is dictated by the diffusing species and n is a sensitive measure of the diffusing species. Among the various exponents (n = 1/2 for proton, n = 1/6 for molecular H 2, n = 1/4 for atomic H), only the diffusion of atomic H appeared to be consistent with experimental results, as will be shown in the later sections. Recent studies have also indicated that the R-D model is questionable as the exponents are different from RD model [9]. But, by looking at the most recent work, the model is still applicable to explain the existence of Nit which the development of carrier separation method [10] is applied to explain the role of hole trapping effect and interface trap [11] thus validity of R-D model is guaranteed. The validity of R-D model is confirmed as the exponents obey the model after applying the carrier separation method [10]. In addition to time exponents, the activation energy of NBTI is also extensively studied in this work and various reports [12, 13] suggest that E a ~ ev. This paper will focus on the NBTI characterization based on the quasi-dc method of measurement (Stress-Measure-Stress). The time dependence of NBTI characterized by parametric shifts of pmosfet transistors is investigated and the transistor lifetime extraction will also be evaluated. The following section will elaborate on the devices used and experiment details. The subsequent sections discuss on the experimental results obtained by first focusing on the NBTI degradation effect on the standard 10 μm/0.18 μm pmosfet and subsequently looking at the NBTI degradation effect on varying W/L transistors. II. DEVICE AND EXPERIMENT DETAILS Keithley 4200 Semiconductor Characterization System (SCS) was used to perform the pre- and post-stress quasi-dc characterization on the sample wafers. The devices used in this study are p + -gate MOSFET fabricated on a standard 0.18 μm single poly dual-gate CMOS process, with thin gate oxide grown on dry oxidation and thick gate oxide grown on wet oxidation. A variation of transistor geometric properties under different /17/$ IEEE 206

2 bias conditions was observed in studying the impact of NBTI degradation on pmosfet. Thin gate oxide transistors (~3 nm) of different W/L properties respectively were compared with the thick gate oxide transistor (~5.6 nm) and their time-dependence degradation effects were studied. NBTI measurements involve the application of stress voltage to the gate that is higher than the nominal supply voltage (V DD = -1.8 V) and at high temperature in order to accelerate degradation. The higher stress voltage value as compared with the nominal supply voltage is based on most prominent researches in this area [14,15]. It is important to keep the stress voltage in the range of low to moderate to avoid impact ionization. The applied high stress voltage results in higher Vt and explains the contribution of oxide trap, Not together with interface trap, Nit which in turn degrade the performance of the devices [15]. The source, drain and substrate contacts were grounded in this experiment [1]. The wafers were subjected to different stress temperatures of 105 C, 125 C and 145 C. The range of the applied stress bias at Gate, V g was between -2.8 V to -3.4 V [16]. The stress were periodically interrupted and the following device parameters were measured at nominal voltages to monitor device degradation under stress: I dsat, subthreshold slope and V th. V th is the threshold voltage extracted through the constant current method, where V th is defined as V g at I d = -0.1μA*W/L. We had executed two different quasi-dc methods to observe the NBTI degradation of the transistors on the wafers, one of which has a longer delay (~ 9 second) in between stress and another favours a relatively smaller delay (~ 1 second). The effects of these delays on the NBTI degradation are presented in the following section. In this work, the NBTI Time-to-Fail (TTF) is defined as the time when the device parameters reach 10% of degradation. If degradation does not reach this limit, the TTF is estimated by extrapolating the degradation with respect to time using a power-law model (e.g. I dsat ~ t n ) which is fitted to the measured data. III. EXPERIMENTAL RESULTS AND DISCUSSION This section presents the experimental results obtained from the quasi-dc characterization and the analysis on the impact of NBTI degradation on the pmosfet transistors. The following subsection will discuss on the NBTI degradation on the thin gate oxide 10/0.18 μm pmosfet transistor and the NBTI characteristics will be analysed from the parametric degradation of the transistor, specifically the threshold voltage shift, subthreshold slope shift and drain current shift. Further observation on the NBTI degradation was carried out by analysing the field dependence and temperature activation on the threshold voltage shifts. The correlation coefficients of each of the fitting curves in the plots presented below are all > 0.98; which means that the measured data and the fitting curves are almost closely fitted together. A. NBTI Degradation on Thin Oxide p MOSFET transistor The NBTI-induced V th degradation dependence on the stress time is shown on Fig. 1(a) to Fig. 1(c). The experimental V th data is plotted on log-log scale versus stress time, and it is observed that the V th obeyed the power-law dependence of stress time with a fractional time exponent, n in the range of This indicates the dominant mechanism in the degradation is the diffusion controlled reaction. The diffusing hydrogen species is atomic hydrogen. The experimental results are consistent with similar experimental approach, quasi DC Stress Measure - Stress where n is between 0.2 to 0.3 [14]. n varies for the cases of different measurement approach, for e.g. n is ~ if using Slow On The Fly [10] and n is ~ if using Fast On The Fly or Fast Id-Vg method [17]. For the case of V g = -3.4 V, the V th shifts towards more negative values which indicates generation of fixed oxide charges and interface trap states after stress and can be approximated by a power law relationship, V th = Ct n, with exponent n ~ The other stress biases, V g = -3.2 V, -3.0 V and -2.8 V follow the same behaviour and having similar time exponents, n as presented in Fig. 1(a). This indicates that the time-dependent exponent is almost independent of the electric field across the gate oxide. The n exponent value is in good agreement with published results (n ~ 0.25) for bulk pmosfet [13]. Fig. 1(b) shows the V th degradation extracted using the constant current method but with different measurement time delays between stopping the stress for measurement and the start of the next stress phase. The method which resulted in the longer delay of ~ 9 second is a result from the complete I d-v d and I d-v g sweep measurement in between stress cycle while the shorter delay of ~ 1 second is a result of an optimized I d-v g sweep in between stress cycle. It is observed that the 8 second difference in delay had resulted in a significant difference in V th degradation which may lead to an underestimation of device lifetime extrapolation. From the Fig. 1(b), for a stress bias of -3.4 V, the shorter delay reaches the targeted degradation mark at 100 second stress while the longer delay at 300 second stress. While at -2.8 V of stress bias, the characterization with a shorter delay reaches the targeted degradation at 2000 second while at longer delay, the device reached targeted degradation at 7000 second. Additionally, higher n value was obtained for the longer delay measurement as compared to the measurement with shorter delay. This may suggest that a characterization method which suffers higher delays and stressed at lower stress biases may result in a higher underestimation of the degradation effects. The difference in the degradation effects for different time delays in the measurement can be attributed to the recovery effects which may have occurred more significantly during the longer delay [10]. This could also suggest that the V th is a combination of interface trap generation ( V IT ) and hole trapping or in other terms, the fixed oxide charges ( V OT). It has been reported that the interface trap generation, N IT, is highly modulated by the delay time [12] and hence it will be shown that the main contributing factor detected by the current measurement applied in this work is the N IT, which causes the degraded shifts in the transistor parameters. It is suggested from this observation that the delay between stress and measurement needs to be reduced or completely eliminated to avoid complications due to recovery effects. Fig. 1(c) presents the effect of various stress temperatures on the time evolution of the threshold voltage degradation, V th. It is observed that the degradation exponent, n slightly increases with the increase in stress temperature. This may be explained 207

3 by the fact that the lower temperature stress could result in slower hydrogen species dispersive diffusion with lower carrier hopping probability [18]. Lower carrier hopping probability would mean that the diffusing hydrogen species would have more time to relax to deeper states with longer release time. Hence at lower temperature, the observed degradation exponents are lower. The carrier hopping probability will be much higher at elevated temperatures and hence the probability of getting trapped into deep level is reduced. Thus, this explains the higher value of degradation exponent at higher temperature Fig. 2 presents the relationship between percentage change in subthreshold slope and threshold voltage. The linear relationship observed again suggests that the interface state generation, N IT as the primary degradation mechanism under NBTI stress. Another non-dominating degradation mechanism that may have induced by the bias temperature stress could be the fixed oxide charges, N OT. The contribution to V th caused by fixed oxide charges ( V OT) is less and these oxide charges cannot be easily detected due to the delay during measurement when the stress is interrupted. If the V th is fully due to the interface traps, the V th would follow power law dependence with the exponent factor, n ( V th ~ t n ) as can be seen in Fig. 2. Hence it can be stated that the V th measured by the DC method in this work is mainly due to interface traps, N IT. (c) Fig. 1 (a) V th degradation extracted using constant current method with measurement delay ~ 9 second. (b) Comparison of NBTI-induced V th degradation, but at different measurement delays. Delays are denoted by short delay and long delay which are of ~ 1 second and ~ 9 second respectively. (c) Time evolution of V th degradation under different stress temperatures (fixed oxide field). The degradation slope (time exponent) is represented by n in respective graphs. Fig. 2 Subthreshold slope degradation for 10μm/0.18 μm pmosfet transistor. (a) Fig. 3(a) and Fig. 3(b) present the V th degradation dependence on the stress voltage and the inverse of stress temperature respectively. For the case of Fig. 3(a), the behaviour of V th can be empirically modelled as below in order to determine whether the device degradation is dependent on the process or on the stress voltage [19], (b) where exponent factor, n ~ Parameter C is extracted from the slope of the graph to determine whether the device degradation is dependent on process (C ~ ) or stress voltage. It is observed from Figure 3(a), that the degradation slopes are much higher than 0.1 which indicates that the device degradation is highly dependent on the stress voltage. The number of free Si bonds broken due to NBTI degradation is a function of temperature and can be expressed by the Arrhenius relationship with the activation energy (E a) presented in Fig. 3(b). From Fig. 3(b), the activation energy, E a is extracted to be 0.20 ev to 0.22 ev for the gate stress bias of -3.4 V, -3.2 V and 208

4 -3.0 V. The extracted activation energy is almost identical for different stress voltage and in the similar range as reported in the literature [12]. The extracted E a show that the same mechanism is responsible for the degradation in V th when different stress voltage and temperature are applied. Fig. 3(b) shows that the V th increases with stress temperature which may result from the temperature dependence of the diffusion coefficient as presented in (2) [20]. This equation suggests that at higher temperature, the drift of hydrogen ions and the electrochemical reaction are enhanced, hence resulting to higher degradation. where D is the effective diffusion coefficient and k B is the Boltzmann constant. pmosfet (W = 10 μm) for a particular stress bias. The 0.22/0.18 μm pmosfet reaches the targeted degradation at shorter times with ~ 50s and ~ 700s of applied stress -3.4V and -3.0V respectively, compared to longer times of ~ 300s and ~ 2000s for the wider 10/0.18 μm pmosfet. The higher NBTI degradation in narrow pmosfet is assumed to due to the edge or stress effects in the shallow trench isolation (STI) structure of the device [21]. The mechanism is very much due to the structure of the STI itself, which induces stress on the device [22]. Fig. 5 shows the comparison of NBTI degradation effects on varying channel lengths of the pmosfet transistor. It was observed that the degradation was slightly more significant in very long channel lengths (L = 10 μm) compared to devices with shorter channel lengths. This can be attributed to the higher contribution of degradation by the fixed oxide charge, N OT in the middle section of the channel area for longer channel length. N IT has stronger influence on carrier mobility near the drain side of the channel, and is the dominant degradation in shorter channel length pmosfet [23,24]. (a) Fig. 4 Comparison of NBTI-induced V th degradation for (W/L) 0.22 μm/0.18 μm with 10 μm/0.18 μm. (b) Fig. 3 (a) V th degradation dependence on the stress bias. (b) V th degradation dependence on the stress temperature B. Comparison of NBTI Degradation with Varying Geometric Properties of p MOSFET Transistor It was observed in Fig. 4 that the narrower pmosfet (W = 0.22 μm) has higher NBTI degradation compared to the wider (a) 209

5 showed that the narrow width (W = 0.22 μm) with the STI stress effect and the very long channel length (L = 10 μm) both induced higher N IT and N OT, as pointed out in section 3.2. The V th lifetime is significantly lower compared to I dsat lifetime (as large as 2 order of magnitude for 10/0.18 μm), indicating the linear mode of operation of pmosfet is highly susceptible to NBTI effects. (b) Fig. 5 Comparison of NBTI-induced (a) I dsat degradation and (b) V th degradation for thin gate oxide pmosfet with varying channel lengths (10/10 μm vs 10/0.18 μm). Fig. 6 compares the NBTI-induced V th for thin gate oxide pmosfet with the thick gate oxide pmosfet. It was observed that the power-law time exponent, n for the thick gate oxide is at the higher end of the range of n for thinner gate oxide, as shown in Figure 1(a). This indicates that the same mechanisms (generation of N IT and N OT) are responsible for the degradation in thick gate oxide pmosfet. However, the thick gate oxide pmosfet shows faster degradation for the same oxide electric field compared to thin gate oxide pmosfet. This can be due to the difference in process condition between thin gate oxide (dry oxidation) and thick gate oxide (wet oxidation). It has been reported that wet oxidation will enhance V th during NBTI stress [25]. Fig. 7 Comparison of Time-to-Fail for thin gate oxide pmosfet with reference to the gate voltage at stress, V g,stress. Each set of lines represents the exponential regression of (W/L) = 10/0.18 μm, 10/10 μm and 0.22/0.18 μm pmosfet respectively. The solid lines represent TTF of I dsat while the dotted lines represent TTF of V th. Fig. 8 compares the TTF plots versus electric field on gate for 10/0.18 μm and 10/0.30 μm pmosfets during stress, E g,stress. This is due to the difference in nominal operating voltage for thin gate oxide (10/0.18 μm) and thick gate oxide (10/0.30 μm). Meaningful comparison on NBTI degradation between this two types of transistors with different oxide thicknesses and processes, can only be done on the basis of equal electric-field across the gate-oxide [27]. The thick gate oxide 10/0.30 μm shows higher I dsat lifetime than V th lifetime, similar to 10/0.18 μm. However, the lifetime for 10/0.30 μm is lower than 10/0.18 μm, due to the faster degradation rate induced by N OT caused by the wet oxidation process for thick gate oxide. Fig. 6 Comparison of V th degradation between thin oxide (3 nm) and thick oxide (5.6 nm) pmosfet, for gate stress bias at 9.5 MV/cm and 10.8 MV/cm. C. DC Lifetime Extrapolation To extract the DC lifetime of NBTI degradation, the Timeto-Fail (TTF) for each stress bias needs to be determined [26]. The TTF is plotted against stress bias and the lifetime was extrapolated to the nominal operating voltage which is -1.98V for the observed pmosfet 10/0.18 μm. Fig.7 and Fig. 8 below presents the NBTI lifetime plots which include exponential regression for the I dsat and V th. The stress temperature for an accelerated condition was set to 125 C. It was observed in Fig. 7 that the 10/0.18 μm transistor has a higher lifetime for both I dsat and V th compared to the other sample transistors. This again Fig. 8 Comparison of Time-to-Fail for thin gate oxide (3 nm) 10/0.18 μm pmosfet to thick gate oxide (5.6 nm) 10/0.30 μm pmosfet with reference to the electric field across the gate oxide during stress, E g,stress. 210

6 IV. CONCLUSION Negative bias temperature instability (NBTI) is an emerging reliability issue in fabrication of semiconductor devices particularly pmosfets. It has been observed that the NBTI degradation is enhanced at higher stress voltage and stress temperatures, demonstrating that the NBTI can be electrically and thermally activated. This work had shown that the power law time dependence with similar n (~1/4) is obtained over a wide range of NBTI stress measured using the quasi-dc measurements. The observed data can be explained with the R- D model of interface states (N IT) generation. Obtained values of n and E a identify the diffusion species as the atomic hydrogen species, H. From the observed data, it was suggested that the generation of interface traps drive the NBTI generation in the samples. It has been observed that the NBTI recovery during measurement delay resulted in lower measured degradation levels which may have been underestimated and a higher power factor, n. Thicker gate oxide pmosfet samples had shown lower NBTI compared to thinner gate oxide pmosfet. NBTI was also observed to be one of the contribution factors to the lifetime of the pmosfet transistors. ACKNOWLEDGMENT The authors acknowledge the tools support from International Islamic University Malaya. The authors also would like to thank to Ministry of Higher Education for the financial support. This research is conducted under the support of Fundamental Research Grant (FRGS: 600-RMI/FRGS 5/3 (31/2015)) and High Impact Research Grant (HIR) of University of Malaya. REFERENCES [1] V. Huard, M. Denais and C. Parthasarathy. (2006), NBTI degradation:from physical mechanism to modelling, Microelectronics Reliability, 46 (2006), [2] Hatta, S.F.W.M., Soin, N., Hadi, D.A., and Zhang, J.F. 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