= (1) E inj. Minority carrier ionization. ln (at p ) Majority carrier ionization. ln (J e ) V, Eox. ~ 5eV

Transcription

1 EE650R: Reliability Physics of Nanoelectronic Devices Lecture 21: Application of Anode hole injection Model to Interpret Experiments Date: Nov ClassNotes: Vijay Rawat Reviewer: Haldun Kufluoglu 21.0 Anode Hole Injection (Review) The anode hole injection model describes a physical process in which electrons injected through the oxide lose there energy at the Si/SiO 2 interface in the anode side through impact ionization, thereby creating electron-hole pairs. A fraction of the electrons tunneling through the oxide are able to transfer their energy to deep valence band electrons. This creates hot holes which tunnel back into the oxide, thereby creating traps inside the oxide layer. Eventually these traps form percolation paths and leads to oxide breakdown. According to the anode hole injection model, the oxide time-to-breakdown can be written as, T N = (1) AJ eαth where N is the no. of traps (which is dependent on the oxide thickness), J e is the electron current, a is the hole generation (or impact ionization rate) and T h is the hole tunneling probability. The injected electron current is directly proportional to the applied voltage and the dependence is shown in Figure 1. Similarly, the hole tunneling efficiency (at p ) depends on the energy of the injected electrons and the dependence is shown in Figure 1. Electric field versus applied voltage. While determining the oxide time-to-breakdown using the AHI model, two different cases should be considered, a) high electric field regime and b) low electric field regimes. ln (J e ) ln (at p ) Minority carrier ionization Majority carrier ionization V, Eox ~ 5eV E inj Figure 1 : The dependence of the electron injection current on the applied gate bias and the electric field across the dielectric and the hole tunneling efficiency on the energy of injected electrons.

2 For the high field case, the tunneling current (J e )is given by the F-N formula and is dictated by the electric field within the oxide (E ox ), i.e. J e ~ A 1 exp(-b 1 /E ox ). The region where ionization is taking place is not affected by the oxide electric field and is purely dependent on the applied gate voltage (V G ); hence, both the impact ionization rate and the hole tunneling probability (T p ) are dependent on gate voltage. However, at high voltage, α~α 0 =1-2 and T P ~ A 2 exp(-b 2 /E ox ) where B 2 is determined by the average barrier height seen by hot holes tunneling across the oxide. Thus, the oxide time-to-breakdown expression can be written as, N T = B1 B (2) 2 Eox Eox Ae 1 α0ae 2 Thus, for the high field case, 1 ln( T ) E On the other hand, in the low electric field regime, the electron tunnel current (J e ) is determined by direct tunneling through the oxide and is determined by applied voltage (i.e. J e ~f(v G )). And the hole tunnel efficiency is at p ~ exp(ßv) (see Fig. 1b). Therefore, Eq. (1) becomes T N BVG f ( VG ) e g( VG ) = (3) As a result, ln(t ) is directly proportional to applied voltage in this regime. ln(t ) V E In short, at high voltages tunneling probability is inversely proportional the gate field but at low voltages it varies non-linearly with the applied gate voltage (Figure 2). As a result, the predicted lifetime can be very high for low gate voltages as shown in figure 2. Experimental data Corrected lifetime ln (at p ) ln (T ) Extrapolated lifetime V G V G Figure 2 : The dependence of the hole tunneling efficiency (at p ) on the gate voltage and the time-to-breakdown on the gate voltage.

3 21.1 Interpreting experimental data for AHI According to the anode hole injection model, the determination of oxide time-to-breakdown depends on multiple factors such as the oxide thickness and polarity of the oxide barrier. In this section some of these factors that affect T are discussed Thickness dependence of T It has been observed in T measurements that when same electric field is applied across oxide of two different thicknesses, sometimes a thinner oxide has longer time-to-breakdown than a thicker oxide. This nonintuitive result can be understood from the Figure 3 below which shows two PMOSFETs with different oxide thicknesses. If the electric field is same across the two oxide layers, then the voltage has to be lower for the thinner oxide. In the F-N regime, however, J e1 ~ J e2 a 1 << a 2 T p1 < T p2 Figure 3 : Schematic showing the band diagram for a thin and a thick gate oxide MOSFET with equal electric field applied across the oxide. ln (T ) Thin oxide layer Thick oxide layer E OX Figure 4 : Comparison of time-to-breakdown for a thick oxide and thin oxide MOSFET with equal electric field applied across the oxide layer.

4 the tunneling is taking place through the triangular region, hence, the injected electron current (J e ) is dependent only on the electric field in the oxide layer and will be comparable for two different thickness cases. The impact ionization rate is directly proportional to applied voltage and hence will be higher for thicker oxide. This implies that more hot holes are being generated in case of thicker oxide. This will lead to a higher hole tunneling probability (T p ) in case of the thicker oxide. Now T is inversely proportional to the impact ionization and the hole tunneling probability and hence, will be smaller for the thicker oxide as shown in Figure 4. The situation is different if instead of applying same electric field, same voltage is applied across the oxide. In that case, the electric field will be higher in the thinner dielectric sample as compared to the thicker sample which will increase the injection current of electrons from the cathode (i.e. J e1 >>J e2 ). The impact ionization rate and the hot hole tunneling probability is similar for both thicknesses, (i.e. a 1 ~ a 2, and T p1 ~ T p2 ) due to equal gate voltages. Thus, the thicker oxide layer will have greater time-to-breakdown Polarity dependence of T The gate dielectric breakdown is found to depend on the polarity of applied gate bias too. Figure 5 below shows two different PMOSFETs, first one with a negative gate bias and the second one with a positive gate bias. In case of positive gate bias the effective barrier height for the injecting carrier is smaller than that for the negative gate bias case. As a result, the injecting current is higher in case of positive bias (i.e. J 2 > J 1 ) due to difference in barrier-height. Now, due to the minority ionization occurs in both anodes, but in case of positively biased gate, the injected electrons have higher energy to impart to the electrons in anode, as a result the ionization probability is higher (i.e. a 2 > a 1 ). The tunneling probability of anode hole is slightly higher for the positively gate bias case, again due to the higher energy of the created hole. Due to these reasons the time-to-breakdown, T, is much shorter for the positive bias case (see Fig. 6). 3eV J 2 3eV 1.1eV J 1 Figure 5 : Comparison of time-to-breakdown for PMOSFETs with a) negative gate bias and b) positive gate bias.

5 Figure 6 : Schematic plot showing the dependence of time-to-breakdown, T, on the polarity of applied gate bias. ln (T ) Negative Gate bias Positive Gate bias Effect of back-gate bias E OX The application of back gate can influence the oxide time-to-breakdown. Figure 7 below shows a PMOS band diagram, superimposed with the schematic showing anode hole injection process, for the case a) when no back gate bias is applied (blue lines) and b) when a positive back gate bias (red lines). As it can be seen from the figure that larger the applied positive back-gate bias, the more is the acceleration of the injected electrons and as a result they generate hotter holes. This results in higher ionization of carriers in anode and a higher tunneling probability (T p ), and hence the oxide lifetime is reduced as shown in Figure7. ln (T ) V B Figure 7 : Schematic plot showing the effect of a positive back-gate bias on hot hole generation and tunneling in a PMOS, and the dependence of T on the back gate voltage T difference between NMOS and PMOS

6 The NMOS and PMOS show different oxide breakdown lifetime due to the availability of minority carrier in PMOS which are unavailable in NMOS (Figure 8). If the energy of the injected electron from the cathode is E in, then the maximum energy of the hot hole generated in the anode due to the majority ionization is going to be E in - E g,si, where E g,si is the silicon band gap (~1.1 ev). This is true for the case of high gate voltage but the ionization process changes when the applied gate voltage is low. In case of high gate voltage, the incident energy of the electrons, E in, is much larger than the band gap and hence, the hole generation is primarily due to the majority carriers ionization. Therefore, both PMOS and NMOS have comparable impact ionization rates (i.e. a 1 ~ a 2 ) and hole tunneling probabilites (i.e. T p1 ~ T p2 ) but the injected electron current is higher in case of NMOS (J e1 >>J e2 ). Overall, therefore, NMOS has shorter lifetime than PMOS. For the low voltage case, if the minority carriers are available then the minority carrier ionization can contribute significantly to the total hole tunneling current. In the case of PMOS, due to presence of minority carriers at the anode/oxide interface, additional hole are generated PMOS Minority carriers available NMOS Figure 8 : Schematic plot showing the dependence of time-to-breakdown, T, on the presence of minority carriers. ln (T ) PMOS NMOS V G Figure 9 : Schematic plot showing the dependence of oxide time-to-breakdown, T on the gate voltage for an NMOSFET (dashed) and a PMOSFET.

7 due to two minority carrier ionization mechanisms discussed in the previous lecture. NMOS does not have free minority carriers. As a result, PMOS has higher impact ionization and hole tunneling probability (a 1 >> a 2, T p1 >> T p2 ) than the NMOS. Though the injected electron current is lower in case of PMOS (J e1 < J e2 ), the combined effect of higher hole ionization and tunneling probabilities ensures that the oxide breakdown time is shorter in case of PMOS. Figure 9 shows a plot comparing the NMOS and PMOS oxide breakdown time as a function of gate voltage. This different in oxide breakdown behavior in NMOS and PMOS was experimentally proved in Prior to that, the T values for PMOS and NMOS were only measured at high gate voltages and the measurements were extrapolated for lower gate voltages, which showed incorrect behavior. Figure 10 shows the extrapolated predictions at lower gate voltages for both NMOS and PMOS and the corrected plots. After making the corrections in the lifetime, it can be seen that NMOS is reliable for all the oxide thicknesses mentioned in the silicon roadmap, but PMOS is not. V DD Si technology roadmap requirement V DD Corrected V safe curve Si technology roadmap requirement V safe Pre prediction V safe t ox t ox NMOS PMOS Figure 10 : The comparison of the corrected oxide time-to-breakdown of NMOS and PMOS with the requirement specified by the silicon technology roadmap Conclusion The PMOS reliability poses a serious challenge to continued gate oxide scaling. With classical definition of gate oxide breakdown (i.e. completion of the 1 st percolation path destroys the oxide), nothing much can be done. However, at lower operating voltages, the energy dissipation through the percolation path is so small that destructive (hard) breakdown is unlikely and the device might continue even after formation of first percolation path. This type of breakdown is called soft breakdown. We will establish the conditions of Hard vs. soft breakdown in Lecture 22 and proceed to explore the implications of soft breakdown in Lecture 23.