TRANSITION metal and rare earth oxides are among the

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1 138 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 7, NO. 1, MARCH 2007 Mechanism of Electron Trapping and Characteristics oftrapsinhfo 2 Gate Stacks Gennadi Bersuker, J. H. Sim, Chang Seo Park, Chadwin D. Young, Suvid V. Nadkarni, Rino Choi, and Byoung Hun Lee Abstract Electron trapping in high-κ gate dielectrics under constant voltage stress is investigated. It is suggested that the electron trapping occurs through a two-step process: resonant tunneling of the injected electron into the preexisting defects (fast trapping) and thermally activated migration of trapped electrons to unoccupied traps (slow trapping). Characteristics of the electron traps extracted based on the proposed model are in good agreement with the calculated properties of the negatively charged oxygen vacancies. The model successfully describes lowtemperature threshold voltage instability in NMOS transistors with HfO 2 /TiN gate stacks. Index Terms Electron trapping, high-κ dielectrics, threshold voltage instability. I. INTRODUCTION TRANSITION metal and rare earth oxides are among the high dielectric constant (high-κ) materials currently being investigated as gate dielectrics in highly scaled transistors. A common electronic feature of these materials is the presence of d-shell states, which make their structural properties drastically different from those of the conventional SiO 2 gate dielectric [1]. One of the consequences of the d-electron bonding in high-κ dielectrics is a relatively high density of as-grown defects, which may function as electron traps and fixed charges. Since electron trapping/detrapping at preexisting structural defects may dominate threshold voltage (V t ) instability [2] [5] at low stress voltages, understanding these processes represents a necessary first step in assessing stress-induced trap generation and bias-temperature instability in high-κ devices [6]. In this paper, we discuss a model for electron-trapping phenomena and apply this model to describe positive bias low-temperature V t instability in NMOS transistors with HfO 2 /TiN gate stacks. The model suggests that electron trapping is caused by contributions from two different processes: fast transient resonant trapping of the injected channel electrons at the defect sites and electron hopping between the traps, which is responsible for the longstress V t shift. Analysis of each of these electron-trapping processes, which can be adiabatically separated based on their different characteristic times, provides insight into the nature of defects responsible for V t instability. Manuscript received September 15, 2006; revised January 31, G. Bersuker, J. H. Sim, C. S. Park, C. D. Young, R. Choi, and B. H. Lee are with SEMATECH, Austin, TX USA ( gennadi.bersuker@ sematech.org). S. V. Nadkarni is with the University of Texas, Austin, TX USA. Color versions of one or more of the figures in this paper are available online at Digital Object Identifier /TDMR II. SAMPLE PREPARATION AND ELECTRICAL TEST DATA NMOS transistors were fabricated with HfO 2 films of 2-, 3-, and 4-nm physical thicknesses, which are deposited by atomic layer deposition on O 3 -treated (001) epi Si substrates and densified by a N 2 anneal. A gate electrode was formed by a 10-nm TiN film, capped with an N-doped poly-si layer. The employed standard CMOS fabrication process included a C/10-s dopant activation anneal and 485- C forming gas anneal. Transistors of 1-µm long and 10-µm wide were subjected to a constant voltage stress (CVS) under the substrate injection condition at different gate biases (V g = V) inatemperature range of K. The stress was interrupted for drain current-gate voltage (I d V g ) measurements to monitor variations in linear V t and transconductance (G m ) values. To avoid a distortion of the V t (t) dependence caused by the V t relaxation during stress interruptions, the stress periods between the I d V g measurements were kept constant: under this condition, charge detrapping may affect an absolute value of the measured V t rather than the shape of the V t (t) curve [7], which is of interest for the analysis of the trapping mechanism. In agreement with earlier reports, the electron trapping at low stress voltages relevant to circuit operation conditions is found to be reversible: by applying a voltage of the opposite polarity, V t can be returned to its initial prestress value (Fig. 1). The kinetics of detrapping are similar to trapping [3], [4], [6], [8], while the actual V t value after detrapping is defined by the detrapping voltage. The V t dependence on stress time does not change with each subsequent stress cycle, and there is no noticeable degradation of the interface electrical properties (i.e., transconductance and subthreshold slopes do not change). Therefore, one may conclude that electron trapping occurs on preexisting (as-grown) defects, and a low-voltage electrical stress of practical importance does not lead to any significant generation of new traps in the high-κ layer. This reversible behavior may be expected when the trapped electron resides mostly on the d-orbitals, which are delocalized over the metal ion and its nearest neighbors. In this case, no significant chemical bond weakening and, hence, permanent structural damage caused by the electron trapping should be expected. In this paper, we focus on data for the 3-nm HfO 2 gate stack as relevant for aggressively scaled equivalent oxide thickness applications while still showing electron trapping sufficient for reliable modeling of the electron-trapping process. An example of changes in the I d V g curves before and after the 2000-s CVS at different stress temperatures is shown in Fig. 2 for /$ IEEE

2 BERSUKER et al.: MECHANISM OF ELECTRON TRAPPING AND CHARACTERISTICS OF TRAPS 139 Fig. 3. Example of the I d V g curve shift during CVS V g = 2.1 V at 298 K. A portion of the curve is magnified. Fig. 1. (a) Threshold voltage change in a TiN/3 nm HfO 2 /1 nm SiO 2 NMOS transistor during stress cycles, which include 1000-s substrate injection stress at V g = 2.4 V, followed by 10-s stress at the opposite bias ( 1 V). (b) I d V g transistor characteristics during the V g pulse having the width of 100 µs and rise/fall time of 5 µs. Fig. 4. Change of V t values during V g = 2.1 stress in the temperature range of 298 K 77 K. Fig. 5. Change of transconductance values (%) during V g = 2.1-V stress and V g = 1.8-V stress at various temperatures. Fig. 2. I d V g characteristics before (BS) and after (AF) 2.1-V/2000-s stress at different temperatures. the V g = 2.1 V stress case. An example of variations in I d V g dependence during the stress is presented in Fig. 3. A summary of V t and G m variations is presented in Figs. 4 and 5, respectively. Threshold voltage changes in the 2-nm HfO 2 stack and a comparison of 3- and 2-nm stacks are shown in Fig. 6. As can be seen in Fig. 1, an initial fast increase of V t during the first second of CVS is followed by slower V t growth. To investigate the initial fast electron trapping, we employed a pulsed I d V g technique [2]. Pulsed I d V g measurements were Fig. 6. (a) V t change in the 2-nm HfO 2 gate stack transistors during V g = 1.8-V stress. (b) V t change after V g = 1.8-V/2000-s stress at different temperatures in the transistors with 2- and 3-nm HfO 2 gate stacks.

3 140 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 7, NO. 1, MARCH 2007 performed on the 1 10-µm transistors, where the MOSFET was embedded in an inverter circuit with a load resistor (R L ) configuration. A trapezoidal pulse shape was applied to the gate, and the voltage was sensed at the drain terminal and converted to I d since R L was a known value of 300 Ω [9]. For the pulse measurements used in the analysis below, the rise and fall times were equal to 100 ns with a fixed pulsewidth of 100 µs. The gate voltage pulse ranged from 1.65 to 1.95 V. In the pulse measurements, the drain current decrease I d is attributed [2] to the effective increase in the device threshold voltage V t due to the charge Q trapped in the dielectric during the gate voltage pulse, V t = Q/C (the trapped charge location with respect to the electrode defines the capacitance C): I d =(W/L)C 0 µ V t. Here, W and L are the transistor width and length, respectively, C 0 is the gate capacitance, and µ is the carrier mobility (as discussed in [10], moderate electron trapping in the high-κ film does not degrade intrinsic mobility but rather changes the surface effective electric field and, hence, inversion charge in the channel). Based on the above expression, the measured I d values can be used to calculate the parameter V t, which can be considered a figure of merit for the fast transient charging effect V t =( I d /I d )(V g V t ). (1) A precise expression for V t, which takes into account variation of the mobility value with changing threshold voltage, is given in [10]. III. MODEL OF CHARGING PROCESSES The preexisting traps can be filed via several processes, as illustrated in Fig. 7(a): direct tunneling of the carriers from the conduction band [process P c in Fig. 7(a)] and the interface traps (process P int ) to the traps in the high-κ dielectric, as well as temperature-activated electron transport between the traps (process P T ). As will be discuss below, an important characteristic of the high-κ traps contributing to charge trapping is that they are relatively shallow with energies in the range of < 0.6 ev from the bottom of the conduction band, depending on the charge states. Therefore, the process P c, which represents the major component of the gate current, can contribute to the electron trapping primarily in the traps, in which energy is in a quasi-resonance with the Fermi level in Si. The probability of trapping the electron from the conduction band [process P in Fig. 7(a)] by a shallow trap quickly reduces with the distance from the injection point as the electron accelerates in the conduction band by the applied electric field, and its energy becomes comparable to the trap energy. The P c process is expected to exhibit shorter characteristic time with respect to the process P int due to the smaller tunneling barrier and higher density of states in the Si conduction band. Here, we focus on the effect of trapping caused by the injection of the conduction band electrons (P c, fast component) and temperaturedependent electron transport (P T, slower component, as will be demonstrated below); the contribution from the P int process, which is only weakly temperature dependent (due to variation of the occupancy of the interface traps), increases with stress Fig. 7. (a) Schematic of the energy band diagram with the proposed electrontrapping processes: P c electrons injection from the conduction band and trapping at a shallow defect [presumably neutral O-vacancy (V 0 )], which leads to the formation of a negative O-vacancy accompanied by the lattice relaxation (down arrow); P T a temperature-assisted electron detrapping/retrapping; P int electron injection from the interface traps. Capture of the electrons accelerated in the conduction band (P ) is ineffective. (b) Schematic of the gate stack (top view) with the primarily (P c) and secondary (P T ) electrontrapping processes. time and might be appreciable with respect to the P T contribution at low temperatures when the temperature-activated electron hopping is suppressed. Neglecting the P int process allows obtaining a simple analytical description for the threshold voltage instability within short stress times, which would be sufficient for extraction of the electron trap characteristics. However, the device lifetime evaluation requires comprehensive analysis of all the aforementioned components, and it will be discussed elsewhere. Since the initial ( 1 s) increase of V t during CVS (see, for example, Fig. 1) is found to be comparable to the V t measured by the pulsed I d V g method in the microsecond range, while

4 BERSUKER et al.: MECHANISM OF ELECTRON TRAPPING AND CHARACTERISTICS OF TRAPS 141 the subsequent V t increase occurs within several seconds of the stress time, we suggest that two trapping processes with very different characteristic times contribute to the observed stress-induced V t shift. By applying pulses of various durations, it was demonstrated that, indeed, the characteristic time of the fast-charging process P c is in the range of microseconds, while the temperature dependent charge transport process P T starts to contribute after about few seconds of stress [11]. The fast P c process is, thus, suggested to be responsible for the significant V t increase at the initial moment of the dc stress [Fig. 1(a)]. Such a significant difference in the time scale, s versus s, allows the fast and slow processes to be separated within the adiabatic approximation, and time dependence of the slow process to be studied under the assumption that the population of the traps filled by the fast charging remains constant during stress. Fig. 8. Change of the drain current (in microampere) during the pulsewidth time (in microsecond) at the pulse voltages V g = 1.65 V and V g = 1.80 V measured at different temperatures. A. Fast Charging To study fast transient charging, we adopted a simplified model where trapping of each electron is independent of the others and does not affect the injection current density. The injected electrons are transported to the traps by a tunneling process and can be trapped at defects whose energies are in quasi-resonance with the electron energy [Fig. 7(a)]. Under these assumptions, the kinetics of fast transient electron trapping can be described by the following equation: n t = p(n 0 n). (2) Here, n is the density of the filled traps, N 0 is the available total trap density, and p is the probability of a single electrontrapping event: p σj/q, where σ is the defect capture cross section and J is the injection current density. To reduce the number of fitting parameters and taking into consideration the low-temperature test conditions, we neglected a detrapping process that is not expected to affect an order of magnitude estimate of the p value. The solution of this equation n = N 0 (1 e pt ) (3) describes the time dependence of V t, V t = qnx, which is caused by an accumulation of trapped electrons (q) in the dielectric in the traps at distance x (from the electrode) defined by the band bending under the given gate bias condition V g [see Fig. 7(a)]. This trapping process defines the time dependence of the drain current, I d V t [see (1)]. By fitting (3) to the measured time dependence of the drain current during the pulse (Fig. 8), one can estimate the characteristic trapping probability p and, subsequently, σ. An example of fitting is presented in Fig. 9, where the fitting was restricted to the drain current change during the initial 12 µs of the pulsewidth time in Fig. 8, which is much shorter than the time required for the drain current to reach a quasi-saturation. This means that most of the available traps are not yet occupied, and therefore, the above discussed limitation of (2) requiring a low density of the Fig. 9. Experimental (symbols) and modeled (lines) reduction of the drain current during the initial portion of the pulse in Fig. 8. trapped charges (so that the electron electron interaction can be neglected) is satisfied. For all temperatures and pulse bias conditions, it was found that σ cm 2, which is consistent with the earlier estimates [12]. The estimated trap density N 0 is on the order of cm 2, which is much higher than the final trapped charge density. The final density is lower due to Coulomb repulsion between the trapped charges, which prevents trapping at the majority of the available defect sites. The data in Fig. 8 show that the fast electron trapping significantly decreases at the lowest used temperature (77 K), suggesting that the trapping is assisted by low-frequency phonons, which may be suppressed at this temperature (see discussion below). B. Slow Charging A similar analysis [see (3)] of the slow-charging process, which exhibits six orders of magnitude of higher characteristic electron-trapping time, of about 10 2 s, yields the value of the effective capture cross section σ cm 2 if one assumes that the electrons available for trapping were supplied by the same gate current of the density J [process P in Fig. 7(a)]. Such a significant difference in the σ values of the slow- and fast-charging processes could suggest that the former process is assisted by a different type of defect. However,

5 142 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 7, NO. 1, MARCH 2007 the above σ values are too small to represent any meaningful physical defect, indicating that the electron capture from the dielectric conduction band is apparently ineffective, as will be discussed below. This suggests that the traps are rather shallow (see [6] and [12]) and, therefore, cannot hold an injected electron if it has gained kinetic energy from acceleration in the conduction band. This is consistent with the observation that the CVS trapping increases with temperature, while the capture from the conduction band is expected to decrease with temperature due to more effective temperature-activated detrapping. The slow traps were demonstrated [3], [11] to detrap as effectively as the fast traps under the same applied detrapping (negative) gate bias. That is, the slow and fast traps exhibit similar detrapping kinetics, indicating that both types of traps may have similar physical characteristics (e.g., energies, electronic structures, etc.). These considerations suggest that different electron-trapping mechanisms rather than different kinds of traps may be responsible for the fast- and slowcharging processes. We propose and investigate a model that is based on the assumption that the same traps contribute to both fast and slow electron trapping. According to the model, the observed slow charging may reflect the capture of secondary electrons the electrons supplied by the traps, charged by the fast direct tunneling process [Fig. 7(b)]. A large trap dimension, on the order of 1 nm, as estimated above, suggests that they may be located close to each other. Therefore, a certain number of electrons activated by temperature from the traps into the conduction band can be recaptured by the nearby available traps before they gain kinetic energy and, thus, become ineligible for retrapping. The large size of the traps allows the trapped electrons to migrate along the conduction band by hopping via the (trap-conduction bandtrap) process, without gaining kinetic energy since the trapped electrons are not subject to electric field acceleration [Fig. 7(a)]. Due to a significant difference in the characteristic charging times of fast (microsecond) and slow (second) trapping, the traps accessible by the fast tunneling process are instantly refilled after their detrapping, which would provide a constant supply of secondary electrons to sustain the slow-charging process. Within the above model, kinetics of the slow-charging process are described by (2) where, however, in the trapping probability p σj/q, the flux J/q is determined by the electrons emitted from the traps via thermally activated excitation [see Fig. 7(b)] J s (i) =n 1 τ exp( E i/kt ) (4) where n is the density of the filled fast traps, τ is the detrapping time constant, and E i is the effective trap energy. In (4), we adopted the Boltzmann temperature dependence for the temperature-activated electron detrapping process and left open the possibility that there may be more than one type of electron traps and, hence, values for the activation energy E i. In the firstorder approximation, we neglected the processes of electron migration between the secondary traps. These processes may become effective at longer stress times (contributions from these processes will be discussed elsewhere). The time dependence of the slow-trapping process then takes the form of (3) N = N s i ( 1 e p s(i)t ) (5) where N s is now the density of the available secondary traps located near the filled traps (these traps, as discussed above, can contribute to recapturing the emitted electrons), and p s (i) σ s J s (i), where σ s is the capture cross section for the electrons in the conduction band, and J s is given by (4). To simplify the fitting procedure, we assume that all secondary traps are located at approximately the same electrical distance l from the electrode. This approximation is based on the fact that the probability of electron retrapping strongly decreases with increasing distance between the primary traps that emit electrons and the capturing traps (this dependence is reflected in the reduction of the effective electron capture cross section σ s with an increase in electron kinetic energy, which is proportional to the intertrap distance). Therefore, secondary traps contributing to the slow-charging process may be located within only a few angstroms of the primary traps and, hence, variation of their positions with respect to the electrode is expected to be on the same order of a few angstroms. Due to the high value of the dielectric constant κ, this variation in the physical positions of the traps would translate into a negligible difference in the corresponding electrical position l of the trapped electrons. This approximation allows for a simple conversion of the threshold voltage shift values V t to the trapped charges Q = V t /l and to the trap density N = Q/q. To further justify the validity of this approximation, we restricted the range of experimental data used in the fitting to within the first 1000 s of stress time. This also helps to mitigate the model limitation due to neglecting the contribution from the slowtrapping process associated with the electron tunneling out of the interface traps [the process P int in Fig. 7(a)]. As recently demonstrated [11], the V t values extracted by dc measurements are subject to fast relaxation (in the time range of s) during the stress interruption time required to perform sense measurements. This relaxation is dominated by detrapping of the charges, which were trapped via the fastcharging process [the process P c in Fig. 7(a)]. Subtracting V t values associated with the fast charging was shown to eliminate the dominant source of V t relaxation. Therefore, it is critically important for modeling of the slow process to separate its contribution to V t from that of the fast process. Fitting the V t, values (after subtracting the fast-traping component of V t ) for different stress voltages using (5) are shown in Fig. 10. To minimize the contribution of the interfacial layer degradation to V t,, which is indicated by G m degradation, the fitting was done on the data obtained with the lower bias stresses, V g < 2 V. The fitting was performed in an iterative way starting with a single term in the sum in (5) and increasing the number of terms until a satisfactory fit was obtained. The fitting for all voltages in the whole temperature range required three terms in (5), suggesting that more than one type of traps contributes to the slow charge trapping. At the

6 BERSUKER et al.: MECHANISM OF ELECTRON TRAPPING AND CHARACTERISTICS OF TRAPS 143 Fig. 11. Activation energies E i corresponding to p i values extracted from V g = 1.8- and 1.95-V stress data in Fig. 10. Fig. 10. Experiment and modeled (open symbols) V t shift during the V g = and 1.80-V stresses at different temperatures. lowest temperature T = 77 K, the time dependence of V t is controlled by a process with a single activation energy (hereafter denoted by the index 3 ) characterized by a high trapping probability p 3 and weak temperature dependence. At higher temperatures, the fitting required three terms in (5), i = 1, 2, 3. The fitting procedure was repeated for each of the stress temperatures generating the values of the fitting parameters: p i (T ) and N s (Fig. 10). The slope of the dependence [ln(p i ) versus 1/kT ] yields the value of the detrapping energy barriers E i for the electron contributing to the charge flux J s (i)(i = 1, 2, 3) in (4): E 1 = ev for V g = 1.95 V, and E 2 = ev for V g = 1.60 V (Fig. 11). These energy values are in good agreement with our previous rough estimates based on the temperature dependence of electron detrapping, E = ev [12]. With the Poole-Frenkel correction for the electric-field-induced barrier-lowing effect, E i = E 0 + βe el, where β is the Poole-Frenkel coefficient of about 0.15 ev in this case, the trap energies are on the order of 0.35 and 0.45 ev, close to the reported value of 0.35 ev obtained from detrapping measurements [13]. The electron migration process of type 3 exhibits a very low activation energy, E 3 < 0.01 ev, which may correspond to the motion of the electrons in the conduction band hindered by the defects (a polaron-type motion). The N s value, which corresponds to the density of the available traps appropriately located to recapture secondary electrons, is on the order of cm 2, suggesting that most of the electrons activated from the primary traps are not recaptured. This explains the high characteristic time constant, on the order of 10 2 s, of the electron-trapping process during CVS. A possible candidate for the electron-trapping defect is a very shallow neutral oxygen vacancy, which, according to the calculation of the monoclinic HfO 2 structure [14], creates small displacements of the surrounding Hf atoms and can trap an injected electron before it gains kinetic energy, thereby forming a negative O vacancy (V ). The frequency of the Hf atoms displacement associated with the electron trapping is in the range of ev [15], which explains significant reduction of the fast electron trapping observed at 77 K ev (Fig. 8) when these vibrations are, to a great degree, frozen out. V can trap a second electron resulting in the V 2 defect of a slightly, by about 0.1 ev, lower energy due to the electron repulsion. Recently, the obtained results estimate the thermal activation energies of V and V 2 oxygen vacancies of 0.5 ev and 0.3 ev, respectively [16], which are in good agreement with our results. We would like to note that the widely reported oneelectron energies of oxygen vacancies may not be directly applicable to the studied thermally activated electron transitions, which involve significant lattice relaxation [16], [17]; modeling of the measurements involving temperature-activated processes requires using thermal activation energies. Electrons trapped at the O defects were calculated to be delocalized over a wide area, greater than 1 nm in diameter, which is consistent with the above electrical estimates for the defect dimension. The above estimated trap density, N cm 2, corresponds to about one half of the oxygen atomic percent. One of the consequences of a large size of the oxygen defects is the reduction of electron trapping in devices with thinner gate dielectrics [Fig. 12(a)]. The ability of high-κ dielectric film to capture injected electrons is expected to diminish when the film thickness becomes comparable to the effective size of the trap, since the barrier separating the trapped electron from the gate electrode becomes too thin (or completely disappears) [Fig. 12(b)]. Thus, in thinner films, more traps become unable to localize the captured electrons, which may leak from the traps to the gate electrode. IV. SUMMARY The proposed model suggests that the migration of electrons captured during fast charging to other available traps represents the major electron-trapping process controlling the

7 144 IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY, VOL. 7, NO. 1, MARCH 2007 Fig. 12. (a) Changes of the drain current during the gate pulse of 100-µs width and 5-µs rise/fall time in transistors with the 18-, 25-, and 32-Å HfO 2 gate dielectrics. (b) Schematic of the high-κ gate stack energy band diagram illustrating reduction of the electron trapping in thinner dielectric films. time-dependent threshold voltage change during CVS. This model provides a foundation for investigation of positive bias temperature instability (PBTI) phenomenon in high-κ gate stacks. Characteristics of the electrically active defects extracted by applying this model to the CVS data are consistent with the oxygen vacancies in the monoclinic hafnia. The obtained results on the defect properties suggest that aggressive scaling of the physical thickness of high-κ dielectric film may provide trapfree electrical characteristics even in the crystalized dielectric. REFERENCES [1] G. Bersuker, B. H. Lee, and H. R. Huff, Novel dielectric materials for future transistor generations, Int. J. High Speed Electron. Syst., vol. 16, no. 1, pp , Mar [2] A. Kerber, E. Cartier, L. Pantisano, M. Rosmeulen, R. Degraeve, T. Kauerauf, G. Groeseneken, H. E. Maes, and U. Schwalke, Characterization of the V t instability in SiO 2 /HfO 2 gate dielectrics, in Proc. 41st IEEE Int. Reliab. Phys. Symp., 2003, pp [3] J. H. Sim, R. Choi, Y. H. Lee, C. Young, P. Zeitzoff, D. L. Kwong, and G. Bersuker, Trapping/de-trapping gate bias dependence of Hf-silicate dielectrics with poly and TiN gate electrode, Jpn. J. Appl. Phys., vol. 44, no. 4B, pp , [4] S. Zafar, A. Kumar, E. Gusev, and E. Cartier, Threshold voltage instabilities in high-κ gate dielectric stacks, IEEE Trans. Device Mater. Rel., vol. 5, no. 1, pp , Mar [5] C. Leroux, J. Mitard, G. Ghibaudo, X. Garros, G. Reimbold, B. Guillaumor, and F. Martin, Characterization and modeling of hysteresis phenomena in high-κ dielectrics, in IEDM Tech. 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Young, Mobility evaluation in transistors with charge trapping gate dielectrics, Appl. Phys. Lett., vol. 87, no. 4, p , Jul [11] D. Heh, R. Choi, C. D. Young, and G. Bersuker, Fast and slow charge trapping/detrapping processes in high-κ nmosfets, in Proc. IEEE IRW Final Report, 2006, pp [12] G. Bersuker, J. H. Sim, C. D. Young, R. Choi, P. M. Zeitzoff, G. A. Brown, B. H. Lee, and R. W. Murto, Effect of pre-existing defects on reliability assessment of high-κ gate dielectrics, Microelectron. Reliab., vol. 44, no. 9 11, pp , Sep. Nov [13] G. Ribes, M. Muller, S. Bruyere, D. Roy, M. Denais, V. Huard, T. Skotnicki, and G. Ghibaudo, Characterization of V t instability in hafnium based dielectrics by pulse gate voltage techniques, in Proc. Eur. Solid-State Device Res. Conf., 2004, pp [14] G. Bersuker, B. H. Lee, H. R. Huff, J. Gavartin, and A. Shluger, Mechanism of charge trapping reduction in scaled high-κ gate stacks, in Defects in High-κ Materials, E. Gusev, Ed. New York: Springer-Verlag, 2006, p [15] J. Gavartin and A. Shluger, Ab initio modeling of electron-phonon coupling in high-κ dielectrics, Phys. Stat. Sol. C, vol. 3, no. 10, [16] J. Gavartin, D. Munoz Ramo, A. Shluger, B. H. Lee, and G. Bersuker, Negative oxygen vacancies in HfO 2 as charge traps in high-κ gate stack, Appl. Phys. Lett., vol. 89, no. 8, p , Aug [17] J. Gavartin, D. Munoz Ramo, A. Shluger, and G. Bersuker, Polaronlike charge trapping in oxygen deficient and disordered hfo 2 : Theoretical insight, ECS Trans., vol. 3, no. 3, pp , Gennadi Bersuker received the M.S. degree from Leningrad State University, St. Petersburg, Russia, and the Ph.D. degree in physics from Kishinev State University, Chisinau, Moldova. After graduation, he joined Moldavian Academy of Sciences, Chisinau, and then joined Leiden University, Leiden, The Netherlands, and the University of Texas, Austin. Since 1994, he has been with SEMATECH, Austin, working on processinduced charging damage, electrical characterization of Cu/low-κ interconnect, high-κ gate dielectrics, and advanced CMOS process development. J. H. Sim, photograph and biography not available at the time of publication. Chang Seo Park received the B.S. degree in ceramic engineering from Yonsei University, Seoul, Korea, in 1991 and the Ph.D. degree in electrical engineering from the National University of Singapore, Singapore, in In 1993, he joined Hynix Semiconductor (formerly Hyundai Electronics) and then, in 1999, joined Tower Semiconductor. Since 2005, he has been with SEMATECH, Austin, TX, working on process development and integration of metal/high-κ gate stack.

8 BERSUKER et al.: MECHANISM OF ELECTRON TRAPPING AND CHARACTERISTICS OF TRAPS 145 Chadwin D. Young received the B.S. degree in electrical engineering from the University of Texas, Austin, in 1996, and the M.S. and Ph.D. degrees from the North Carolina State University, Raleigh, in 1998 and 2004, respectively. His dissertation research is on high-κ gate stacks. He has held several internships during this time until 2001 when he joined SEMATECH, Austin, TX. He now continues his research on high-κ gate stacks at SEMATECH as a Project Engineer working on electrical characterization and reliability methodologies for the evaluation of high-κ gate stacks. He has authored or coauthored more than 100 journal and conference papers. Dr. Young is currently serving on the management committee of the 2007 International Integrated Reliability Workshop as the Finance Chair, and as a Guest Editor for the IEEE TRANSACTIONS ON DEVICE AND MATERIALS RELIABILITY. Suvid V. Nadkarni received the B.E. degree in electronics and telecommunications engineering from the University of Pune, Pune, India, in 2002 and the M.S. degree in electrical engineering from the University of Texas, Austin, in He is currently working toward the Ph.D. degree in the area of organic microelectronics at the University of Texas. Rino Choi received the B.S. and M.S. degrees from Seoul National University, Seoul, Korea, in 1992 and 1994, respectively, and the Ph.D. degree in materials science and engineering program from the University of Texas, Austin, in From 1994 to 1999, he was with Daewoo Motors Company, where he was a Development and Test Engineer. Since 1999, he has studied various high-κ dielectrics and published more than 50 journal and conference papers. After his graduation, he has been continuing his research on the electrical characterization and reliability of advanced gate stacks at SEMATECH, Austin, TX. Byoung Hun Lee received the B.S. and M.S. degrees in physics from Korea Advanced Institute of Science and Technology, Daejeon, Korea, in 1989 and 1992, respectively, and the Ph.D. degree in electrical and computer engineering from the University of Texas, Austin, in From 1992 to 1997, he was with Samsung Semiconductor and, since 2001, has been with IBM. He has authored or coauthored more than 220 journal and conference papers in various semiconductor research areas including gate oxide reliability, SOI device and process, strained silicon devices, and high-κ/metal gate process and devices. He is currently on assignment at SEMATECH, Austin, as Manager of the Advanced Gate Stack Program, managing high-κ dielectric project, metal electrode project, material evaluation test structure project, and electrical characterization project.