THE PENNSYLVANIA STATE UNIVERSITY SCHREYER HONORS COLLEGE DEPARTMENT OF ENGINEERING SCIENCE AND MECHANICS

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1 THE PENNSYLVANIA STATE UNIVERSITY SCHREYER HONORS COLLEGE DEPARTMENT OF ENGINEERING SCIENCE AND MECHANICS UNDERSTANDING AND IMPROVING DEFECTS IN SILICON CARBIDE SEMICONDUCTOR DEVICES MATTHEW J. STOREY Fall 2011 A thesis submitted in partial fulfillment of the requirements for a baccalaureate degree in Engineering Science with honors in Engineering Science Reviewed and approved* by the following: Patrick M. Lenahan Distinguished Professor of Engineering Science and Mechanics Thesis Supervisor Bernhard R. Tittmann Schell Professor of Engineering Science and Mechanics Honors Adviser Judith A. Todd P. B. Breneman Deparment Head Chair Professor, Department of Engineering Science and Mechanics * Signatures are on file in the Schreyer Honors College and Engineering Science and Mechanics Office.

2 i Abstract Silicon (Si) has long been the leader in the semiconductor market covering a wide range of applications. Research efforts are attempting to replace silicon devices with those made from silicon carbide (SiC), especially in high frequency, high temperature, and high power applications. Currently, these SiC devices have detrimental limiting factors, which can be attributed to the high number of defects at the SiC- SiO2 interface. These defects are created during the manufacturing process. A comprehensive study of these defects needs to be done so that connections and alterations can be made to the manufacturing processes, leading to fewer defects in these SiC devices. Electrically Detected Magnetic Resonance (EDMR) studies were previously done in the lab and the majority of the defects are suspected to be silicon vacancies. In this thesis, capacitance- voltage electrical measurements were taken and used to examine defect densities in several SiC devices using the Gray- Brown and Jenq technique. The initial n- type 4H- SiC MOS thin oxide capacitors were not suited for the aforementioned electrical techniques. Instead, n- channel 4H- SiC MOSFETs with NO annealed and dry oxides were studied. The Jenq technique showed larger average defect densities in the dry oxide device, which is consistent with EDMR results done in the lab. The Gray- Brown method, on the other hand, was qualitatively indicative of similar behavior, but unresolved problems with accumulation capacitances limited the usefulness of that data.

3 ii Table of Contents Acknowledgements iv I. Introduction 1 II. Literature Review 3 Interface Characteristics for Si/SiO2 Interface 3 Advantages and Limitations of SiC Devices 5 Determining Defect Densities Through Electrical Measurements 10 General Capacitance Voltage Characteristics 10 Gray- Brown Method 14 Jenq Technique 17 III. Theory 20 Doping Concentration 20 Flatband Capacitance 23 Gray- Brown Method 25 Jenq Technique 30 IV. Experimental Procedure 31 Mounting the Device 31 CV Measurement System 32 Initial Low Temperature System 34 Initial High Temperature System 35 Complete Variable Temperature System 37 V. Results 39

4 iii VI. Conclusion 49 VII. Future Work 50 VIII. References 52 IX. Appendix 55

5 iv Acknowledgments I would like to thank first and foremost Dr. Patrick M. Lenahan for supervising this senior thesis. He allowed a certain degree of freedom for this thesis; ensuring that independent research took place while providing guidance when needed. I would also like to thank Brad Bittel, a graduate student, for assisting in the mounting and selection of the devices used in this thesis. Finally, special thanks to Corey Cochrane, Jacob Follman, and Thomas Aichinger for their general assistance whenever problems were encountered throughout the thesis.

6 1 I. Introduction Up until now, silicon (Si) devices have dominated the electronics market. Silicon is not favorable, however, for high temperature, high frequency, and high power applications. Instead, a close relative, Silicon Carbide (SiC), has emerged as the frontrunner to replace Si in these applications [1]. Silicon Carbide has some very desirable semiconductor characteristics, but most importantly, its native oxide can be thermally grown on the SiC substrate [2]. Both Si and SiC have SiO2 as its native oxides, and it s the semiconductor- oxide interface that is most important for the performance of the device. The only thing holding SiC devices back are their performance limiting defects at and near the SiC/SiO2 interface. It is vital that these interface states be characterized both electrically and chemically in order to improve production methods so as to reduce these limiting defects. One of the focuses in Professor Lenahan s lab has been characterizing the interface states in modern SiC devices (capacitors, MOSFETS, BJT, etc.). These characterizations were done with electrically detected magnetic resonance (EDMR). In order to fully characterize the defects found in these devices, both magnetic and electrical measurements must be implemented and eventually corrected. Magnetic measurement techniques are best suited for describing the physical and chemical composition of defects while the electrical measurements provide insight into the defects performance- limiting characteristics. The most recent EDMR measurements conducted in the lab (by Corey Cochrane) examined the types of point defects found at the SiC/SiO2 interface in several MOSFET devices with various manufacturing

7 2 parameters [1]. Based on the results of their EDMR measurements, point defects called silicon vacancies are present at the interface in SiC devices [1]. However, Cochrane s observations don t tell the full story. The results do not fully describe the electronic properties of the vacancies and do not rule out the inclusion of other defects. Now that the defects have been identified as primarily silicon vacancies, some electrical measurements can be made to describe how these defects will affect the device performance. This thesis will focus on making several electrical measurements on SiC devices with various manufacturing parameters to determine a relationship between manufacturing processes and the number of these defects present. Since this silicon vacancy at the interface might have multiple energy levels within the band gap, electrical measurements will be performed examining both near the band edges and near midgap. First, the Gray- Brown method will be used at various temperatures to measure the defect density and energy profiles near the band edges. Then, the Jenq technique will be performed to determine the density and energy profile of the SiC defects near midgap. At first, a simple approach will be implemented where these measurements will be taken at a discrete set of temperatures. Finally, a controllable and variable temperature system will be implemented to allow for greater resolution in these electrical measurements.

8 3 II. Literature Review Interface Characteristics for Si/SiO2 Interface Most modern day electronics contain various systems of integrated circuits. The most widely used component in these circuits is the metal oxide semiconductor field effect transistor (MOSFET). These are widely used because of their increasingly small size, cost and low power consumption [2]. MOSFET s based on the Si- SiO2 system are the most commercially available semiconductors on the market. There are three main regions within these MOS devices. First, there is the bulk oxide region, which acts as the insulating measure between the applied voltage (VG) and the semiconductor material. The second region is deemed the semiconductor- oxide interface and the third region is the bulk semiconductor material [2,3]. Figure 1 at the bottom of the page shows an example of a typical MOSFET device. The oxide layer is shown as the striped region and the p- type Si is the bulk semiconductor. The channel between the two n+ type Si doped regions is known as the inversion channel and is responsible for the majority of the functionality of the device. [Figure 1]: Typical construction of an n channel Si- SiO 2 MOSFET device [3].

9 4 The Si- SiO2 system resides in this inversion channel. A MOSFET has 3 modes of operation. The first is called the weak inversion mode. This is when the gate voltage (VG) is less than the device s threshold voltage (Vth). In this state, the MOSFET is essentially turned off except for some highly energetic majority carriers that travel through the inversion channel, which results in leakage current. When VG is slightly higher than Vth, the device is turned on and acts like a resistor, where the current passing through the inversion channel is dependent on the majority carrier mobility and the voltage applied across the drain and source [4]. Finally, the devices reaches a saturation current when the voltage across the source and drain is high enough to create an inversion channel pinch- off near the drain [4]. It has been shown that defects at or near the interface have adverse affects on the electrical performance of these devices [5]. These defects can be classified as either interface traps, oxide fixed charges, oxide trap charges, or mobile ionic charges. The mobile ionic and fixed oxide charges are located within the oxide layer of the device while the traps are located at or near the interface of the inversion channel in MOSFETs [2]. These traps are interface states that can alter their relative charge by interacting with mobile carriers within the Si system [2,6]. These interface states are present because of the difference in atomic structure between Si and SiO2, which create additional energetic states at positions 2-6 Å from the interface [7]. The typical density for interface traps in the Si- SiO2 system is somewhere between 10 9 and cm - 3 at energies near the midgap [2,3].

10 5 Advantages and Limitations of SiC Devices While silicon has many uses as a semiconductor, it is not optimal for high temperature, high power, and high frequency applications. Due to silicon s small band gap (1.1 ev), it has high leakage currents and unstable junctions above 150 C [8,9]. Because of this, wide band gap semiconductors have been researched to replace Si in these applications. One wide band gap semiconductor in particular, silicon carbide (SiC), is being heavily researched and shows the most promise in replacing Si devices due to it s high thermal conductivity, wide band gap, large mechanical strength, and radiation resistance [10,11]. Table 1 shows a comparison of some key parameters between silicon and some prominent silicon carbide polytypes for high temperature and high power applications. While the table only compares 2 polytypes of SiC, it is in fact the 4H- SiC polytype that has the greatest potential in these applications because of its higher band gap [12,13]. Examples of some high frequency applications are ultraviolet (UV) light emitting diodes (LEDs) and optical waveguides. Due to SiC s wide band gap (3-3.3 [Table 1]: Table comparing some key semiconductor properties between a couple SiC structures and Si [8]. ev), it is capable of either emitting or detecting blue or ultraviolet light [14]. With respect to waveguide applications, cubic SiC (3C- SiC) has a very large linear electro- optic effect with a

11 6 coefficient 1.7 times larger than GaAs, which does not involve any free carriers [14,15]. By not operating on free carrier effects like Si, 3C- SiC is capable of very high- speed modulations (GHz range) because the response time of the modulation is only dependant on the RC time constant of the SiC system and not the transient time through the device [14,16]. High temperature applications include monitoring combustion reactions in both automobile engines, high temperature manufacturing processes, and sensing devices in high temperature atmospheres, like inside a turbine. The intrinsic carrier concentration s interdependence on bandgap and temperature allow for wide band gap semiconductors (including SiC) to maintain performance at temperatures higher than Si. The following equation is a simple expression for intrinsic carrier concentration n i = N C N V exp E G 2kT (1) Two important conclusions may be drawn from equation (1). The first is the temperature in which a junction ceases to be a junction. For a doped p- n junction with a given bandgap, as the temperature increases, more electron hole pairs are generated and the Fermi level on each side of the junction moves closer to midgap. At a certain temperature, the intrinsic carrier concentration becomes greater than the doping concentration and the junction no longer exists, rendering the semiconductor device useless. For devices with a wide band gap, like SiC, they have

12 7 a much lower intrinsic carrier concentration for a given temperature and can still operate at a higher temperature for the same doping concentration in a Si device. For example, if a Si junction would fail at 150 C, then a SiC junction would fail at about 600 C [8,9]. High temperature device performance is also dependent on the leakage current of a MOSFET in its off state. This leakage current is proportional to the intrinsic carrier concentration, which once again means that a larger bandgap will allow for a smaller leakage current at any given temperature [8]. High power applications can include either energy storage or high power output semiconductor devices. In the latter case, SiC s large breakdown electric field makes it an ideal candidate for power applications in turbine engines, propulsion systems, aerospace electronics and others [11,17]. In general though, high power semiconductor devices must be able to withstand a large applied voltage. Once again, this can be explained by examining a simple junction. As a larger and larger reverse bias is applied across the junction, the increased band bending gives the minority carriers a larger potential until they have enough energy to collide with the particles in the bands generating electron- hole pairs. These pairs then have enough energy to collide with other particles in the bands generating more and more pairs. This causes the current in the device to increase exponentially until catastrophic failure. The impact ionization energy associated with this effect scales with the bandgap. Since SiC has a wider band gap than Si, the minority carriers must have more energy to span the potential across the bandgap to collide with particles in the bands [8,9].

13 8 While the above properties hold true for most wide band gap semiconductors, SiC has one advantage over all the competition: SiC can be thermally oxidized to grow SiO2 [18]. The only other semiconductor material that has a natural oxide is Si. This allows for easy integration of the semiconductor during MOS device manufacturing. Due to SiC s apparent advantages and similarities with Si, SiC has a lot of potential to replace Si in high temperature and high power applications [19]. While there are many advantages to silicon carbide over silicon, there are currently just too many defects generated within the production process to allow SiC devices to be mass- produced and marketed [10,11,20]. Cree was the first company to produce a commercial SiC power MOSFET, the CMF20120D, which was released in the first quarter of 2011 [21]. These defects are typically measured as a density, which reports the number of defects per area per energy within the bandgap. While the SiC- SiO2 interface behaves similarly to the Si- SiO2 interface, the defect density of the former is almost two orders of magnitude higher than the latter [18,22]. Since these defects have energy levels found within the bandgap of SiC, these defects can have adverse effects on the electrical and optical properties of these devices [12]. It has also been proposed that due to SiC s large band gap, some interface state defects might have multiple states within the bandgap. This leads to some defects having multiple energy levels [13]. With respect to MOSFET s, there are two major electrical properties adversely affected by these large defect densities. The first limitation deals with

14 9 instability in the MOSFET s threshold voltage. As various gate voltages are applied, some interface states are charged and this affects the movement of the majority charge carriers, causing the threshold voltage to shift either positively or negatively [23]. Since this effect varies with gate voltage and temperature, it leads to very unreliable devices. The second limiting factor in SiC MOSFET devices is their reduced effective charge carrier mobility. As the charge carriers travel through the inversion channel, the interface states can either trap the charge carriers or scatter them through coulomb interactions [22,24]. This reduces the lifetime of these carriers in the inversion channel, therefore reducing their mobility. There have been some recent advancement in reducing defect densities and increasing the channel mobility, like N passivation, but it is not understood why [24]. One group looking into the defect density of current SiC devices has found that there is a large peak close to the conduction band edge (0.1 ev from EC) in n- type devices [24]. In summation, the purpose of examining interface state densities is due to the their connection with the processing methods used in fabricating these MOS devices. Once the kinds of defects and their densities are determined, the processing techniques could be altered to ultimately reduce the number of these defects and improve the performance of these MOS devices [2].

15 10 Determining Defect Densities Through Electrical Measurements General Capacitance Voltage Characteristics For shallow impurities (near the interface) electrical measurements are best for determining the defect density profile [2,3,25]. Out of all the possible types of electrical measurements, capacitance- voltage (CV) measurements are the easiest to implement [2,25]. There are two different classifications of capacitance measurements: high frequency and low frequency. High frequency measurements used an applied AC voltage of 100kHz or higher (usually no higher than 1MHz), whereas low frequency AC voltages are typically around 10kHz or lower. This thesis will deal with high frequency CV measurements, so an explanation to the regions of high frequency CV curve will be detailed below. In order to make CV measurements, one must drive the MOS device with a high frequency capacitance bridge (1MHz or 100kHz), which is typically connected to the top and bottom of the MOS capacitor [25]. The base or bottom contact on the substrate acts like a complex and heavy load, which will elicit large impedances and affect the measurement accuracy. In order to reduce the inaccuracies introduced through the connection points, the contacts for the gate and substrate could both be made on the top of the mounted device [26]. While a high frequency AC voltage is being applied to the device, a slow DC bias is swept from ether a large positive value to a large negative value or visa versa [2,25]. A typical CV curve is composed of three main regions, which are the

16 11 accumulation, depletion, and inversion regions. Figure 2 shows the detail of a CV curve for a p- type semiconductor device, which will be detailed below. If the MOS device were n- type, then simply reverse the polarity of all of the applied gate biases. [Figure 2]: Graph of a typical CV curve for a p- type Si MOS capacitor [25]. The accumulation region in the CV curve (for a p- type MOS capacitor) occurs when a large negative bias is applied to the gate. This causes majority carriers (holes) to accumulate at the interface, hence the name accumulation region [2,25,27]. As the gate voltage becomes slightly positive, the majority carriers are repelled from the interface and a region forms depleted of carriers (called the depletion region), which creates an insulator and effective capacitance within this region. The capacitance bridge now picks up two capacitances in series: one from the oxide and one from this depletion region [25]. As the gate voltage becomes more positive, the depletion width increases, thereby deceasing the effective capacitance and the overall capacitance. This continues until a minimum total capacitance value is reached. In a physical sense, this occurs when the gate voltage becomes such a large positive value that the minority carriers (electrons) are attracted to the interface and this

17 12 layer is called the inversion layer because the carrier polarity has been inverted [6,25]. The amount of minority carriers available is limited, which is why at large enough positive gate biases the depletion region does not increase any further and the capacitance value becomes constant again [25]. Most of the interesting characteristics found in the CV curve are due to a difference between the response of the majority and minority charge carriers. For AC voltages applied within the range of 0-1MHz (this covers both high and low frequencies), the majority carriers respond very rapidly to the voltages over all of the DC biases [2]. The minority carriers, however, behave differently depending on the frequency of the AC voltage. For high frequencies, the minority carriers can t follow the AC signal and therefore don t contribute to the capacitance in the inversion layer (as stated before). On the other hand, at low frequencies, the minority carriers can still follow the signal and therefore create a different shape in the CV curve in the weak to strong inversion region [28]. At lower frequencies when the minority carrier concentration becomes comparable to the majority carrier concentration, the capacitance will increase back to the accumulation capacitance in the inversion region [2]. It is important to note that for these CV measurements, the accuracy does not depend on the methodology behind the data acquisition but rather the quality of the equipment and signal analysis techniques used [2,25]. There are several sources of error that can be controlled to reduce the overall inaccuracies in the measurements. First, coaxial cables with minimal cable lengths should be used for CV measurements to reduce the stray capacitance from these cables [26]. Secondly,

18 13 offset and gain errors are common, but these are typically corrected internally through the AC impedance meter being used to measure the capacitance [26]. Finally, the capacitor being measured has inherent impedance with an associated frequency. As the frequency of the applied AC voltage increases, a larger phase error is introduced due to the difference in frequencies. This is only a problem for frequencies larger then 1MHz and would then have to be taken into consideration [26]. Since this thesis is concerned with SiC devices and their defect densities, some CV characteristics related to these two topics will be reviewed. SiC is a wide band gap semiconductor, and this means that there are fewer minority carriers available in the inversion region of the CV curve. The bias then shifts it into quasi- equilibrium, corresponding to its inversion region. The very slow generation of minority carriers causes the depletion layer to dip into the bulk of the device. This non- equilibrium condition drives the overall capacitance even lower than the quasi- equilibrium values in the inversion region, which is called deep depletion [2,19]. Next, the contributions of defects to the CV curve will be looked at. In general, bulk traps far from the interface dominate in the inversion layer while interface traps have a large effect on the depletion region of the CV curve [2]. Since this thesis is concerned with the effects of interface states, the following two techniques in this review (Jenq and Gray- Brown) examine and analyze changes in the depletion region of the CV curves. The defects affect the CV curve the same way as the majority and minority charge carriers do, which is through their response to the applied AC voltage. The interface states have a large response time, especially at

19 14 energies near midgap, and therefore do not respond to the AC voltage. They do, however, still respond to the applied DC voltage. As the DC voltage is slowly changed, the depletion layer equilibrates its shape and this leads to a change in the charge density within the depletion layer. With defects present, this also leads to a change in the interface state charge density, which will stretch out the slope of the CV curve [2]. Due to the combination of SiC having a wide band gap, deep depletion region, and unresponsive interface states, the CV curves look almost ideal at room temperature [19]. This doesn t mean that there are no interface states present; it just means that special techniques must be used to measure the interface states within the band gap. The next sections will outline the basic theory behind two techniques that cover different areas of the band gap. One will use light as a stimulus to fill interface states near midgap and the other will use various temperatures to measure near the band edges (less than 0.6 ev from the majority carrier edge) [18]. Gray-Brown Method The Gray- Brown method uses high frequency CV measurements at various temperatures to determine the defect density of interfaces states. At room temperature, the interfaces states near the majority carrier band edge have a small enough response time to react to the AC voltage. At lower temperatures, the response time increases so that they can no longer respond to the high frequency AC voltage [3]. Therefore, the Gray- Brown method typically measures CV curves

20 15 between room temperature and liquid nitrogen temperatures (77 K) so that the defect densities can be determined near the majority carrier band edges [2,3,29]. In theory, this method works as follows: given a specific band bending at a high temperature, the [Figure 3]: High frequency curves obtained at 20K increments from 300K to 80K [31]. band bending is held constant by adjusting the gate voltage as the temperature slowly decreases. In practice, the Gray- Brown method works by obtaining C- V curves for the semiconductor device at various temperatures. Since the Fermi energy moves as the temperature changes, then at various temperatures the Fermi level will be at a different interface trap level within the band gap. When the temperature is high, the Fermi energy is closer to midgap than at lower temperatures. At the initial temperature value, a capacitance value within the depletion region can be associated with a specific band bending. As the temperature changes and the C- V is shifted either left of right, the amount of gate bias needed to obtain the same band bending value as before is proportional to the additional number of defects filled due to that change in temperature [2,3,30]. Figure 3 shows the various CV curves obtained at 20K increments ranging from temperatures of 300K to 80K [31].

21 16 In order to determine the defect density, the temperature of the system is related to the Fermi level. A plot of change in gate bias vs. change in temperature will give a curve proportional to the defect density of interface traps [2]. Any band bending can be chosen for the reference case, but there are a couple advantages in choosing the flat band condition as the reference band bending. First, the shift in the flat band voltage from ideal (VG = 0 V) is directly related to effective charges present at the interface, like fixed oxide charges and charged interface states [18]. Also, the Fermi level is easy to calculate in the flat band condition because the surface potential is equal to the bulk Fermi level. Finally, by using the change in surface charge as the relation to interface density, the oxide space charge doesn t affect the results since it is a constant and exerts a constant effect regardless of the temperature of the system [30]. It has been shown though that at higher temperatures, these charged interface states have large contributions to the capacitance near flat bands [32]. Overall, the two most important parameters needed before applying the Gray- Brown method are expressions for the flatband capacitance and the dopant ionization with respect to temperature [29]. Using a method similar to Gray- Brown, some initial research on 4H- SiC n- type MOS capacitors has been done by another research group [24]. Through their investigation, they found rightward shifts in the CV curves as the temperature was decreased. As lower temperatures were reached, the Fermi level approached the conduction band edge. The large number of defects with energies near the conduction band edge trapped majority carrier electrons, which led to a large negative interface state charge. This negative charge increase near flatband caused

22 17 the rightward shift in the CV curve [24]. They concluded from this that there was an extremely high defect density approximately 0.2 ev from the conduction band edge [24]. Before using this method, there are some precautions and limitations that must be reviewed. First, it is important to note that the band gap s temperature dependence is negligible over the range of temperatures used in Gray- Brown [24]. Also, this method is limited to a small range within the band gap [29]. Finally, this method has been criticized due to a potential false peak in the defect density near the band edges [2]. As a band edge is approached, there is a sudden decrease in the capture cross sections of the interface states, which leads to a sudden shift in the flatband voltage around 0.1 ev from the band edge [32]. In order to remove this supposedly false peak, an applied AC voltage with a frequency of 200 MHz or higher is necessary, although this peak has also not been proven to not exist [3,32]. Jenq Technique While the Gray-Brown method determines interfaces state defect densities at energies near the majority carrier band edge, another approach must be used to examine these densities in the middle portion of the gap. For SiC, the Jenq technique is great for extracting an average defect density over the middle of the gap because this technique requires the device to enter deep depletion, which SiC MOS capacitors readily enter at room temperature [18].

23 18 The following steps outline the general procedure for the Jenq technique. First, the SiC MOS device is biased into accumulation and then swept into deep depletion. When the device is in deep depletion, a non-equilibrium state exists because there are not enough minority carriers in the depletion region and not many of the interface traps are full [33]. The device is then illuminated in deep depletion, which generates electron-hole pairs. There are now enough minority carriers present to fill most of the interface states, creating an equilibrated inversion region [18,28]. The light is then turned off and then biased back into accumulation. While still in the inversion region, the interface states retain their minority carrier charges because they can t respond to the high frequency AC voltage [33]. Once the device transitions into the depletion region, the majority carrier concentration becomes noticeable and also gets trapped by the interface states. This causes a charge cancellation within the interface states. The bias voltage range in which this process occurs is called the surface state ledge [18,33]. The hysteresis just below the onset of this ledge corresponds to the number of interface states that couldn t respond to the AC voltage [91]. This range of interface states accounts for almost all of the surface states in the SiC MOS capacitors (around 3eV of the band gap) [3,33]. Figure 4 shows the two CV curves measured in the Jenq technique. The lower curve is the [Figure 4]: Example CV curves using the Jenq technique at room temperature for a p- type SiC MOS capacitor [33]. first sweep from accumulation to deep depletion. The light was then

24 19 turned on, increasing the capacitance until it reached equilibrium in inversion. Finally, the upper curve shows the second sweep from inversion back to accumulation. It is important to note that any additional hysteresis from midgap to accumulation in the second curve is due to charges trapped in the oxide and not the interface defects [2,33]. Another way to remove the effect of oxide charges is by running two separate sets of sweeps. The first set of sweeps can be done completely in the dark. If there is hysteresis present, it is entirely due to the oxide charges and can then be subtracted out of the second set of sweeps that include illumination [34].

25 20 III. Theory The focus of this thesis is to ultimately examine the density of defects at various energy levels within the bandgap. Each method described in the literature review has a certain range of the bandgap in which it is applicable. Therefore, by implementing a procedure using a combination of the Gray- Brown and Jenq technique, a larger range of the band gap can be examined. While the general theory of operation has already been detailed for these two CV methods, the specific methods implemented in this thesis will now be outlined. Doping Concentration As stated earlier, the two parameters needed for a given device before the Gray- Brown method can be implemented are the doping concentration and the flatband capacitance [29]. Since the relationship for flatband capacitance used in this thesis also depends on the doping concentration, this value will be calculated first [35,36]. The Gray- brown method requires both CV curves and flatband capacitances to be measured at various temperatures. Therefore, a method must be implemented to determine the doping concentration of the device at these various temperatures. Theoretical descriptions of ionized doping concentrations can be modeled, but these models are scarce for SiC devices, especially as a function of temperature.

26 21 Therefore, the dopant concentration will be determined experimentally. Using the CV curves measured at various temperatures, the doping concentration can be found from each curve [2]. MOS capacitors were the first devices examined in this thesis because the dopant concentration can be measured the closest to the interface in these devices, which is important when the goal is measuring defect densities at the interface [2,3]. The following equation can be used to determine the doping concentration for a given high frequency CV curve 2 N = d 1 qε o ε s dv G C 2 (2) where N is the doping concentration, q = C is the elementary charge, ε o = F /cm is the constant of permittivity, ε s is the dielectric constant of the bulk semiconductor material, VG is the gate bias voltage, and C is the high frequency capacitance [2,37]. As one can see from equation (2), the doping concentration is inversely proportional to the derivative of the 1/C 2 vs. VG plot. This plot is a discrete set of data points, which means the derivative can be approximated as the slope of the least squares regression equation calculated to fit the data set. Equation (2) is based on an ideal case related to high frequency CV curves. In the depletion region, majority carriers are lacking, leaving minority carriers and ionized dopants. Since the minority carriers can t follow the high frequency AC voltage, the depletion

27 22 capacitance measured in this region contains information on the charge of the ionized dopants present. Therefore, when examining the graph of 1/C 2 vs. VG, the slope of interest is the one corresponding to the depletion region. Ideally, if the device was uniformly doped the slope in this region should appear linear [2]. This method was chosen because it is very simple and straightforward to implement, but there are a couple sources of error that might affect the accuracy of the calculated dopant concentration. First, equation (2) was derived in an ideal case where no interface states were present. Since interface states cause stretch- out in the CV curve, they will also affect the slope of the 1/C 2 vs. VG plot. This error is marginable at defect densities less than ~10 12 cm - 2 and can be reduced further at higher frequency CV measurements [2,37]. It is initially assumed that the defect densities in the SiC MOS devices are not large enough to cause meaningful error in the dopant concentration calculation, but an adjusted expression is proposed here for future work. The following expression is for the doping concentration adjusted for the presence of interface states 2 1 C /C LF ox 1 C N adj = HF /C ox d 1 qε o ε s 2 dv G C HF (3) where Nadj is the dopant concentration corrected for measured interface states, CLF is the measured low frequency CV data set, and CHF is the previously measured high

28 23 frequency CV data set [2]. The minority carriers and interface states respond to low frequency AC voltages, so the combination of both high and low frequency CV data provides the complete picture needed for the doping concentration [2]. Finally, some error is introduced due to the fact that not all of the dopants are ionized. The previous expressions assume that all if not most of the dopants are ionized at all of the various temperatures, but this is not the case. In fact, even at room temperature it has been shown that some dopants in SiC devices are not ionized [35]. This level of ionization is still being studied for SiC devices and difficult to correct for at various temperatures. Flatband Capacitance The next step is determining the flatband capacitance for each measured CV curve. The flatband capacitance method is a simple way to determine the flatband capacitance given the temperature of the device and its dopant concentration. The flatband condition is defined as when the surface potential is equal to the bulk potential of the semiconductor [2]. In the ideal case where there are no oxide charges or interface states, the potentials are equal when there is no applied bias to the gate (VG=0V). In reality, however, there are both oxide charges and interface states present. With no bias applied, the fixed oxide charges and oxide trap charges will shift the surface potential, causing the bands to bend. In order to meet flatband

29 24 conditions, a slight bias must be applied to create a depletion region. The dopants in the depletion region will offset the oxide charges and the surface potential will again be equal to the potential deep in the bulk semiconductor. The width of the depletion region needed to offset the oxide charges is the Debye length, a characteristic length of semiconductor materials. This capacitance measured at flatband is now modeled as the capacitance of the oxide in series with the capacitance of a depleted layer with a Debye length as its thickness 1 C = (4) C ox C D where C is the measured capacitance, Cox is the oxide capacitance, and CD is the depletion layer capacitance. Equation (4) can be rewritten specifically for the flatband capacitance as follows C FB = C ox ε oε s /L D C ox +ε o ε s /L D (5) where LD is the Debye length [24,38]. The Debye length is defined as L D = ε oε s k B T q 2 N (6)

30 25 with k B = m 2 kgs 2 K 1 is the Boltzmann s constant, and T is the temperature in Kelvin [24,38]. As with the analysis of the doping concentration, there are a couple possible sources of error in this approximation. Once again, this model assumes that all of the dopants ionize, but this is not approximately true with SiC so some error will be present due to this simplification [38]. For large interface state densities, considerable shifts could occur in the flatband capacitance [39]. Corrections to these sources of error are very difficult to implement and might not be fully understood for SiC. Gray-Brown Method Now that the doping concentration and flatband capacitance has been determined for each CV curve at a given temperature, the Gray- Brown method can be applied to determine the defect density. The first step in the Gray- Brown method is to determine the position of the Fermi level within the band gap for each temperature [24]. It is widely accepted to describe the position of the Fermi level relative to the majority carrier band edge. The following expression is for the relative position of the Fermi level for an n- type MOS device. E C E F = k B T ln N C N (7)

31 26 where EC is the conduction band edge, EF is the Fermi energy level, and NC is the effective density of states near the conduction band. A similar expression can be determined for a p- type MOS device. E F E V = k B T ln N V N (8) where EV is the valence band edge, and NV is the effective density of states near the valence band edge. These effective densities of states are defined as follows N C,V = 2M C,V * 2πm n,p h 2 k B T 3 / 2 (9) The term MC represents the number of equivalent minima in the conduction band. Since SiC is indirect, there could be multiple minima in the conduction band that would add to the effective density of states at this band edge [24]. Conversely, MV is the number of equivalent maxima in the valence band. The terms mn* and mp* are the effective masses of the electrons and holes respectively. Finally, h = m 2 kg /s is Planck s constant. Given any two CV curves measured at different temperatures, T1 and T2 (where T2 < T1) the change in energy in the band gap is simply the difference in the relative Fermi levels calculated using equation (7) at the CV curves respective

32 27 temperatures. As one can see, this difference in energy is not just equal to the difference in temperature because the relationship in (7) and (9) between temperature and Fermi level position is more complex than simply linear. Therefore, the forward difference in Fermi energy between the CV curves is ΔE = E F, T1 E F,T2 (10) where the energies are the Fermi level positions at the temperatures of each CV curve. The next step is to use the flatband capacitance calculated at the given temperature of each CV curve and find its corresponding flatband voltage [24]. The CV curve detailed earlier in this thesis was for a high frequency signal on a MOS capacitor. Since these types of CV curves are one- to- one, there is only one corresponding flatband voltage to the calculated flatband capacitance. If, however, the high frequency signals are applied to a MOSFET, the capacitance in the inversion region will behave differently. This is due to the presence of oppositely doped semiconductor regions near the inversion channel. As the depletion region reaches its maximum, the potential between the bulk semiconductor and the highly doped source and drain decrease, causing majority carriers from the source and drain (which are minority carriers in the bulk) to escape into the depletion region. This flux in minority carriers increases the number of charges at the interface, thereby increasing the capacitance. This means that for a given flatband capacitance, there might be two corresponding flatband voltages, one in the inversion region and one

33 28 at the cusp of the accumulation region. The appropriate flatband voltage to use for the Gray- Brown method would be the one that separates the accumulation region from the depletion region. When looking at the same two CV curves at temperatures T1 and T2 (where T2 < T1), this difference in flatband voltage is related to the number of defects that were filled in between those temperatures. Since the charged states lie at the interface, the capacitance associated with these newly charged states is simply the oxide capacitance. This relation between the difference in flatband voltage and net charge created by the filling of interface states is Q it = C ox V FB,T2 ( V FB,T1 ) (11) where Qit is the charge of the newly filled interface states, Cox is the capacitance of the oxide per area (determined from the capacitance measured in the accumulation region), and VFB are the flatband voltages on the CV curves at T2 and T1. By definition, each interface state can only trap one charge carrier. This means that the total charge found in equation (11) is directly related to the number of filled interface states through the equation ΔN it = Q it q (12)

34 29 In equation (12), Nit represents the number of filled interface states between the temperatures T1 and T2 and q is the elementary charge. Finally, using equation (10) and (12) the average density of states can be determined between any 2 temperatures. The density of states is defined as the number of states per area per energy. This can be written as D it = ΔN it ΔE (13) where Dit is the average density of states. The end result will be an average density of states calculated for every set of CV curves measured at different temperatures. These densities of states can be plotted with respect to their position in the band gap to give a profile of the density of states across a certain region of the band gap. The position of the energy within the bandgap for each density of states is based off of the average Fermi level position between two temperatures [24]. E C E ave = E C E F,T 2 ( ) + ( E C E F,T1 ) 2 (14) Again, these density of states profiles are only determined for a small range of the band gap near the majority carrier band edge. The following technique could give a rough density of states over the middle of the band gap.

35 30 Jenq Technique This technique is very similar to the Gray- Brown method, except that it covers a different region of the bandgap. In order for this technique to work, the device must be able to enter deep depletion. Once the device is in deep depletion, light is turned on and carriers are generated and trapped in the interface states. If CV measurements are done on a transistor, minority carriers are provided by source and drain instead of external light. As the device is bias towards accumulation, the interface states retain their charges until majority carriers are present in depletion. This interface state ledge leads to a hysteresis in the two CV curves being measured. The voltage difference between the lower CV curve and the onset of the interface state ledge is the shift in the threshold voltage. This is related to the number of interface states near midgap, similar to equation (11). Q it = C ox ΔV TH (15) where VTH is the threshold voltage for both the sweep into deep depletion and then back into accumulation. Equation (12) can then be applied to determine the number of interface states measured near midgap per area. If the density of states is desired, then the average energy in the middle of the band gap could be used to find the number of states per area per average energy.

36 31 IV. Experimental Procedure Mounting the Device Given a device for testing, the first step was to mount this device on a tee. The tees are made of plastic with thin gold surface wires along the entire tees connected to large area gold pads at one end. The devices typically have an aluminum back contact, which can be glued to one end of one of the gold wires. The gate, source, and drain of the MOS device (or just gate if it s a capacitor) are then connected to the other 3 gold wires through a wire- bonding machine. Four coaxial cables are then connected to the four gold pads at the other end of the tee. The shielding and core connection are separated with the core connections being soldered to the gold pads while the shielding is bound and soldered together as the ground. The other ends of these four coaxial cables are then soldered to a 7- pin female connector with four of the seven pins being assigned a device connection (gate/bulk/source/drain). A fifth pin is then designated the ground connection. [Figure 5]: Example of a fully mounted device on a tee with a 7- pin connector. Electrical tape and glue are then put on

37 32 the interface of the coaxial wires and gold pads to increase the stability of the connection. Figure 5 shows an example of what a fully mounted device looks like. The device is mounted in the middle of the tee and then connected to the 7- pin connector through the coaxial cables. All of the experimental equipment in the lab has been adapted to use the 7- pin connector and tee. The next step is to connect this mounted device to the system needed to perform CV measurements. CV Measurement System The system used to measure CV curves is comprised of three devices. A computer software package gives commands to the 4145B Semiconductor Parameter Analyzer regarding the bias voltage. This information is then input into a Boonton 72C Capacitance Meter, which measures the capacitance at every designated bias voltage. The capacitance bridge has only two inputs: high and low. Therefore, a custom made box is needed as an adapter between the 7- pin tee connector and the high- low BNC cable input of the capacitance meter. The adapter is set up so that MOS capacitors are low for the bulk and high for the gate. Transistors have the bulk as low while the gate, source, and drain are all high. Figure 6 shows the model high frequency capacitance meter used in these experiments. Also in the picture is the adapter box connected to the input on the front face of the meter. The output of the

38 33 [Figure 6]: Boonton 72C Capacitance Meter with tee adapter (shown top right). [Figure 7]: Parameter Analyzer connected to BASIC software used to measure CV curves. capacitance meter is a relative number between 1 and 3, which means the absolute scale must be set on the right- hand side of the box. The ranges are 1, 3, 10, 30, 100, 300, 1000, and 3000 pf. An initial capacitance reading must be taken with the bridge to determine the capacitance range of the device before CV curves can be measured. After the device is plugged into the capacitance meter in the correct capacitance range, the parameters were set for the CV measurement using a BASIC program compatible with the parameter analyzer. The CV sweep was set for the slowest sweep speed (which was one step per second) and set for 2 sweeps: one from accumulation to inversion, hold for 100 seconds, and then sweep back from inversion to accumulation. The bias was from - 18V to 18V. If the device were n- type, the sweeps would start at 18V, then swept down to - 18V, held for 100 seconds, and swept back up to 18V. If the device were p- type, the opposite voltages would be

39 34 applied. A bias step size of 50mV was chosen to allow enough time for the charge carriers to react to the high frequency AC voltages applied by the capacitance bridge. Finally, a linear step function was chosen because that is common practice in making CV curves. The capacitances measured at each bias voltage were output to the laptop through the software and collected. Figure 7 shows the parameter analyzer (behind the laptop) with the software running on the laptop. This setup as it is was used to make the first CV measurement at room temperature. A small black cover was placed over the tee so that the ambient light did not affect the charge carriers in the devices. To make these measurements at temperatures above and below room temperature, some simple temperature setups were used as detailed below. Initial Low Temperature System To measure CV curves on devices below room temperature, a simple setup was implemented for the first devices measured. As shown in figure 8, the tees were still connected to the capacitance meter and controlled through the parameter [Figure 8]: Shown here is the initial low temperature setup for the first couple devices tested. analyzer software; the only difference is the tee container. For these measurements, the

40 35 tee is placed in a large copper air chamber with a thermocouple (shown left in figure 8). CV curves at two different temperatures were measured in this setup. The first temperature was around C, which was accomplished by filling the dewer with liquid nitrogen. This caused the air inside the copper chamber to cool. Since a temperature gradient was set up inside this copper chamber, a thermocouple was placed at the same depth as the device on the tee so that an accurate temperature reading could take place. The CV curves were not measured until the temperature stabilized with a drift of a degree or less. The second temperature measured below room was near 0 C. This was accomplished by filling the dewer with ice water and waiting for the temperature of the air inside the copper chamber to stabilize around 3 to 4 C. The final CV curves measured for these initial two devices used a high temperature system. Initial High Temperature System The high temperature system consisted of three components. The first was the heating stage. This was simply a custom spectroscopy stage built to house a tee with a hole in the back of it. Figure 9 shows the spectrometer with the custom- built glass stage in the middle. Behind the stage was a large dewer with a glass chamber attached to the top of it. Also, air was fed into the large dewer through a plastic hose. As air is passed into the dewer and through the glass chamber, a heater in the

41 36 [Figure 10]: Dewer with heating element inside the glass connector (blue). [Figure 9]: Stage used for initial high temperature CV curves. Glass rod connected to back of stage runs hot air through glass dewer shown here. [Figure 11]: Analogue temperature control system. chamber heats the air resulting in hot air blowing over the tee in the stage. Figure 10 shows a picture of this dewer and chamber connected to the back of the spectrometer stage. The temperature of the air passing through the chamber and stage is regulated through the IBM variable temperature unit shown in figure 11. A thermocouple is placed in the stage and its temperature is input into this variable temperature system. Once a desired temperature is input into the front of the variable temperature unit, an error gauge shows the relative difference between the desired temperature and the actual temperature inside the stage. The second gauge on the system shows the current being fed to the heater inside of the chamber. This current can be limited using a dial on the front of the temperature system. Based on

42 37 a positive feedback between the thermocouple and the current through the heater, the system adjusts the current through the heater to maintain the desired temperature. For the first couple devices, CV measurements were taken at 360K (87 C) and 405K (132 C), This system initially wasn t used for both temperatures above and below room temperatures because it would cause freezing inside the spectroscopy chamber, which would be a problem. After the variable temperature system was moved to another location in the lab, it was used for all temperature ranges. The last two devices studied in this [Figure 12]: New stage exclusively used for variable temperature system. Stage consists of a glass chamber with thermocouple and input nozzle for air. thesis were measured using this complete system and outlined below. Complete Variable Temperature System [Figure 13]: Complete variable temperature system, which includes a liquid nitrogen filled dewer and heating chamber. This complete variable temperature system was used

43 38 to measure the CV curves on the transistors in this thesis. This system is very similar to the initial high temperature system with a few adjustments. First, a new stage has been made just for this system. Figure 12 shows the construction and function of this stage. The tee is placed in the glass tube from one end with other end of the glass chamber housing the thermocouple. There is then an opening in the front for the glass chamber used to heat the gas being blown over the device (blue glass rod in figure 12). The second change is the addition of liquid nitrogen into the large dewer. In addition to a heater in the glass chamber, there is also a heating coil at the bottom of the dewer. This coil heats up a portion of the liquid nitrogen and causes it to evaporate into the chamber. The heater in the glass chamber can then heat this gas to any temperature between 95K and room temperature. Figure 13 shows the variable temperature system set up measuring CV curves below room temperature with a dewer filled with liquid nitrogen. The evaporation rate and heating limit in the chamber can be set through the variable temperature controller. Using the dewer filled with liquid nitrogen, CV curves were measured at temperatures of 155K, 200K, and 250K below room temperature. Next, one CV measurement was taken at room temperature with no temperature control. Finally, CV curves of 350K and 400K (above room temperature) were measured by replacing the liquid nitrogen with an air hose. It is important to note that all CV measurements made with the setup in figure 13 were done once the desired temperatures were equal to the temperature of the gas passing over the device.

44 39 V. Results The first device examined was an n- type 4H- SiC MOS capacitor from General Electric. This capacitor had an area of 150µm by 150µm and an oxide thickness of approximately 5nm on the manufacturing sheet. The manufacturing parameter examined on this device was its NO annealing treatment of the oxide. As previously detailed, the CV curves were measured using the initial high and low temperature setups. As a result, five temperatures were taken between 160K and 405K and plotted in figure 14. Upon inspection of these curves, it was determined that neither the Jenq technique nor the Gray- Brown technique could be used on this device. First, the Jenq technique was attempted, but there was a thick gold metal coating across the entire top of the capacitor. This coating did not allow any light through, which means light could not be used to bring the device from deep depletion to equilibrium in the inversion region. The capacitance in deep depletion (shown in [Figure 14]: CV curves at five different temperatures for an n- type 4H- SiC MOS capacitor with NO annealed oxide.

45 40 figure 14) is very small relative to the accumulation capacitances. Therefore, a noticeable jump in the capacitance should have taken place when the device was exposed to the light. Not only was there no increase in the capacitance, but there was also little to no hysteresis present in the sweep back up from inversion to accumulation. The Gray- Brown measurements were also attempted but didn t provide useful data because the capacitances in the accumulation region displayed anomalous behavior. First, the capacitance never leveled off to a constant oxide capacitance in accumulation. Since a reasonable oxide capacitance could not be determined from the CV curve, the flatband capacitances and voltages could not be determined. Second, the accumulation capacitance should roughly stay the same over the range of temperature used in this thesis. The results, however, showed that the accumulation capacitance spread over a wide range of values. [Figure 15]: Leakage current as a function of bias voltage through the oxide of a n- type 4H- SiC MOS capacitor.

46 41 These unusual CV characteristics might have something to do with the fact that this capacitor has an extremely thin oxide. One reason why the accumulation capacitances spread might be due to the series resistance. As the oxide thickness deceases, the oxide capacitance increases. This causes the RC time constant of the device to increase. If this time constant approaches the inverse of the AC voltage sampling frequency, the impedance of the bulk device could strongly influence the measured capacitance. This RC time constant problem is most likely to be encountered in very high capacitance devices with thin oxides. Another possible problem lies in the leakage current through the thin oxide. Figure 15 shows the measured current through the oxide as the bias voltage was varied. After 2 volts, there is a couple milliamps of leakage current, which is high enough to interfere with the capacitance measurements across the oxide. [Figure 16]: Various CV curves measured at different temperatures on an n- type 4H- SiC MOS capacitor with no oxide treatment (dry oxide).

47 42 A second 4H- SiC MOS capacitor from General Electric was examined that had the same manufactured dimensions. The only difference was the manufacturing parameter of interest, which is the oxide treatment. Unlike the previous MOS capacitor, this device had no treatment (dry oxide). Figure 16 shows the CV curves measured for this dry oxide MOS capacitor at 4 temperatures ranging from 141K to 360K. These CV curves were measured using the same initial temperature setup as the first set of data. Once again, the accumulation capacitances continue to trail off and do not steady, making the determination of the oxide capacitance impractical. Also, these accumulation capacitances are spreading out similar to the previous device. Since the oxide treatment is independent of the proposed problem (oxide thickness), the same unusual characteristics were viewed, which made the implementation of the Jenq and Gray- Brown impractical again. Since the problems with the devices up to this point could have been due to the use of a thin oxide [Figure 17]: Leakage current through n- channel lateral 4H- SiC MOSFET.

48 43 (5nm), a couple thick oxide devices were examined. The third device in this thesis is a 4H- SiC lateral MOSFET from General Electric. It is an n- channel MOSFET, which means the source and drain regions were implanted with nitrogen while the substrate is p- type 4H- SiC with a doping of 1x10 17 cm - 3 on the manufacturing sheet. This device is also listed as having a lateral area of 100µm by 100µm and an oxide thickness of 50nm. Finally, similar to the first pair of devices, the manufacturing parameter of interest is the treatment of the oxide growth. This device had an NO anneal at 1175 C following the initial growth of the SiO2 oxide. Before any extensive work was done on this device, the leakage current was measured to make sure the oxide wasn t losing charges. Figure 17 shows the measured leakage current through the oxide of this MOSFET. The maximum current measured is on the order of microamps, which has negligible effect on the charge loss across the capacitor. [Figure 18]: CV sweep down to inversion then back up to accumulation for a room temperature n- channel 4H- SiC NO anneal lateral MOSFET.

49 44 The first technique applied to this device was the Jenq technique. The CV curves measured behave differently than a capacitor because of the presence of oppositely doped source and drain regions at the interface. Figure 18 shows a typical CV curve measured on this lateral MOSFET. The device never stays in deep depletion because it gathers minority charge carriers from the source and drain. These excess minority carriers in the inversion region also fill interface states during the sweep down to inversion. As the device is swept back up to accumulation, the interface states slowly begin to lose their charges and hysteresis is observed between the two sweeps. When the device enters the depletion region, the curves during the sweep up and sweep down are roughly parallel. At a certain point in the depletion region, the curves are no longer parallel and tend toward the same accumulation capacitance. The voltage difference between the two sweeps at the capacitance where they start to not be parallel in the depletion region is then related to the number of defects present. The energy over which these defects spread is simply twice the difference between the Fermi level and the intrinsic Fermi level. The average defect density over a large portion of the bandgap was [Table 2]: Average defect densities calculated at various temperatures for n- channel 4H- SiC lateral MOSFETs.

50 45 calculated at various temperatures for this device. In order to compare oxide treatments, a second n- channel 4H- SiC lateral MOSFET was examined with the same dimensions and no treatment of the oxide. A similar procedure was implemented to determine the average defect density across the middle of the band gap. Table 2 gives the results for the Jenq technique implemented on the two SiC MOSFETs. There is a clear difference between the two devices in the number of defects present over most of the band gap. The voltage difference is proportional to the number of defects present. The MOSFET with the dry oxide had significantly larger voltage shifts at every temperature measured. Note that the energy ranges of the average defect densities were similar at each temperature. The dry oxide s average interface trap densities were larger than the NO annealed device, sometimes by as much as a factor of 2. This shows that the inclusion of an NO annealing treatment in the oxide growth lends to a smaller defect density over most of the bandgap. Also, when comparing the defect densities at 400K and 155K in both devices, an increase of more than a factor of two is observed over a small increase in the energy. It can be concluded that there are large defect densities in both of these devices near the band edges. Since this increase in defect density was by the same factor in both devices, it could point to the same kinds of defects present in both these devices. To illustrate how much of the bandgap was covered, 4H- SiC s bandgap is 3.23 ev and the energy spread of this measurement got as large as 3.17 ev. These observations, indicating larger interface defect densities in the dry oxides, are in agreement with current literature and the Cochrane EDMR results.

51 46 The Gray- Brown method was attempted on these two 4H- SiC MOSFETs. Figure 18 shows the entire CV measurement, but the Gray- Brown method only requires the sweep down into inversion. Therefore, only the first sweep was plotted for the six temperatures measured. These temperatures range from 155K to 400K at 50K intervals. Figure 19 shows the CV curves measured for the n- channel 4H- SiC MOSFET with the NO annealing treatment. These results were unusual and unexpected because of the CV curves trend in the accumulation region. Qualitatively, the results are as expected because the curves all sweep from accumulation to inversion and relative shifts in the flatband voltages were observed. The problem arises in the oxide capacitance in the accumulation region. Over the range of temperatures in this thesis, the capacitance in the accumulation region should remain constant. The shifts shown in figure 19 are not negligible and make [Figure 19]: CV curves at various temperatures for the n- channel 4H- SiC MOSFET with NO annealing treatment.

52 47 [Figure 20]: CV curves over a range of temperatures for a n- channel 4H- SiC MOSFET with a dry oxide. Gray- Brown calculations very questionable since the oxide capacitance is different for each measured CV curve. The same procedure was applied to the SiC MOSFET with a dry oxide and the results are displayed in figure 20. Again, the results show a trend qualitatively similar to that expected, but as with the NO annealed device, there exists the same problem of varying capacitances in the accumulation region. There is another unusual characteristic noticed in these dry oxide CV curves. All of the capacitances in the inversion region are higher than the capacitance in the accumulation region. The capacitance in the accumulation region can be associated with the capacitance of the oxide. This oxide capacitance is a property of the material and therefore should limit the maximum capacitance possible in the CV curve.

53 48 [Figure 21]: Defect densities calculated for both SiC MOSFET devices. The defect density calculations were carried out on both of these devices and the results are shown in figure 21. It is important to note that these defect densities are not reliable; however, the calculations were carried out and illustrated in the figure. The problems that caused the anomalies in the Gray- Brown CV measurements have yet to be resolved. The remainder of the academic semester will be spent trying to rectify this issue. Brad Bittel, a graduate student in the lab, has made CV measurements on devices similar to the ones looked at in this thesis and had no problems with the capacitance in accumulation. Retesting and reexamining these devices may resolve these problems.

54 49 VI. Conclusion CV curves were measured at various temperatures for the following four devices: n- type 4H- SiC thin oxide MOS capacitor with NO annealing, n- type 4H- SiC thin oxide capacitor with dry oxide, n- channel 4H- SiC MOSFET with dry oxide, and n- channel 4H- SiC MOSFET with NO annealing. Neither the Jenq technique nor the Gray- Brown technique provided reliable results on the first two devices because of issues with the capacitance in the accumulation region. However, the Jenq technique did provide results that appear to be physically reasonable on the SiC MOSFETs. The average defect densities on these devices were found to be lower in the NO annealed device over comparable energy ranges. An overall relationship was drawn between oxide treatments and interface states in most of the bandgap. The NO annealing showed lower average defect densities, although the specific defect densities at points within the bandgap could not be determined.

55 50 VII. Future Work There are several short term and long term work planned after this thesis in order to further study the defect densities in SiC devices. This thesis provided a start to examining the effect of manufacturing parameters on the defect densities in SiC devices. A wider breadth of devices must be examined for a truly comprehensive study. Also, these additional devices must be compatible with both the Gray- Brown method and the Jenq technique so that defect densities can be determined at energies throughout the band gap. First and foremost, the problems associated with varying accumulation capacitances must be addressed. The rest of this semester will be spent investigation the problem associated with the separation in the oxide capacitances and several more devices will be looked at to try and get a quantitative Gray- Brown analysis to compliment the Jenq technique. Also, a more portable variable temperature system has been in development and is currently being built. Figure 22 shows the device in its current state of the development process. The device is much smaller than the current variable temperature system and offers [Figure 22]: Picture of a compact variable temperature system being developed. several more advantages. With two inlets at the top, it would be possible

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