There s Plenty of Room at the Bottom and at the Top

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1 14 nm chip X SEM from bohr 2014 idf presentation.pdf There s Plenty of Room at the Bottom and at the Top Tsu Jae King Liu Department of Electrical Engineering and Computer Sciences University of California, Berkeley August 16, 2016 SFBA Nano Seminar

2 Outline Introduction Transistor scaling limit Extending the Era of Moore s Law Beyond Moore: Mechanical Computing Redux Summary 2

3 MOSFET Operation: Gate Control Metal Oxide Semiconductor (MOS) Field Effect Transistor (FET) Gate length, L G Current flowing between Source & Drain is controlled by the Gate voltage. Desired characteristics: High ON current Low OFF current n(e) exp ( E/kT) Electron Energy Band Profile log I D I ON increasing E Source Inverse slope is subthreshold swing, S increasing I OFF [mv/dec] V GS Drain 0 GATE VOLTAGE V TH distance V DD 3

4 CMOS Circuits S CIRCUIT SYMBOLS N-channel MOSFET G D P-channel MOSFET S G D CMOS NAND GATE CMOS INVERTER CIRCUIT V DD V IN GND S ON D D OFF S V OUT V DD V OUT 0 V DD INVERTER LOGIC SYMBOL V IN STATIC MEMORY (SRAM) CELL NOT AND (NAND) TRUTH TABLE WORD LINE BIT LINE 0 1 or or 1 0 BIT LINE 4

5 Improving I ON /I OFF Gate log I D I ON C ox C dep S C C total ox Source Body Drain The greater the capacitive coupling between Gate and channel, the better control the Gate has over the channel potential. higher I ON /I OFF for fixed V DD, or lower V DD to achieve target I ON /I OFF reduced short channel effect and drain induced barrier lowering: log I D V DD V GS Source decreasing L G, or increasing V DS Drain decreasing L G or increasing V DS I OFF V GS 5

6 FinFET/Tri Gate Transistor H fin L G W fin GATE Source Gate 10 nm SOURCE Drain D. Hisamoto et al. (UC Berkeley), IEDM nm L g FinFET 20 nm DRAIN log I D V DD I ON V GS Superior gate control higher I ON /I OFF or lower V DD Multiple fins can be connected in parallel to achieve higher drive current. Y. K. Choi et al., (UC Berkeley) IEDM 2001 Intel Corp., May

7 3 D Transistor Technology Roadmap Year: Intel Technology Node 22 nm 14 nm 10 nm Year: 2015 Foundry Technology Node: 14 nm 10 nm 7 nm Gate length, L G 25 nm 20 nm 15 nm Fin width, W fin ~10 nm ~8 nm ~6 nm Equivalent oxide thickness 0.9 nm 0.85 nm 0.8 nm X SEM Images Gate Gate Si SiO 2 SiO 2 C. Auth et al. (Intel Corp.) VLSI Symp Si SiO 2 Si S. Natarajan et al. (Intel Corp.) IEDM

8 MOSFET Evolution 32 nm planar FinFET: 22 nm thin body beyond 7 nm stacked nanowires? P. Packan et al. (Intel), IEDM 2009 FD SOI: Intel Corp. K. Cheng et al. (IBM), VLSI Symp C. Dupré et al. (CEA LETI) IEDM 2008 Stacked gate all around (GAA) FETs achieve the highest layout efficiency. 8

9 Channel Length Scaling Limit Quantum mechanical tunneling sets a fundamental scaling limit for the channel length (L C ). If electrons can easily tunnel through the source potential barrier, the gate cannot shut off the transistor. nmosfet Energy Band Diagram (OFF state) SOURCE DRAIN E C J. Wang et al., IEDM Technical Digest, pp , 2002 E C 9

10 Ultimately Scaled MOSFETs M. Luisier et al., IEDM 2011 L G = 5 nm 10

11 Outline Introduction Extending the Era of Moore s Law Beyond Moore: Mechanical Computing Redux Summary 11

12 Multiple patterning techniques have extended Moore s Law beyond the lithographic resolution limit at increasing cost Normalized Cost and Steps Single Exposure Cost Steps LELE Single Spacer Samsung, EUVL Symposium 2009 ASML, SPIE Advanced Lithography 2012 Double Spacer The sheer cost and complexity of this lithographic solution could dissuade chipmakers from jumping to future nodes, thereby stunting the growth rates of the IC industry. Semiconductor Engineering, April 17 th, /25/2016 Sang Wan Kim 12 12

13 Tilted ion implantation (TII) Approach A sub lithographic damage region can be achieved by tilted ion implantation (TII) + photoresist/hard mask self aligned to pre existing mask features on surface 13

14 Impact of TII on SiO 2 Etch Rate S. W. Kim et al. (UC Berkeley), SPIE Advanced Lithography 2016 Ar + implant conditions: 15 tilt; 1.5 kev; dose = 0, 2 or 3 x /cm Etch rate [Å/sec] 1.5 3E14 2E14 ~6X ~9X no implant SiO 2 Depth [Å] 3E14 2E Damage [x10 22 /cm 3 ] Symbols & solid lines: etch rate in 200:1 DHF Dotted lines: damage profile (SRIM) 14

15 Double Patterning by TII θ Thermal SiO 2 : masking layer Formation of linear a-si hard-mask features by spacer patterning hard mask Si y First implant: positive tilt angle x W trench y(tan(θ) cot(α)) α α SiO 2 x x Silicon W trench 15

16 Double Patterning by TII Thermal SiO 2 : masking layer Formation of linear a-si hard-mask features by spacer patterning hard mask First implant: positive tilt angle x W trench y(tan(θ) cot(α)) Second implant: negative tilt angle x W trench y(tan(θ) cot(α)) SiO 2 16

17 Double Patterning by TII Thermal SiO 2 : masking layer Formation of linear a-si hard-mask features by spacer patterning hard mask Si y First implant: positive tilt angle x W trench y(tan(θ) cot(α)) α Second implant: negative tilt angle x W trench y(tan(θ) cot(α)) SiO 2 x W fin x x Silicon W fin x Selective removal of damaged SiO 2 Si substrate dry etch W fin 2y(tan(θ) cot(α)) W trench 17

18 Proof of Concept: Single Implant S. W. Kim et al. (UC Berkeley), SPIE Advanced Lithography 2016 Cross sectional Scanning Electron Micrographs Ar-ion implantation with θ = etched a-si remaining a-si Si substrate Si substrate Sub lithographic features (~45 nm) achieved by 15 tilt, 3.0 kev Ar + implant into 10 nm thick SiO 2 hard mask dilute HF etch Si dry etch 18

19 Self Aligned Nature of TII Patterning P. Zheng et al. (UC Berkeley), to be published The TII defined edge closely tracks the HM edge = a Si hard mask = un etched c Si = etched c Si 19

20 Line Edge Roughess Comparison P. Zheng et al. (UC Berkeley), to be published 36 samples, 2.74 µm long TII improves low and mid frequency line edge roughness 20

21 Double Tilted Implant Results S. W. Kim et al. (UC Berkeley), SPIE Advanced Lithography 2016 Cross-sectional SEM Plan-view SEM 1 15 LTO 3 a-si 2 Si substrate Local pitch halving achieved with ±15 tilt, 3.0 kev Ar + implants ~21 nm half pitch of the etched Si features 21

22 Double Patterning Approaches Spacer lithography (SADP) Tilted Ion Implantation (TII) Hard mask (CVD) SiO 2 (Oxidation) Silicon SiO 2 (Oxidation) Silicon SiO 2 (Oxidation) Silicon Silicon Silicon 22

23 Cost Comparison P. Zheng et al. (UC Berkeley), to be published Self-aligned Double Patterning TII Double Patterning Process Steps Cost Process Steps Cost Process Description (a.u./wafer) Process Description (a.u./wafer) PECVD Etch stop layer 1.5 LPCVD Mask layer 2 CVD Mandrel layer 2 CVD Mandrel layer 2 Photolithography Patterning 30 Photolithography Patterning 30 Dry etch Mandrel etch 10 Dry etch Mandrel etch 10 ALD Spacer deposition 3 Ion implantation Double implants 1.7 Spacer etch Wet etch Selective mask etch 1 Dry etch 16 Mandrel pull Mandrel removal Dry etch 16 Wet clean Clean 1 Pattern transfer Dry etch Pattern transfer Wet etch Mask removal 1 16 Pattern transfer Wet etch Spacer removal 1 Wet etch Etch stopper strip 1 Total: 81.5 Total: 63.7 If photoresist is used as the mandrel layer, the cost of TII double patterning can be only ~50% of the cost of SADP. 23

24 Outline Introduction Extending the Era of Moore s Law Beyond Moore: Mechanical Computing Redux Summary 24

25 Impact of Moore s Law Investment Transistor Scaling Lower Cost/Component Higher Performance Market Growth Mobile Internet Internet of Things (IoT) # DEVICES Mainframe Minicomputer Desktop Internet PC Source: Morgan Stanley Research YEAR 25

26 A Vision of the Future Ultra low power chips required! The Cloud (millions) Mobile devices (billions) The Swarm (trillions) Source: J. Rabaey, ASPDAC

27 Micro Electro Mechanical Switch Zero off state leakage Zero passive energy consumption Abrupt switching behavior Low V DD (low active energy) Three Terminal Switch OFF State: Measured I V Characteristic V min Source ON State: Gate F spring Drain F elec F adhesion 27

28 Surface Micromachining Process Cross sectional View structural film sacrificial layer Si wafer substrate Mechanical structures can be made using conventional microfabrication techniques Structures are freed by selective removal of sacrificial layer(s) 28

29 IC Technology Advancement D. C. Edelstein, 214th ECS Meeting, Abstract #2073, 2008 Intel s 14nm CMOS technology Time Advanced back end of line (BEOL) processes have air gapped interconnects can be adapted for fabrication of compact NEMS! S. Natarajan et al. (Intel), IEDM

30 BEOL NEM Switch N. Xu et al. (UC Berkeley), 2014 IEEE International Electron Devices Meeting D1 M5 D0 V DD V DD V DD GND M4 GND M3 GND M2 INPUT courtesy of Dr. Kimihiko Kato (UC Berkeley) A relay can be implemented using multiple metal layers Vias can be used for electrical connection and as torsional elements for lower k eff Actuation electrodes on opposite sides of movable electrode structure 2 stable states (contacting D0 or D1) Low voltage (<1 V) operation can be achieved with small footprint (< 0.1 m 2 ). 30

31 Non Volatile Device Comparison N. Xu et al. (UC Berkeley), 2014 IEEE International Electron Devices Meeting A bi stable NEM switch is projected to operate with much less energy and delay than other non volatile switching devices can be used to continually shadow the information stored in an SRAM cell 31

32 In Memory Computing K. Kato et al., IEEE Electron Device Letters, Vol. 37, pp , 2016 NV NEMory cell array for memory based super parallel data searching Data Data Data Data4 Not programmed DL0 BL 1 BL 2 BL 3 BL 4 WL 1 DL1 WL 2 DL0 WL 3 DL1 WL 4 DL0 A A A A 32

33 Non Volatile NEMory Cell Structure K. Kato et al., IEEE Electron Device Letters, Vol. 37, pp , 2016 DL0 Beam 8F 2 F F AL0 DL1 DL1 / AL1 F F AL1 BL F F DL0 / AL0 Deformation direction BL Diffusion WL Float DL DL 0 1 Deformed beam AL AL 0 1 GND V prog Metal: Al (Young s modulus: 70 GPa) Gap: Air Year Half pitch, F (nm)

34 Data Search Step 1: Match 0 Reference Data: 1100 K. Kato et al., IEEE Electron Device Letters, Vol. 37, pp , 2016 Data Data Data Data4 Not programed DL 0 BL 1 BL 2 BL 3 BL 4 DL 1 DL 0 DL 1 DL 0 BL 1 BL 2 BL 3 BL 4 a) Activate DL1 lines b)access rows for 0 bits in reference c) Zero BL current Matched 0s A A A A 34

35 Data Search Step 2: Match 1 Reference Data: 1100 K. Kato et al., IEEE Electron Device Letters, Vol. 37, pp , 2016 Data Data Data Data4 Not programed DL 0 BL 1 BL 2 BL 3 BL 4 DL 1 DL 0 DL 1 DL 0 WL 1 WL 2 WL 3 WL 4 a) Activate DL0 lines b)access rows for 1 bits in reference c) Zero BL current Matched 1s A A A A 35

36 Energy and Delay for Data Search K. Kato et al., IEEE Electron Device Letters, Vol. 37, pp , 2016 Cells involved: NV NEMory Array 1 column 1 row Energy 1 column 256 rows 256 columns 256 rows Delay Program (V prog = 2.5 V) 15 fj 2.0 pj N/A < 10 ns Match 0 or Match 1 N/A N/A 1.2 pj < 0.2 ns The location of a data string can be found in <0.5 ns with less than 2.5 pj. For a die size of 42 mm 2 (same as DDR4 DRAM) at F = 20 nm and cell density of 65% (similar to DRAM), a NV NEMory chip would have the capacity 8 Gb and would consume only 300 nj to find a match on the whole chip. In comparison, it would take CPU+DRAM ~90 mj, 80 ms for the same task. Relatively fast read speed & low power consumption make NV NEMory technology well suited for real time data searching applications! 36

37 Outline Introduction Extending the Era of Moore s Law Beyond Moore: Mechanical Computing Redux Summary 37

38 Summary Tilted ion implantation (TII) is an effective sublithographic patterning and pitch halving technique features are self aligned to pre existing mask process flow is much simpler (lower cost) than SADP shows promise for extending Moore s Law! Electronic devices which enable more energyefficient computation and data storage, at ever lower cost per function, will be required for ubiquitous computing. BEOL NEM devices show promise in this regard 38

39 Acknowledgements TII Enhanced Lithography: Dr. Sang Wan Kim (UC Berkeley) Dr. Peng Zheng (now with Intel Corporation) Dr. Leonard Rubin (Axcelis Technologies) UC Berkeley Marvell Nanofabrication Laboratory Funding from Applied Materials, Lam Research BEOL NEM Relays Technology: Dr. Nuo Xu (now with Samsung Semiconductor, Inc.) Dr. Kimihiko Kato (now at University of Tokyo) Prof. Vladimir Stojanović (UC Berkeley) Funding from National Science Foundation Center for Energy Efficient Electronics Science 39